A probabilistic approach for testing large-scale integrated circuits

If the statistics available from various process steps involved in the fabrication of large-scale integrated logic circuit chips indicate that the computed probability of each circuit path operating properly is greater than 1/2, then a reliable screening test procedure can be devised. A reliable reference standard from untested chips, or modules, can be constructed, and such a standard reference can be used in all test procedures in which circuit testing is based on comparison.     

Discrete compensation of control systems with integrated circuits

This paper combines the compensation of control systems with transient analysis and switching circuit theory to accomplish the discrete compensation of control systems. Several transfer functions are used as examples, and their realizations are discussed in detail. Lead and lag compensation are used, and several general transfer function realizations are presented for clarity. All of the realizations have been implemented with methods suitable for complete circuit integration, i.e., the logic circuits required for implementation are all commonly available in large quantities on a single integrated circuit chip.     

A pipelined image analysis system using custom integrated circuits

The requirements of a computer vision system in relation to industrial applications are studied. It is concluded that for the iconic image-processing part, a pipeline system built around a custom integrated circuit is preferred. This custom integrated circuit makes it possible to realize four basic operations in a compact way: shape recognition, mask generation, programmable image delay, and subsample filtering. An example that has been processed by a hardware realization of such a pipeline system is provided     

AMOLED displays with transfer‐printed integrated circuits

Abstract— Small integrated circuits of crystalline silicon (chiplets) transfer‐printed onto a flat‐panel‐display substrate provide greatly improved electrical performance and uniformity in active‐matrix organic light‐emitting‐diode (OLED) displays. The integrated circuits are formed in high‐performance crystalline silicon using conventional photolithographic processes and then transfer‐printed onto a substrate using a stamp that transfers hundreds or thousands of chiplets at once. The chiplets are connected to an external controller and to pixel elements using conventional photolithographic substrate processing methods. Active‐matrix OLED (AMOLED) displays using transfer‐printed chiplets have good yields, excellent uniformity, and electrical performance and are thermally robust.     

Novel yield model for integrated circuits with clustered defects

As wafer sizes increase, the clustering phenomenon of defects increases. Clustered defects cause the conventional Poisson yield model underestimate actual wafer yield, as defects are no longer uniformly distributed over a wafer. Although some yield models, such as negative binomial or compound Poisson models, consider the effects of defect clustering on yield prediction, these models have some drawbacks. This study presents a novel yield model that employs General Regression Neural Network (GRNN) to predict wafer yield for integrated circuits (IC) with clustered defects. The proposed method utilizes five relevant variables as input for the GRNN yield model. A simulated case is applied to demonstrate the effectiveness of the proposed model.     

A hardware digital fuzzy inference engine using standard integrated circuits

The paper describes a general-purpose board-level fuzzy inference engine intended primarily for experimental and educational applications. The components are all standard TTL integrated circuits (7400 series) and CMOS RAMs (CY7C series). The engine processes 16 rules in parallel with two antecedents and one consequent per rule. The design may easily be scaled to accommodate more or fewer rules. Static RAMs are used to store membership functions of both antecedent and consequent variables. “Min-max” composition is used for inferencing, and for defuzzification, the mean of maxima strategy is used. Simulation on VALID CAE software predicts that the engine is capable of performing up to 1.56 million fuzzy logic inferences per second.     

A survey on design and synthesis techniques for photonic integrated circuits

The Journal of Supercomputing - In recent years, silicon photonics (Si-photonics) have received significant attention among researchers due to complementary metal-oxide semiconductor compatibility,...     

Noise estimation for deep sub-micron integrated circuits

Noise analysis and avoidance are an increasingly critical step in the design of deep sub-micron (DSM) integrated circuits (ICs). The crosstalk between neighboring interconnects gradually becomes the main noise sources in DSM ICs. We introduce an efficient and accurate noise-evaluation method for capacitively coupled nets of ICs. The method holds for a victim net with arbitrary number of aggressive nets under ramp input excitation. For common RC nets extracted by electronic design au-tomation (EDA) tools, the deviation between our method and HSPICE is under 10% .     

三维芯片制造成本分析

三维芯片由于其集成度高、功耗小、性能好等优点成为未来芯片制造的一种趋势,其制造成本问题成为该技术是否有应用前景的关键。分析了三维芯片的制造成本模型,并通过实验数据得到了三维芯片的成本最优划分方式;然后对多核处理器的二维芯片和三维芯片制造成本进行了对比,证明了在核数较大的情况下三维芯片制造成本的优势,说明三维芯片在未来芯片门数越来越多的情况下有很好的应用前景。     

A 6.94-in. WVGA poly-Si TFT-LCD with integrated driver including sequential analog sampling circuits

By the integrated drive circuitry with laser crystallization process, the gate and data driver circuits required for full color WVGA(800 × RGB × 480) LCD are integrated on panel. The integrated driver comprises a sequential analog sampling data driver and a dual logic gate scanner for redundancy. The characteristics and uniformities of the LTPS (low temperature polycrystalline silicon) devices have been remarkably enhanced by applying stacked SiO₂ and SiN_x buffer layers and surface treatment.     

Techniques for synthesis of analog integrated circuits

The CAD tools that have been developed for automated analog synthesis are reviewed. The synthesis process is described. The major techniques employed by the tools are examined. They are knowledge-based hierarchical design, analytic design, and placement/routing. Critical design issues are identified. It is shown how the technique discussed could be combined in a comprehensive framework supporting design from specification to physical layout     

Optimal repair decisions for integrated circuits manufacturing

The sequential manufacturing process has been widely applied to the making of complicated integrated circuits (IC). The basic idea is to break an IC product line into a linear sequence of simple operations, and then, a final product with desired high complexity can be obtained by performing the individual operations step by step. To assure the quality of the in-process products, we may conduct a test after each operation. When an in-process product is fault-free, it will pass the test and be moved to the next operation. On the other hand, for a defective in-process product which fails the test, we have to make a decision to either scrap or repair it so that no fault propagates to later operations. The repair/scrapping decisions certainly affect the manufacturing cost. Our goal is to find a set of optimal repair decisions so that the total manufacturing cost per fault-free IC product is minimized. For an IC product line with n sequential operations, there are 2ⁿpossible decision combinations in total. In this paper, we introduce a dynamic programming approach with an algorithm of 0(n₂) complexity to solve the problem.     

集成电路引线的电阻、电流和电位

讨论集成电路内引线的设计.在一定电压下,利用Maple数学软件包为0.2μm长度的光滑内引线绘制了宽度为0.1μm时电阻和电流与不同高度的关系.内引线指定与集成电路AD8622的发射极相连接,因此流过此内引线的电流为Isr=0.350mA.于是确定了0.2μm长度的光滑内引线的两端电压降为0.2mV.当内引线长度为n×0.2μm时,两端电压降为n×0.2mV.本文提出,当引线中流过电流I(/mA)时,不同引线长度L(μm)、宽度W(μm)、和高度h(μm)引线两端所应加的设计电压的一个普适的简式:AU=0.2×I×0.1×L×0.061/(0.35W×0.2h) (mV).同L时要求引线长度方向上△U/L在几mV/μm数量级以下.当引线中有气泡时,在此电压下,讨论了气泡的半径对其电阻、电流的影响.获得了引线中的电流分布,并指出在引线中气泡的最大突起半径外缘电流表现出拥挤和气泡的半径对全引线电阻的影响.所提供的有关数据可用于集成电路内引线的设计.     

Placement and routing in 3D integrated circuits

Three-dimension technologies offer great promise in providing improvements in the overall circuit performance. Physical design plays a major role in the ability to exploit the flexibilities offered in the third dimension, and this article gives an overview of placement and routing methods for FPGA- and ASIC-style designs. We describe CAD techniques for placement and routing in 3D ICs, developed under our 3D analysis and design optimization framework. These approaches address a dichotomy of design styles, both FPGA and ASIC. The factors that are important in each style are different, so that a one-size-fits-all approach is impractical, and therefore, we present separate approaches for 3D physical design for each of these technologies. Hence, our FPGA placement method uses a two-step optimization process that minimizes inter-tier vias first, followed by further optimization within and across tiers. In contrast, the ASIC flow uses cost function weighting to discourage, but not minimize, inter-tier crossings.     

An image-recognition system using algorithmically dedicated integrated circuits

An image-recognition system was implemented with a set of eight algorithmically dedicated integrated circuits to recognize two-dimensional objects that are characterized by their closed outer contours. The complete system operates at rates up to 15 frames/second using a standard workstation as a controller. The recognition system achieved a 97% recognition rate for over 10,000 trials of recognition of eight objects over a wide range of orientation and size variations. A 100% recognition rate was achieved if size variations were eliminated. The set of 4-micron NMOS image processor chips operates on 10-megahertz 8-bit video data (512 × 512 images) in real time. The processors include: a 3 × 3 linear convolver, a 3 × 3 sorting filter, a 7 × 7 logical convolver, a contour tracer, a feature extractor, a look-up table ROM, and two post-processors for the linear convolver. Each chip was designed using an architecture that is dedicated to the particular image processing task being performed. The design time for all of the chips was kept to 1.5 man-years by developing a set of design guidelines. The relationship between the algorithms that were implemented and the silicon implementation is discussed.     

Analog integrated circuits for the Lotka-Volterra competitiveneural networks

A subthreshold MOS integrated circuit (IC) is designed and fabricated for implementing a competitive neural network of the Lotka-Volterra (LV) type which is derived from conventional membrane dynamics of neurons and is used for the selection of external inputs. The steady-state solutions to the LV equation can be classified into three types, each of which represents qualitatively different selection behavior. Among the solutions, the winners-share-all (WSA) solution in which a certain number of neurons remain activated in steady states is particularly useful owing to robustness in the selection of inputs from a noisy environment. The measured results of the fabricated LV ICs agree well with the theoretical prediction as long as the influence of device mismatches is small. Furthermore, results of extensive circuit simulations prove that the large-scale LV circuit producing the WSA solution does exhibit a reliable selection compared with winner-take-all circuits, in the possible presence of device mismatches.