A new field dependent mobility model for high frequency channel thermal noise of deep submicron RFCMOS

In this paper, a new field dependent effective mobility model including the drain-induced vertical field effect (DIVF) is presented to calculate the channel thermal noise of short channel MOSFETs operating at high frequencies. Based on the new channel thermal noise model, the simulated channel thermal noise spectral densities have been compared to the channel thermal noise directly extracted from noise measurements on devices fabricated using GLOBALFOUNDRIES’ 0.13 μm RFCMOS technology. The comparison has been done across different channel length, finger width and number of finger for different frequencies, gate biases and drain biases. Excellent agreement between simulated and extracted noise data has shown that the proposed model is scalable over different dimensions and operating conditions. The proposed model is simple and can be easily implemented in a circuit simulation environment.     

Analytical and experimental studies of thermal noise in MOSFET's

An analysis of the channel thermal noise in MOSFET's based on the one-dimensional charge sheet model, is presented. The analytical expression is valid in the strong, moderate, and weak inversion regions. The body effect on the device parameters relevant to the thermal noise is discussed. A measurement technique as well as experimental results of P- and N-MOSFET's of a 1.2 μm radiation hard CMOS process are presented. The calculated channel thermal noise coefficient γ as in i_d²/Δf=4kT γ g_do, agrees well with experimental data for effective device channel length as short as 1.7 μm     

The gate bias and geometry dependence of random telegraph signalamplitudes [MOSFET]

A new random telegraph signal (RTS) amplitude model based upon band bending fluctuations has been developed, in contrast to other studies of RTS noise amplitudes, which are derived from RTS fitting parameters, it is demonstrated in this work that noise amplitudes may be predicted from band bending calculations and device DC characteristics. This new model suggests that the decrease in band bending associated with slow-state trapping results in mobility degradation for low gate biases (Coulombic-scattering-limited) and an enhancement in mobility due to vertical field reductions at high gate biases (surface roughness/phonon scattering limited). The band bending formulation shows good correlation with experimental data and accurately predicts the observed dependence upon effective channel length and width     

Low-Frequency Noise Partition of Asymmetric MOS Transistors Operating in Linear Regime

The low-frequency noise in asymmetric MOS transistors with graded channel doping from the source to the drain can be partitioned by assuming a series connection of two or more transistors along the device's channel length. The partition explains the noise overshoot at gate biases around the threshold voltage of the composite device. Expressions for the input-referred gate noise voltage are obtained and verified.      

Static and low frequency noise characterization of surface- and buried-mode 0.1 μm P and N MOSFETs

This work presents the low frequency noise and the electric performances in terms of output/transfer characteristics, threshold voltage, and short channel effect in both NMOS and PMOS transistors for 0.1 μm technologies. For the last one there are two architectures based either on a surface mode of operation (surface channel) or on a buried one (buried channel) featuring either a P+ or a N+ polysilicon gate material. The impact of the channel length on the noise characteristics as well as on the output/transfer characteristics is studied. We find that the 1/f noise can be interpreted in terms of carrier number fluctuations for both N and P channel MOSFETs for surface and buried mode of operation. The oxide trap density Nt is therefore evaluated, demonstrating an overall good oxide quality.     

Static and low frequency noise characterization of surface- and buried-mode 0.1 μm P and N MOSFETs

This work presents the low frequency noise and the electric performances in terms of output/transfer characteristics, threshold voltage, and short channel effect in both NMOS and PMOS transistors for 0.1 μm technologies. For the last one there are two architectures based either on a surface mode of operation (surface channel) or on a buried one (buried channel) featuring either a P+ or a N+ polysilicon gate material. The impact of the channel length on the noise characteristics as well as on the output/transfer characteristics is studied. We find that the 1/f noise can be interpreted in terms of carrier number fluctuations for both N and P channel MOSFETs for surface and buried mode of operation. The oxide trap density Nt is therefore evaluated, demonstrating an overall good oxide quality.     

Analysis of flicker and thermal noise in p-channel Underlap DG FinFET

In this paper, we analyze the flicker and thermal noise model for underlap p-channel DG FinFET in weak inversion region. During the analysis of current and charge model, minimum channel potential i.e. virtual source is considered. Initially, the drain current for both long and short channel of DG FinFET are evaluated and found to be well interpreted with experimental results. Further, the flicker and thermal noise spectral density are derived. The flicker noise power spectral density is compared with published experimental results, which shows a good agreement between proposed model and experimental result. During calculation we have considered variation of scattering parameter and furthermore, the degradation of effective mobility is taken into account for ultrathin body. The variation of structural parameters such as gate length (L_g), body thickness (t_Si) and underlap length (L_un) are also considered. The degradation of gate noise voltage with frequency, underlap length and gate length signify that p-channel DG FinFET device can be a promising candidate for analog and RF applications.     

Analytical modeling of flicker and thermal noise in n-channel DG FinFETs

A compact physics-based thermal and flicker noise model has been developed for n-channel Double Gate FinFETs with varying structural parameters. The effects of mobility degradation due to velocity saturation, carrier heating and channel length modulation have been incorporated for an accurate modeling of noise. The mobility fluctuations dependent on the inversion carrier density have been considered and a characteristic of the flicker noise different from that of Bulk MOSFETs was observed. This has been validated by the experimental results. Based on the proposed thermal and flicker noise model, a compact expression of the corner frequency has been derived and the effects of the structural parameters such as the length and the thickness of the channel have been analyzed. Finally, the model has been applied for p-channel devices and noise behavior in accordance with experimental data has been obtained.     

一种深亚微米MOSFET高频噪声模型

基于深亚微米MOSFET的短沟道效应(迁移率退化、热载流子效应、体电荷效应、沟道长度调制效应等),提出了一种高频沟道噪声分析模型.该分析模型不仅具有较高的精确性,而且只包括MOSFET的工艺参数和电学参数,不含有微积分和拟合参数,较大地提高了MOSFET高频噪声模型的易用性.根据MOSFET的高频等效电路,得出了MOSFET的噪声系数模型.实验结果证明,提出的深亚微米MOSFET高频噪声模型的仿真结果与测试结果的平均误差不到0.4 dB,并与其他高频沟道噪声分析模型进行了比较.     

Pocket implantation effect on drain current flicker noise in analog nMOSFET devices

The pocket implantation effect on drain current flicker noise in 0.13 /spl mu/m CMOS process based high performance analog nMOSFETs is investigated. Our result shows that pocket implantation will significantly degrade device low-frequency noise primarily because of nonuniform threshold voltage distribution along the channel. An analytical flicker noise model to account for a pocket doping effect is proposed. In our model, the local threshold voltage and the width of the pocket implant region are extracted from the measured reverse short-channel effect, and the oxide trap density is extracted from a long-channel device. Good agreement between our model and the measurement result is obtained without other fitting parameters.     

Performance of DS/SSMA Communications in Impulsive Channels--Part I: Linear Correlation Receivers

The performance of digital linear correlation receivers is studied in a multiuser environment. There are assumed to be two types of sources interfering with data transmission: multiple-access interference, and additive channel noise which is attributed to impulsive noise sources in the environment. The contribution of multiple-access interference is examined by consideringKasynchronous users transmitting simultaneously over a linear channel using the binary PSK direct-sequence spreadspectrum multiple-access (DS/SSMA) technique. Alternatively, the effects of the non-Gaussian impulsive channel in such a system are studied by modeling the samples of noise after front-end filtering. Errorprobability performance under these conditions is compared to that for additive white Gaussian noise (AWGN) channels. Due to computational complexity, exact analysis is limited here to systems utilizing short spreading sequences. Computationally simple methods are proposed for approximating the average error probability when the length of the signature sequences is large. Furthermore, some asymptotic results are obtained for the case of infinitely long sequences. In all cases, performance variation is examined as the shape of the noise density varies with SNR held constant. The results of this analysis indicate that the presence of impulsive noise can cause significant performance degradation over that predicted from an AWGN model, even when the total noise power does not increase.     

General noise considerations for gigabit-rate NMOSFET front-end design for optical-fiber communication systems

Receiver design noise considerations for FET front ends for fiber-optics amplifiers as presented by Smith and Personick are revisited. The MOSFET noise model used is simple yet more accurate than that used previously. The device equivalent circuit for noise is derived from first principles. We are thus able to optimize the amplifier sensitivity with respect to hot-carrier channel thermal noise in terms of the FET drain-to-source voltage and the effective channel length. The importance of drain-source overlap capacitance in determining amplifier sensitivity, which has hitherto not been formulated, is also quantified. It is thus concluded that in spite of hot-carrier noise effects, fine-line NMOS amplifiers designed for gigabit-rate applications will continue to see sensitivity improvement for effective channel lengths down into the quarter-micrometer range. Investigation in the subquarter-micrometer range is in progress.     

Extraction of bias-dependent parasitic source/drain resistance in MOSFETs with an advanced mobility model

We present a new method to extract gate-bias-dependent source/drain resistance in MOSFETs. The extraction starts from a simple mobility model, but a more sophisticated mobility model is incorporated afterward. The method provides a convenient way to extract the source/drain resistance as well as parameters in a sophisticated mobility model. The extracted parameters in the mobility model vary with channel length. To satisfy some device modeling work where parameters independent of channel length are desirable, we also develop another technique so that a single set of parameters is obtained and is applicable to all channel lengths. The extraction techniques are useful for submicron MOSFETs without going through complicated procedure.     

Temperature Dependence of High Frequency Noise Behaviors for RF MOSFETs

For the first time, the temperature dependences of radio frequency (RF) metal oxide semiconductor field effect transistors' intrinsic noise currents, including the induced gate noise current $(i_{g})$, channel noise current $(i_{d})$ and their correlation noise current, are experimentally investigated. The power spectral densities for the induced gate noise current and correlation noise current are found to rise as temperature increases, and decline for the channel noise current. Moreover, by using van der Ziel's noise model, our experimental results show that, besides ambient temperature, the channel conductance is the main factor dominating the RF noise behaviors. Finally, bias dependence results are also presented.      

A New Lossy Substrate Model for Accurate RF CMOS Noise Extraction and Simulation With Frequency and Bias Dependence

A lossy substrate model is developed to accurately simulate the measured RF noise of 80-nm super-100-GHz f_T n-MOSFETs. A substrate RLC network built in the model plays a key role responsible for the nonlinear frequency response of noise in 1-18-GHz regime, which did not follow the typical thermal noise theory. Good match with the measured S-parameters, Y-parameters, and noise parameters before deembedding proves the lossy substrate model. The intrinsic RF noise can be extracted easily and precisely by the lossy substrate deembedding using circuit simulation. The accuracy has been justified by good agreement in terms of I_d,g_m, Y-parameters, and f _T under a wide range of bias conditions and operating frequencies. Both channel thermal noise and resistance induced excess noises have been implemented in simulation. A white noise gamma factor extracted to be higher than 2/3 accounts for the velocity saturation and channel length modulation effects. The extracted intrinsic NF_min as low as 0.6-0.7 dB at 10 GHz indicates the advantages of super-100 GHz f_T offered by the sub-100-nm multifinger n-MOSFETs. The frequency dependence of noise resistance R_n suggests the bulk RC coupling induced excess channel thermal noise apparent in 1-10-GHz regime. The study provides useful guideline for low noise and low power design by using sub-100-nm RF CMOS technology     

A Novel Three-State ARQ Scheme for Variable Error-Tate Channels

This paper presents a new type of automatic-repeat-request (ARQ) scheme, Three-State ARQ (TS-ARQ), for error control in data transmission over a noisy channel. The new scheme is based on the Go-Back-N (GBN) protocol and uses three different methods of GBN protocols: basic GBN, n-copy GBN and continuous-GBN. The new ARQ model is applicable for channels having the variable noise level going from low through medium until very high levels. As it is known, such wireless channels are to be found in terrestrial and space (satellite) communications. This model is to be used for the estimation of the noise state in the channel and one of the methods is used, depending of the noise level. When the noise level is low GBN-ARQ is used, in the case of the medium noise level the n-copy GBN is used, and if the noise level is high continuous-GBN will be applied. This paper presents the method of determining the parameters and transfer moments from one state to another. An original mathematical model is given, together with evaluation results. These results are compared with the known methods and the conclusion that the described method provides some better performances is drowned. The implementation of this new procedure is simple as described in the flow chart given in the paper.     

Analytical modeling of thermal noise in deep submicron MOSFETs

An analytical modeling of MOSFETs channel noise is proposed by considering short-channel effects of deep submicron MOSFETs, such as mobility degradation, hot carrier, bulk charge, and channel length modulation effect. The model is only dependent on bias, size, and technology of MOSFETs, and hence is suitable for low-noise RF IC design. Noise parameters of MOSFETs are achieved and good agreement between calculated and measured results is demonstrated.     

Excess low-frequency noise in ultrathin oxide n-MOSFETs arising from valence-band electron tunneling

Low-frequency flicker noise in analog n-MOSFETs with 15-/spl Aring/ gate oxide is investigated. A new noise generation mechanism resulting from valence-band electron tunneling is proposed. In strong inversion conditions, valence-band electron tunneling from Si substrate to polysilicon gate takes place and results in the splitting of electron and hole quasi-Fermi-levels in the channel. The excess low-frequency noise is attributed to electron and hole recombination at interface traps between the two quasi-Fermi-levels. Random telegraph signals due to the capture of channel electrons and holes is characterized in a small area device to support our model.     

Analytical model and characterization of small geometry MOSFET's

Electrical characteristics of small geometry p-channel and n-channel MOSFET's are characterized based on an analytical model that includes short-channel, narrow-channel, and carrier-velocity-saturation effects. Theoretical results on threshold voltage, threshold-voltage shift by a substrate bias voltage, and drain current are in good agreement with the experimental results over wide ranges of channel lengths from 1 to 9 µm and channel widths from 2 to 14 µm. A comparison of the electrical characteristics of MOSFET's with and without field implantation leads to the conclusion that the field implantation is the main cause of the narrow-channel-width effect on threshold-voltage increase and drain-current degradation. The carrier-velocity-saturation effect starts to appear at the 3-µm channel length for the n-channel device and at 1 µm for the p-channel device under 5-V operation. According to the theoretical analysis of a 1-µm-channel inverter circuit, a CMOS inverter has superior noise immunity with 1.4 to 2.0 times larger driving-current capability in a load MOS device and requires 9 percent less area than a 1-µm n-channel enhancement/depletion inverter.     

A model for the channel noise of MESFETs including hot electron effects

Noise is an important consideration in the reliability of microelectronic circuits determining the sensitivity of the circuits and placing a lower limit on the regions of operation. Proper modeling of noise in integrated circuits is essential for reliable operation. A derivation is given for the channel noise coefficient of FET’s operating in the saturation region. Some simple approximations are made for hot electron effects which can be incorporated into the derivation and accounted for by a numerical integration technique. Experimental results of measured and calculated noise coefficients are compared for depletion mode MESFETs of different gate lengths. This model gives a much more realistic representation of the channel noise coefficients for short gate length devices rather than the simple 2/3 value currently used in circuit simulations.