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A 2.4GHz CMOS Monolithic Transceiver Front-End for IEEE 802.11b Wireless LAN Applications 总被引:4,自引:3,他引:1
A 2.4GHz CMOS monolithic transceiver front-end for IEEE 802.11b wireless LAN applications is presented.The receiver and transmitter are both of superheterodyne structure for good system performance.The front-end consists of five blocks:low noise amplifier,down-converter,up-converter, pre-amplifier,and LO buffer.Their input/output impedance are all on-chip matched to 50Ω except the down-converter which has open-drain outputs.The transceiver RF front-end has been implemented in a 0.18μm CMOS process.When the LNA and the down-converter are directly connected,the measured noise figure is 5.2dB,the measured available power gain 12.5dB,the input 1dB compression point -18dBm,and the third-order input intercept point -7dBm.The receiver front-end draws 13.6mA currents from the 1.8V power supply.When the up-converter and pre-amplifier are directly connected,the measured noise figure is 12.4dB,the power gain is 23.8dB,the output 1dB compression point is 15dBm,and the third-order output intercept point is 16dBm.The transmitter consumes 276mA current from the 1.8V power supply. 相似文献
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This paper presents a 2.4 GHz power amplifier (PA) designed and implemented in 0.35 μm SiGe BiCMOS technology. Instead of chip grounding through PCB vias, a metal plate with a mesa connecting ground is designed to decrease the parasitics in the PCB, improving the stability and the gain of the circuit. In addition, a low-pass network for output matching is designed to improve the linearity and power capability. At 2.4 GHz, a P_(1dB) of 15.7 dBm has been measured, and the small signal gain is 27.6 dB with S_(11) < -7 dB and S_(22) < -15 dB. 相似文献
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基于Tower Jazz 0.13 μm SOI CMOS工艺,提出了一种应用于无线局域网的2.4/5.5 GHz双频段低噪声放大器(LNA)。该双频段LNA基于带源极电感的共源共栅结构,在放大管栅极与共源共栅管漏极之间增加负反馈电容,以改善5.5 GHz频段的阻抗匹配。工作频段的切换通过开关控制的电感电容匹配网络实现。SOI射频开关通过增加MOS管尺寸来减小导通时的插入损耗,并且保持较低的关断电容,使开关的引入对LNA性能的影响最小化。Cadence后仿真结果表明,在2.4 GHz频段范围内,S21为10.3~10.7 dB,NF为2.1 ~2.2 dB,IIP3为5 dBm;在5.5 GHz频段范围内,S21为9.7 ~11.8 dB,NF为2.4~2.9 dB,IIP3为14 dBm。 相似文献
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提出了一种应用于无线内窥镜系统的2.4GHz低功耗ASK发射机.为了获得高的数据传输速率,采用了基于混频器的直接上变换发射机结构.为了节省功耗,提出了一种基于电流复用技术的伪差分堆栈结构的A类功放.低功耗发射机由两部分组成:基于恒幅度锁相环(PLL)的20MHz的ASK基带调制器和直接上变换的射频电路.该设计已经采用TSMC 0.25μm CMOS工艺实现并进行了验证.测试结果表明,发射数据速率为1Mbps时,发射机的输出功率为-23.217dBm.采用单2.5V的电源供电下,低功耗发射机消耗的电流约为3.17mA. 相似文献
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采用0.18 μm CMOS工艺,实现了双频段低噪声放大器设计.通过射频选择开关,电路可以分别工作在无线局域网标准802.11g规定的2.4 GHz和802.11a规定的5.2 GHz频段.该低噪声放大器为共源共栅结构,设计中采用了噪声阻抗和输入阻抗同时匹配的噪声优化技术.电路仿真结果表明:在2.4 GHz频段电路线性增益为15.4 dB,噪声系数为2.3 dB,1 dB压缩点为-12.5 dBm,IIP3为-4.7 dBm;5.2 GHz频段线性增益为12.5 dB,噪声系数为2.9 dB,1 dB压缩点为-11.3 dBm,IIP3为-5.5 dBm. 相似文献
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随着特征尺寸的不断减小,深亚微米CMOS工艺其MOSFET的特征频率已经达到50Hz以上,使得利用CMOS工艺实现GHz频段的高频模拟集成电路成为可能,越来越多的射频工程师开始利用先进的CMOS工艺设计射频集成电路,本文给出了一个利用0.35μmCMOS工艺实现的2.9GHz单片低噪声放大器,放大器采用片内集成的螺旋电感实现低噪声和单片集成。在3伏电源下,工作电流为8mA,功率增益大于10dB,输入反射小于-12dB. 相似文献
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This paper presents a 2.4 GHz power amplifier(PA) designed and implemented in 0.35μm SiGe BiCMOS technology.Instead of chip grounding through PCB vias,a metal plate with a mesa connecting ground is designed to decrease the parasitics in the PCB,improving the stability and the gain of the circuit.In addition,a low-pass network for output matching is designed to improve the linearity and power capability.At 2.4 GHz,a P_(1dB) of 15.7 dBm has been measured,and the small signal gain is 27.6 dB with S_(11)<-7 ... 相似文献
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提出了一种应用于MEMS压力传感器的高精度Σ-Δ A/D转换器。该电路由Σ-Δ调制器和数字抽取滤波器组成。其中,Σ-Δ调制器采用3阶前馈、单环、单比特量化结构。数字抽取滤波器由级联积分梳状(CIC)滤波器、补偿滤波器和半带滤波器(HBF)组成。采用TSMC 0.35 μm CMOS工艺和Matlab模型对电路进行设计与后仿验证。结果表明,该Σ-Δ A/D转换器的过采样比为2 048,信噪比为112.3 dB,精度为18.36 位,带宽为200 Hz,输入采样频率为819.2 kHz,通带波纹系数为±0.01 dB,阻带增益衰减为120 dB,输出动态范围为110.6 dB。 相似文献
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本文报道了基于0.35µm SiGe BiCMOS工艺的2.4GHz功率放大器的设计。为了降低PCB上的寄生效应,提高电路稳定性和增益,设计了带台面的金属板使芯片通过台面接地而避免通过PCB过孔接地。另外,输出匹配网络中采用了低通匹配形式,提高了电路的线性度和功率输出能力。在2.4GHz,测得1dB压缩点输出功率为15.7dBm,线性增益为27.6dB,S11和S22分别低于-7dB和-15dB。 相似文献
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A 2.4 GHz radio frequency receiver front end with an on-chip transformer compliant with IEEE 802.11b/g standards is presented.Based on zero-IF receiver architecture,the front end comprises a variable gain common-source low noise amplifier with an on-chip transformer as its load and a high linear quadrature folded Gilbert mixer.As the load of the LNA,the on-chip transformer is optimized for lowest resistive loss and highest power gain.The whole front end draws 21 mA from 1.2 V supply,and the measured results show a double side band noise figure of 3.75 dB,-31 dBm IIP3 with 44 dB conversion gain at maximum gain setting.Implemented in 0.13μm CMOS technology,it occupies a 0.612 mm~2 die size. 相似文献
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实现了一个基于触发器结构用0.35μm CMOS工艺实现的1∶8分频器.它由3级1∶2 分频器单元组成,其中第一级为动态分频器,决定了整个芯片的性能,第二、三级为静态分频器,在低频下能稳定工作.分频器采用源极耦合逻辑电路,并在传统的电路结构上进行改进,提高了电路的性能.测试的结果表明,芯片工作速率超过8.5GHz,工作带宽大于2GHz.电路在3.3V电源电压下工作,每个1∶2分频器单元的功耗约为11mW,面积为35μm×50μm.该芯片可应用于高速射频或光电收发机系统中. 相似文献
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A low-voltage CMOS low-noise amplifier (LNA) architecture is presented. We have used a TSMC 0.35?µm CMOS high-frequency model to design a fully integrated 1?V, 5.2?GHz two-stage CMOS low-noise amplifier for RF front-end applications. No off-chip element is needed and a conventional common-source with feedback technology is used in this circuit. The first stage of the LNA is the common-source with feedback structure and the output stage is a buffer which increases the gain somewhat. An interstage negative-impedance circuit is added between the two stages of the LNA to further enhance the overall gain and thus upgrade its performance. Mainly because of the finite Q of the inductor, the negative-impedance circuit used in this interstage can cancel the losses in the first-stage inductor load. The input and output matching network is matched to approximately 50?Ω. The simulation results show that the amplifier provides a gain of 9.48?dB, a noise figure of 4.08?dB, and draws 13.4?mW from a 1?V supply. The S11 and S22 are both lower than ?15?dB. 相似文献
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设计了一个基于TSMC 0.18 μm CMOS工艺的2.45 GHz全差分CMOS低噪声放大器.根据电路结构特点,采用图解法对LNA进行功耗约束下的噪声优化,以选取最优的晶体管栅宽;设计了仅消耗15 μA电流的偏置电路;采用在输入级增加电容的方法,在改善输入匹配网络特性的同时,解决了栅极电感的集成问题.仿真结果表明:LNA噪声系数为1.96 dB,功率增益S_(21)超过20 dB,输入反射系数S_(11)和输出反射系数S_(22)分别小于-30 dB和-20 dB,反向功率增益S_(12)小于-30 dB,1 dB压缩点和三阶互调输入点IIP3分别达到-17.1 dBm和-2.55 dBm,整个电路在1.8 V电源下功耗为22.4 mW. 相似文献