共查询到18条相似文献,搜索用时 140 毫秒
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目前的ASIC设计中,时钟偏移对同步数字电路的影响越来越大,它也越来越受到高速电路设计者的关注,因此如何解决它给电路带来的不利影响成了设计中的重要挑战.分析了时钟偏移的产生机理,提出了怎样使用CTS在时钟树中插入不同驱动能力的缓冲器,以平衡时钟网络,以及如何利用有用的时钟偏移来改善电路的时序. 相似文献
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专用集成电路设计中的时钟偏移分析 总被引:1,自引:0,他引:1
目前的专用集成电路设计中,时钟偏移对同步数字电路的影响越来越大,它也越来越受到高速电路设计者的关注。因此如何解决它给电路带来的不利影响成了设计中的重要挑战。本文分析了时钟偏移的产生机理,然后提出了怎样使用CTS在时钟树中插入不同驱动能力的缓冲器,以平衡时钟网络,最后还分析了如何利用有用的时钟偏移来改善电路的时序。 相似文献
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ASIC后端设计中的时钟偏移以及时钟树综合 总被引:2,自引:0,他引:2
目前的ASIC设计中,时钟偏移成为限制系统时钟频率的主要因素,时钟树综合技术通过在时钟网络中插入缓冲器来减小时钟偏移.但是,有时这样做并不能达到系统要求的时钟偏移.以一款SMIC 0.18μm工艺的DVBT数字电视解调芯片为例,分析了时钟偏移的产生原因.介殚绍了使用Synopsys公司Astro工具进行时钟树综合的方法,重点分析了在时钟树综合之前如何设置约束手动优化电路从而改善设计的时序,最后的流片结果证明该方法是有效的. 相似文献
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为了解决用传统时钟树综合策略来设计芯片只能尽量减小时钟偏移,而不能满足时序收敛的问题,文中引入了有效时钟偏移的概念,并通过在TSMC0.13μm工艺下流片成功的芯片BES7000作为设计实例,分析了有效时钟偏移引入之后对改进时序建立时间的效果。 相似文献
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基于片上偏差对芯片性能的影响,分析对比了时钟树设计与时钟网格设计,重点分析了时钟网格抗OCV影响的优点,并利用实际电路应用两种方法分别进行设计对比,通过结果分析,验证了理论分析的正确性,证明在抗OCV及时序优化时钟网格方法具有很大的优势。 相似文献
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介绍了一种加宽数据时钟自恢复电路的可恢复时钟频率带宽的方法,重点提出了时钟锁定的检测电路及时钟输出的选择电路的设计,并进行了分析。 相似文献
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基于时钟设计的异步时序逻辑电路设计法 总被引:1,自引:1,他引:0
基于时钟设计的异步时序逻辑电路设计法,根据电路状态转换规律,立足电路中各位触发器时钟设计,使电路完成所要求的逻辑功能,从而避免了求解电路状态方程,驱动方程。 相似文献
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Syed Rafay HasanAuthor Vitae Normand BélangerAuthor VitaeYvon SavariaAuthor Vitae M. Omair AhmadAuthor Vitae 《Integration, the VLSI Journal》2011,44(1):22-38
High-performance clocking of intellectual property (IP) modules, within a skew budget, is becoming difficult in deep sub-micron technologies. In this work, we propose a novel and all-digital synchronous design method for point-to-point communications, using two stages of interfacing registers and locally delayed clock with phase adjustments. This design is free from synchronizers and clock-data mismatch problems. Moreover, communicating modules run at frequencies which are virtually independent of the clock skew. We also provide a comprehensive case-wise mathematical analysis to facilitate design automation for synthesizing such designs as standard cells. An overall improvement in skew tolerance of up to n times (where n is the number of registers used), when compared to conventional designs, is achieved when the skew orientation is known and n/2 times if the skew orientation is unknown. Improvement in skew tolerance is validated using gate level simulations with the 0.18 μm TSMC CMOS technology. A prototype implementation of the proposed design using a Virtex-II Pro FPGA from Xilinx validates the claim that such designs allow a fast module to communicate with a slow module without constraining their frequencies. 相似文献
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《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2001,9(5):704-717
Clock skew modeling is important in the performance evaluation and prediction of clock distribution networks. This paper addresses the problem of statistical skew modeling for general clock distribution networks in the presence of process variations. The only available statistical skew model is not suitable for modeling the clock skews of general clock distribution networks in which clock paths are not identical. The old model is also too conservative for estimating the clock skew of a well-balanced clock network that has identical but strongly correlated clock paths (for instance, a well-balanced H-tree). In order to provide a more accurate and more general statistical skew model for general clock distributions, we propose a new approach to estimating the mean values and variances of both clock skews and the maximal clock delay of general clock distribution networks. Based on the new approach, a closed-form model is also obtained for well-balanced H-tree clock distribution networks. The paths delay correlation caused by the overlapped parts of path lengths is considered in the new approach, so the mean values and the variances of both clock skews and the maximal clock delay are accurately estimated for general clock distribution networks. This enables an accurate estimate of yields of both clock skew and maximal clock delay to be made for a general clock distribution network 相似文献
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无缓冲谐振时钟分布网络能够最小化同步系统的时钟功耗。但由于没有缓冲器,时钟网络的偏斜受到多方面因素的影响,例如时钟互连线寄生参数的差异,非平衡时钟负载以及工艺、电压温度变化。本文提出了一种层次化的两相无缓冲谐振时钟互连网络结构,将网格型和树型结构的各自优点相结合。在TSMC 65nm标准CMOS工艺下,通过一个流水线乘法器电路分析了该结构时钟网络的偏斜及变化容忍特性。版图后仿真结果表明,层次化时钟网络的偏斜分别比纯网格和纯H树结构时钟网络降低超过75%和65%,而且在非平衡时钟负载或工艺、电压温度变化的情况下,时钟网络偏斜最高小于7ps,不超过整个时钟周期(约760ps)的1%。 相似文献
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《IEEE transactions on circuits and systems. I, Regular papers》2009,56(2):374-383
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用Encounter实现Mesh-Local-Tree结构的时钟设计流程 总被引:1,自引:0,他引:1
提出了一种实用的设计流程,即在Cadencd公司的Encounter环境中去实现对网格 本地树(MLT)时钟结构的综合与分析方法.对一个实际工业设计试验的数据表明:运用Clockmesh CRS的综合方式,MLT的时钟架构相对于单一的树结构能够实现更小的时钟偏差(114ps、 171ps).同时,将这种设计流程运用于其他设计中,以比较MLT和CTS不同的设计流程.结果显示,MLT的时钟架构可以实现更小的时钟偏差,同时还可以降低缓冲器的数量,这样也弥补了单一网格结构的功耗问题. 相似文献
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Many methodologies for clock mesh networks have been introduced for two‐dimensional integrated circuit clock distribution networks, such as methods to reduce the total wirelength for power consumption and to reduce the clock skew variation through consideration of buffer placement and sizing. In this paper, we present a methodology for clock mesh to reduce both the clock skew and the total wirelength in three‐dimensional integrated circuits. To reduce the total wirelength, we construct a smaller mesh size on a die where the clock source is not directly connected. We also insert through‐silicon vias (TSVs) to distribute the clock signal using an effective clock TSV insertion algorithm, which can reduce the total wirelength on each die. The results of our proposed methods show that the total wirelength was reduced by 12.2%, the clock skew by 16.11%, and the clock skew variation by 11.74%, on average. These advantages are possible through increasing the buffer area by 2.49% on the benchmark circuits. 相似文献
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Statistical clock skew modeling with data delay variations 总被引:1,自引:0,他引:1
Harris D. Naffziger S. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2001,9(6):888-898
Accurate clock skew budgets are important for microprocessor designers to avoid hold-time failures and to properly allocate resources when optimizing global and local paths. Many published clock skew budgets neglect voltage jitter and process variation, which are becoming dominant factors in otherwise balanced H-trees. However, worst-case process variation assumptions are severely pessimistic. This paper describes the major sources of clock skew in a microprocessor using a modified H-tree and applies the model to a second-generation Itanium-M processor family microprocessor currently under design. Monte Carlo simulation is used to develop statistical clock skew budgets for setup and hold time constraints in a four-level skew hierarchy. Voltage jitter through the phase locked loop (PLL) and clock buffers accounts for the majority of skew budgets. We show that taking into account the number of nearly critical paths between clocked elements at each level of the skew hierarchy and variations in the data delays of these paths reduces the difference between global and local skew budgets by more than a factor of two. Another insight is that data path delay variability limits the potential cycle-time benefits of active deskew circuits because the paths with the worst skew are unlikely to also be the paths with the longest data delays 相似文献