P-channel Ge/Si Hetero-nanocrystal Based MOSFET Memory

The charge storage characteristics of P-channel Ge/Si hetero-nanocrystal based MOSFET memory has been investigated and a logical array has been constructed using this memory cell. In the case of the thickness of tunneling oxide T_ox=2nm and the dimensions of Si- and Ge-nanocrystal D_Si=D_Ge=5nm, the retention time of this device can reach ten years(~1×10~8s) while the programming and erasing time achieve the orders of microsecond and millisecond at the control gate voltage |V_g|=3V with respect to N-wells, respectively. Therefore, this novel device, as an excellent nonvolatile memory operating at room temperature, is desired to obtain application in future VLSI.     

Nonvolatile flash memory device using Ge nanocrystals embedded in HfAlO high-/spl kappa/tunneling and control oxides: Device fabrication and electrical performance

We fabricated a nonvolatile Flash memory device using Ge nanocrystals (NCs) floating-gate (FG)-embedded in HfAlO high-/spl kappa/ tunneling/control oxides. Process compatibility and memory operation of the device were investigated. Results show that Ge-NC have good thermal stability in the HfAlO matrix as indicated by the negative Gibbs free energy changes for both reactions of GeO/sub 2/+Hf/spl rarr/HfO/sub 2/+Ge and 3GeO/sub 2/+4Al/spl rarr/2Al/sub 2/O/sub 3/+3Ge. This stability implies that the fabricated structure can be compatible with the standard CMOS process with the ability to sustain source-drain activation anneal temperatures. Compared with Si-NC embedded in HfO/sub 2/, Ge-NC embedded in HfAlO can provide more electron traps, thereby enlarging the memory window. It is also shown that this structure can achieve a low programming voltage of 6-7 V for fast programming, a long charge retention time of ten years maintaining a 0.7-V memory window, and good endurance characteristics of up to 10/sup 6/ rewrite cycles. This paper shows that the Ge-NC embedded in HfAlO is a promising candidate for further scaling of FG Flash memory devices.     

A novel germanium doping method for fabrication of high-performance p-channel poly-Si/sub 1-x/Ge/sub x/ TFT by excimer laser crystallization

In this letter, a novel process for fabricating p-channel poly-Si/sub 1-x/Ge/sub x/ thin-film transistors (TFTs) with high-hole mobility was demonstrated. Germanium (Ge) atoms were incorporated into poly-Si by excimer laser irradiation of a-Si/sub 1-x/Ge/sub x//poly-Si double layer. For small size TFTs, especially when channel width/length (W/L) was less than 2 /spl mu/m/2 /spl mu/m, the hole mobility of poly-Si/sub 1-x/Ge/sub x/ TFTs was superior to that of poly-Si TFTs. It was inferred that the degree of mobility enhancement by Ge incorporation was beyond that of mobility degradation by defect trap generation when TFT size was shrunk to 2 /spl mu/m/2 /spl mu/m. The poly-Si/sub 0.91/Ge/sub 0.09/ TFT exhibited a high-hole mobility of 112 cm/sup 2//V-s, while the hole mobility of the poly-Si counterpart was 73 cm/sup 2//V-s.     

Organic field-effect transistors based on single-crystalline active layer and top-gate insulator consistently fabricated by electrostatic spray deposition

An electrostatic spray deposition (ESD) method was applied to prepare both crystalline domains of 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS pentacene) and insulating films of poly(methyl methacrylate) (PMMA) for fabricating top-gate single-crystal organic field-effect transistors (OFETs). The electrical characteristics of the top-gate device were compared to those of the bottom-gate one (SiO₂ bottom-gate insulator) with the same active layer, and the lower charge-trap density at the interface between the top-gate insulator and single-crystalline active layer was demonstrated. The drain current compression in the output characteristics of the top-gate device, however, occurred due to the large parasitic resistance between the source/drain electrodes and accumulation channel. Reducing the thickness of the single-crystalline active layer resulted in a high charge-carrier mobility of 0.29 cm²/V s (channel length of 5 μm).     

A TaN-HfO/sub 2/-Ge pMOSFET with NovelSiH/sub 4/ surface passivation

In this letter, we demonstrate a novel surface passivation process for HfO/sub 2/ Ge pMOSFETs using SiH/sub 4/ surface annealing prior to HfO/sub 2/ deposition. By using SiH/sub 4/ passivation, a uniform amorphous interfacial layer is formed after device fabrication. Electrical results show that the HfO/sub 2/ Ge MOSFET with Si-passivation exhibits less frequency dispersion, narrower gate leakage current distribution, and a /spl sim/140% higher peak mobility than that of the device with surface nitridation.     

GaN/AlGaN p-channel inverted heterostructure JFET

A novel GaN/AlGaN p-channel inverted heterostructure junction field-effect transistor (HJFET) with a n/sup +/-type gate is proposed and demonstrated. A new superlattice aided strain compensation techniques was used for fabricating high quality GaN/AlGaN p-n junction. The p-channel HJFET gate leakage current was below 10 nA, and the threshold voltage was 8 V, which is close to that of typical n-channel HFETs. This new HJFET device opens up a way for fabricating nitride based complimentary integrated circuits.     

$hbox{HfO}_{x}$ Bipolar Resistive Memory With Robust Endurance Using AlCu as Buffer Electrode

A novel method of fabricating $hbox{HfO}_{x}$-based resistive memory device with excellent nonvolatile characteristics is proposed. By using a thin AlCu layer as the reactive buffer layer into the anodic side of a capacitor-like memory cell, excellent memory performances, which include reliable programming/erasing endurance $(≫ hbox{10}^{5} hbox{cycles})$, robust data retention at high temperature, and fast operation speed ( $≪$ 50 ns), have been demonstrated. The resistive memory based on AlCu/$hbox{HfO}_{x}$ stacked layer in this letter shows promising application in the next generation of nonvolatile memory.      

Numerical investigation of characteristics of p-channel Ge/Si hetero-nanocrystal memory

The characteristics of p-channel Ge/Si hetero-nanocrystal based MOSFET memory have been investigated numerically considering mainly hole-tunneling process. Owing to the advantages of a compound potential well and a higher band offset at the valence band compared with the p-channel Si nanocrystal based MOSFET memory and n-channel Ge/Si hetero-nanocrystal based MOSFET memory, the present structure shows that the holes have a longer retention time. Moreover, this kind of device keeps on having high-speed writing/erasing in the direct-tunneling ultrathin oxide regime. It would be expected to solve the contradictory problem between high-speed programming and long retention, therefore, the performance would be substantially improved.     

The thermal stability of one-transistor ferroelectric memory with Pt-Pb/sub 5/Ge/sub 3/O/sub 11/-Ir-poly-SiO/sub 2/-Si gate stack

The thermal stability of one-transistor ferroelectric nonvolatile memory devices with a gate stack of Pt-Pb/sub 5/Ge/sub 3/O/sub 11/-Ir-Poly-SiO/sub 2/-Si was characterized in the temperature range of -10/spl deg/C to 150/spl deg/C. The memory windows decrease when the temperatures are higher than 60/spl deg/C. The drain currents (I/sub D/) after programming to on state decrease with increasing temperature. The drain currents (I/sub D/) after programming to off state increase with increasing temperature. The ratio of drain current (I/sub D/) at on state to that at off state drops from 7.5 orders of magnitude to 3.5 orders of magnitude when the temperature increases from room temperature to 150/spl deg/C. On the other hand, the memory window and the ratio of I/sub D/(on)/I/sub D/(off) of the one-transistor memory device displays practically no change when the temperature is reduced from room temperature to -10/spl deg/C. One-transistor (1T) memory devices also show excellent thermal imprint properties. Retention properties of 1T memory devices degrade with increasing temperature over 60/spl deg/C.     

A Study on the Failure Mechanism of a Phase-Change Memory in Write/Erase Cycling

Using a phase-change memory (PCM) device composed of Ge₂Sb₂e₅ (GST), we studied the mechanism of the SET-stuck failure (SSF), a constantly low-resistance state during write/erase (W/E) cycling. The SSF state was characterized with increased RESET current and decreased threshold voltage, which were thought to be due to depletion of Ge and enrichment of Sb inside the active volume of GST. Moreover, we found that device characteristics of an SSF-PCM could be recovered by reversing bias polarity and the repaired device could endure many W/E cycles, implying that field-induced ion migration was the major cause of the SSF of a PCM.     

An understanding of ohmic contact formation with Ge doping of n-GaAs

Ge is commonly used as an n⁺ dopant in fabricating ohmic contacts to n-type GaAs. It is suggested here that the donor-like behaviour of this otherwise amphoteric impurity may be related to the effect of distortion of the GaAs lattice on Ge impurities. Attempts to maximise the Ge n⁺ doping behaviour, however, may enhance lattice strain and degrade device life-time.     

Ge/Si复合纳米结构电荷存储特性的模拟研究

这一研究工作模拟计算了 Ge/ Si复合纳米结构 MOSFET存储器的擦写和存储时间特性。结果表明 ,Ge/ Si复合纳米结构存储器在低压下即可实现 μs和 ns量级编程。与 Si纳米结构存储器相比 ,由于 Ge/ Si复合势阱的作用 ,器件的电荷保留时间提高了 3～ 5个量级 ,有效地解决了快速擦写编程与长久存储之间的矛盾 ,使器件的性能得到明显改善。     

Electrical properties of Ge metal–oxide–semiconductor capacitors with high-k La2O3 gate dielectric incorporated by N or/and Ti

LaON, LaTiO and LaTiON films are deposited as gate dielectrics by incorporating N or/and Ti into La2O3 using the sputtering method to fabricate Ge MOS capacitors, and the electrical properties of the devices are carefully examined. LaON/Ge capacitors exhibit the best interface quality, gate leakage property and device reliability, but a smaller k value (14.9). LaTiO/Ge capacitors exhibit a higher k value (22.7), but a deteriorated interface quality, gate leakage property and device reliability. LaTiON/Ge capacitors exhibit the highest k value (24.6), and a relatively better interface quality (3.1E11 eV^-1cm^-2), gate leakage property (3.6E3 A/cm^2 at Vg = 1 V + Vfb) and device reliability. Therefore, LaTiON is more suitable for high performance Ge MOS devices as a gate dielectric than LaON and LaTiO materials.     

Laser Annealing of Amorphous Germanium on Silicon–Germanium Source/Drain for Strain and Performance Enhancement in pMOSFETs

We report the first demonstration of a novel germanium-enrichment process for forming a silicon-germanium (SiGe) source/drain (S/D) stressor with a high Ge content. The process involves laser-induced local melting and intermixing of a Ge layer with an underlying Si_0.8Ge_0.2 S/D region, leading to a graded SiGe S/D stressor with a significant increase in the peak Ge content. Various laser fluences were investigated for the laser annealing process. The process is then successfully integrated in a device fabrication flow, forming strained silicon-on-insulator p-channel field-effect transistors (p-FETs) with a high Ge content in SiGe S/D. A drive current enhancement of ~ 12% was achieved with this process, as compared to a strained p-FET with Si_0.8Ge_0.2 S/D p-FETs. The I _Dsat enhancement, primarily attributed to strain-induced mobility improvement, is found to increase with decreasing gate lengths.     

Enhanced Sensitivity of Small-Size (With 1-$mu hbox{m}$ Gate Length) Junction-Field-Effect-Transistor-Based Germanium Photodetector Using Two-Step Germanium Epitaxy by Ultrahigh Vacuum Chemical Vapor Deposition

In this letter, we demonstrate a scalable (with gate length of 1 mum) Ge photodetector based on a junction field-effect-transistor (JFET) structure with high sensitivity and improved response time. To overcome the low-detection-efficiency issue of typical JFET photodetectors, a high-quality Ge epilayer, as the gate of JFET, was achieved using a novel epigrowth technique. By laser surface illumination of 3 mW on the Ge gate, an I _ON/I _OFF ratio up to 185 was achieved at a wavelength of 1550 nm for the first time. In addition, the device shows a temporal response time of 110 ps with a rise time of 10 ps, indicating that the scalable Ge JFET photodetector is a promising candidate to replace large-size photodiodes in future optoelectronic integrated circuits and as an image sensor integrated with a CMOS circuit for its comparable size in respect to modern MOSFETs.     

Electrical Characteristics of Memory Devices With a High- k HfO2 Trapping Layer and Dual SiO2/Si3N4 Tunneling Layer

A novel device structure with a high-k HfO₂ charge storage layer and dual tunneling layer (DTL) (SiO₂/Si₃N₄) is presented in this paper. Combining advantages of the high trapping efficiency of high-k materials and enhanced charge injection from the substrate through the DTL, the device achieves a fast program/erase speed and a large memory window. The device demonstrates excellent retention due to its physically thick DTL and also improved endurance without any increase of programming V_th throughout the cyclic test as compared with SONOS Flash memory devices using an Si₃N₄ trapping layer.     

Sb-Se-based phase-change memory device with lower power and higher speed operations

A phase-change material of Sb/sub 65/Se/sub 35/ was newly proposed for the nonvolatile memory applications. The fabricated phase-change memory device using Sb/sub 65/Se/sub 35/ showed a good electrical threshold switching characteristic in the dc current-voltage (I-V) measurement. The programming time for set operation of the memory device decreased from 1 /spl mu/s to 250 ns when Sb/sub 65/Se/sub 35/ was introduced in place of the conventionally employed Ge/sub 2/Sb/sub 2/Te/sub 5/ (GST). The reset current of Sb/sub 65/Se/sub 35/ device also dramatically reduced from 15 mA to 1.6 mA, compared with that of GST device. These results are attributed to the low melting temperature and high crystallization speed of Sb/sub 65/Se/sub 35/ and will contribute to lower power and higher speed operations of a phase-change nonvolatile memory.     

Smooth, 3D Ge transistor channels by heteroepitaxial growth

Crystalline germanium (Ge) is a prime candidate as a material for high-performance transistors due to its higher electron and hole mobility with respect to those of silicon. In this study, we present a novel method of fabricating epitaxial Ge structures of high crystalline and morphological quality directly onto Si substrates, in which 3D Ge structures are grown by selective epitaxy then annealed in a hydrogen ambient at 850 °C. Under such annealing, the surface of the Ge structures deform by surface diffusion to form smooth, rounded shapes for which the surface energy is at a local minima. The apparent smoothness of the surface, along with the decreased defect density expected to exist in these heteroepitaxial Ge structures, suggest they are adequate for use as transistor channels.     

SiGeC/Si异质结二极管特性分析与优化设计

基于异质结理论,提出了一种新型p+(SiGeC)-n--n+异质结功率二极管结构。分析了C对SiGe合金的应变补偿作用的物理机理。利用MEDICI模拟、对比分析了C的引入对器件电特性的影响,并针对不同Ge/C组分比进行优化设计。结果表明:在SiGe/Si功率二极管中加入少量的C,在基本不影响器件正向I-V特性和反向恢复特性的前提下,大大减少了器件的反向漏电流,提高了器件稳定性,而且对于一定的Ge含量存在一个C的临界值,使得二极管具有最小的反向漏电流,该临界值的提出,对研究其它结构SiGeC/Si异质结半导体器件有一定的参考意义。     

Nonvolatile Memory Effect in Indium Gallium Arsenide-Based Metal–Oxide–Semiconductor Devices Using II–VI Tunnel Insulators

This paper reports the successful use of ZnSe/ZnS/ZnMgS/ZnS/ZnSe as a gate insulator stack for an InGaAs-based metal–oxide–semiconductor (MOS) device, and demonstrates the threshold voltage shift required in nonvolatile memory devices using a floating gate quantum dot layer. An InGaAs-based nonvolatile memory MOS device was fabricated using a high-κ II–VI tunnel insulator stack and self-assembled GeO _x -cladded Ge quantum dots as the charge storage units. A Si₃N₄ layer was used as the control gate insulator. Capacitance–voltage data showed that, after applying a positive voltage to the gate of a MOS device, charges were being stored in the quantum dots. This was shown by the shift in the flat-band/threshold voltage, simulating the write process of a nonvolatile memory device.