负阻提升的微波混沌振荡器的设计

将负阻提升技术引入到混沌振荡器的设计中,通过理论推导、数值计算和测试验证来优化电路结构,提供参数选取规则,从理论和实验两方面验证,在双电感的比值达到最优值时振荡器负阻能够得到大幅提升。并基于负阻提升技术提出了双电感结构的微波Colpitts 混沌振荡器。新结构电路的最高混沌振荡基频为1.78 GHz,较经典电路提升了39%;带宽达到4.60GHz(0.80～5.40 GHz),较经典电路提升了119%。测试结果表明,优化的双电感结构能有效提升混沌振荡基频和带宽。     

微波Colpitts混沌电路实验研究

本文首先介绍了Colpitts电路的数学模型，给出了基于预设定频谱分布的Colpitts混沌电路中主要电路参数的设计方法；然后对工作在微波频段的Colpitts混沌电路进行了实验研究，验证了给出的电路参数设计方案；最后对实验过程中的电路调试方法，电路频谱宽度的瓶颈问题，电路功耗问题以及进一步的工作进行了讨论。     

基于高次谐波体声波谐振器的微波振荡器设计

基于高次谐波体声波谐振器(HBAR)的高品质因数(Q)值和多模谐振特性,设计了Colpitts和Pierce两种形式的微波振荡器。采用HBAR与LC元件组成谐振回路的方法,与放大电路构成反馈环路直接基频输出微波频段信号。Colpitts振荡器输出信号频率为980 MHz,信号输出功率为-4.92dBm,信号相位噪声达-119.64dBc/Hz@10kHz;Pierce振荡电路输出信号频率达到2.962GHz,信号输出功率为-9.77dBm,信号相位噪声达-112.30dBc/Hz@10kHz。     

三极管特征频率下1GHz振荡器设计与仿真

三极管振荡器一般工作在截止频率附近，这时虽然能够输出较大信号，获得较好的频率稳定度，但是电路中滤波器性能的好坏直接影响输出的高次谐波干扰，而且这种设计思想大大限制了三极管往更高频率上的应用。谩计了在特征频率工作下的三极管振荡嚣，严格限制了高次谐波干扰。建立了射频三极管分布参数、封装参数模型，利用上述模型模拟了三极管特征频率下工作的振荡器振荡频率，输出电压与电源电压、振荡频率与电源电压、振荡频率与基极电感、输出电压与基极电感的关系。最后得出模拟与实验测试一致的结果。     

压控振荡器在射频通信电路中的应用

随着现代通信系统和现代雷达系统的出现,射频电路需要在特定的载波频率点上建立稳定的谐波振荡,以便为调制和混额创造必要的条件.设计了一个振荡频率在1.14～1.18 GHz的负阻LC压控振荡器,实现了压控振荡器的宽调频,使频率范围达到加MHz.并且为避免在外部电路对压控振荡器(VCO)的影响,在电路中加入射极跟随器作为buffer,起到阻抗变换和级间隔离的作用.为负阻LC压控振荡器的设计提供了一种参考电路.     

基于栅极电感反馈的CMOS差分Vacker VCO设计

提出了一种基于栅极电感反馈的Vacker压控振荡器(VCO),该结构能够改善电路的负阻抗,进而使得电路易于起振。对晶体管的负载效应和振幅稳定性的分析表明,该Vacker VCO相比较于Colpitts VCO,具有更好的振幅稳定性,进而改善了VCO的相位噪声。基于0.13-μm RF CMOS工艺,对该Vacker VCO进行了设计与芯片实现,测试结果表明：在消耗4.2 mW功耗的前提下,该VCO振荡频率为11 GHz～12.6 GHz,在11.8 GHz振荡频率处,相位噪声为-115.1 dBc/Hz@1 MHz,品质因数FOM指标达到-190.3 dBc/Hz。     

基本电子电路

TN702,TN752.52006010724基于预设定频率分布的Colpitts混沌电路设计/史治国,冉立新,陈抗生(浙江大学信息与电子工程学系)//浙江大学学报(工学版).―2005,39(3).―402～406.为了找出Colpitts混沌电路的设计综合准则,给出基于预设定频率分布的电路主要元件参数表达式。通过引入了电路的数学模型,导出电路的归一化状态方程,在电路仿真的基础上,得到电路的频率分布特征。根据三个预设定的频率分布,计算出电路主要元件参数,使用专业的射频微波仿真软件高级设计系统(ADS)对电路进行仿真。仿真结果表明,在上限频率为100MHz～1GHz的预设定频…     

基于HBT工艺的高功率低相位噪声QVCO

基于Sanan 2 μm GaAs HBT工艺,提出了一种差分Colpitts结构的高功率低相位噪声正交压控振荡器(QVCO)。该QVCO采用四只环形连接的二极管,通过二次谐波反相作用,迫使压控振荡器基波正交。该QVCO比传统串并联晶体管耦合电路具有更高的输出功率和更低的相位噪声。仿真结果表明,该QVCO的调谐范围为12.98~14.05 GHz。振荡频率为13.51 GHz时,输出信号功率为12.557 dBm。相位噪声为-117.795 dBc/Hz @1 MHz。     

小型化低相噪FBAR压控振荡器的研制

利用薄膜声体波谐振器(FBAR),结合GaAs异质结双极晶体管(HBT)工艺研制了一款小型化低相噪FBAR压控振荡器。将振荡三极管、偏置电路及隔离缓冲放大器集成到一个GaAs单片微波集成电路(MMIC)中,振荡管基极接薄膜电感形成负阻,发射极通过键合线与FBAR进行互连。将GaAs单片集成电路的大信号模型作为一个非线性器件,用探针台测试FBAR谐振器的单端口S参数,导入ADS软件进行谐波平衡法仿真和优化;通过电路制作和调试,达到了预期设计目标。该FBAR压控振荡器中心频率为2.44 GHz,调谐带宽15 MHz,单边带相位噪声达-110 dBc/Hz@10 kHz,与同频段同轴介质压控振荡器指标相当,但其尺寸更小,仅为5 mm×7 mm×2.35 mm。     

一种基于BiCMOS工艺的差分压控振荡器

设计了一种Colpitts型LC振荡器。该电路采用差分结构，具有集成度高，噪声性能良好的优点。该设计基于0．8μm BiCMOS工艺，实现了中心频率为433MHz的Colpitts型差分压控振荡器（VCO）。电路采用3V电压供电，频率范围399．8～465．1MHz，偏离中心频率1MHz处的相位噪声是-137dBc／Hz。     

Two-stage chaotic Colpitts oscillator

A novel version of the chaotic Colpitts oscillator is proposed. It contains two bipolar junction transistors coupled in series. The resonance loop consists of an inductor and three capacitors. The two-stage oscillator, compared with the classical circuit, enables the fundamental frequency of chaotic oscillations to be increased by a factor of three. The PSpice simulations performed with 9 GHz threshold frequency transistors demonstrate that the highest fundamental frequencies of chaotic behaviour are 1 and 3 GHz for the classical and the two-stage Colpitts oscillator, respectively     

The design and analysis of dual control voltages delay cell for low power and wide tuning range ring oscillators in 65 nm CMOS technology for CDR applications

In this paper three delay cell structures used in four-stage ring oscillator are evaluated. In the first structure, the control voltage is employed to the gate of PMOS transistors which are inserted in series with the input PMOS transistors. In this case the minimum power dissipation is gained. Since the control voltage is injected to the PMOS transistors parallel with input transistors, the better tuning range in higher frequency and lower phase noise is achieved. In order to make a tradeoff between the tuning range, phase noise and power dissipation, the PMOS transistors activated with the control voltage are applied to the oscillator in both the series and parallel paths. In improved structure, the oscillator works in 2.65–13.93 GHz under 1 V supply voltage in 65 nm CMOS technology. The phase noise is −94.33 dBc/Hz at 1 MHz offset from 3.7 GHz center frequency, while the power dissipation is 328.6 μW and the chip area is 139.5 µm².     

Improved chaotic Colpitts oscillator for ultrahigh frequencies

A novel version of the Colpitts oscillator is presented generating chaotic oscillations at gigahertz frequencies. In contrast to the standard oscillator the inductor is moved from the collector circuit of the transistor to the base circuit. PSpice simulations demonstrate chaos at the fundamental frequencies of 0.5, 1 and 2 GHz employing transistors with a threshold frequency of 9 GHz.     

Design and performance analysis of wrap-gate CNTFET-based ring oscillators for IoT applications

In recent years, usage of novel non-Si materials as the gate channel region in next generation of field effect transistors, including carbon nanotubes, have been in the spotlight of nanoelectronics research due to astounding carrier transport and I-V characteristics. These properties make them a highly suitable platform in modern radio frequency applications. Therefore, the aim of this work is to design and investigate the performance of current-starved and skewed ring oscillators based on ballistic carbon nanotube transistors (CNTFETs). In this work, we have utilized wrap-gate structure to have a better electrostatics control and mitigate the gate leakage current. All the CNTs in both n-type and p-type transistors have 0.9 nm diameter and an array of CNTs have been exploited in the gate region to achieve low-power and high-performance operation. The simulation results demonstrate that the proposed CNTFET-based ring oscillators have sub-100μW power consumption (P_{current-starved} = 6.011 μW, P_low-skew = 67.2 μW, and P_high-skew = 23.5 μW) along with wide frequency tuning range (f_{current-starved} = 0.202 GHz − 1.205 GHz, f_low-skew = 0.361 GHz − 2.137 GHz, and f_high-skew = 0.335 GHz − 2.38 GHz) which are suitable for internet of thing (IoT) devices operating from 100 MHz to 5.8 GHz. Finally, based on the simulation results, we have emphasized that the CNTFET-based skewed ring oscillators are suitable for high-speed purposes, while the CNTFET-based current-starved ring oscillator is recommended for low-power and high-swing applications.     

A C-band low-power sub-1volt current-reused multiphase oscillator

A new sub-1V and low power multiphase voltage-controlled oscillator (QVCO) with current-reused structure is proposed. The proposed core oscillator consists of two N-metal oxide semiconductor (NMOS) and P-metal oxide semiconductor (PMOS) transistors and an additional NMOS-only cross-coupled pair that enhances the effective negative transconductance and facilities the start-up condition at sub-1V supply voltages in modern nm CMOS technologies. In the proposed coupling scheme, the gate of cross-coupled transistors is used for coupling in an ‘in-phase−anti-phase’ manner. Parallel capacitors to the drain-source of transistors have been used for further enhancement of effective transconductance and thus lower power consumption; though the increase of parallel capacitors reduces the tuning range, indicating a trade-off in the proposed QVCO. The proposed quadrature oscillator is designed and simulated in a standard 0.18 μm RF-CMOS technology. The results of the simulation show that the QVCO has a 9% tuning range from 5.35 GHz to 5.88 GHz, and the phase noise is −119.6 dBc/Hz at 1-MHz offset from the 5.7 GHz carrier while consumes only 1.4 mW from a 0.85-V supply voltage; yielding an excellent figure-of-merit (FOM) of −193.3 dBc that is amongst the best FOMs. Several Monte Carlo and PVT analyses verify the robust performance of the QVCO.     

Design of a new low-phase-noise millimetre-wave quadrature voltage-controlled oscillator

This paper presents a new circuit topology of millimetre-wave quadrature voltage-controlled oscillator (QVCO) using an improved Colpitts oscillator without tail bias. By employing an extra capacitance between the drain and source terminations of the transistors and optimising circuit values, a low-power and low-phase-noise (PN) oscillator is designed. For generating the output signals with 90° phase difference, a self-injection coupling network between two identical cores is used. The proposed QVCO dissipates no extra dc power for coupling, since there is no dc-path to ground for the coupled transistors and no extra noise is added to circuit. The best figure-of-merit is ?188.5, the power consumption is 14.98–15.45 mW, in a standard 180-nm CMOS technology, for 58.2 GHz center frequency from 59.3 to 59.6 GHz. The PN is ?104.86 dBc/Hz at 1-MHz offset.     

Design of 10 GHz eight-phase voltage controlled oscillator in 90 nm CMOS

A novel 10 GHz eight-phase voltage-controlled oscillator(VCO) architecture applied in clock and data recovery(CDR) circuit for 40 Gbit/s optical communications system is proposed.Compared with the traditional eight-phase oscillator,a new ring CL ladder filter structure with four inductors is proposed.The VCO is designed and fabricated in IBM 90nm complementary metal-oxide-semiconductor transistor(CMOS) technology.Measurement results show the tuning range is 9.2 GHz～11.0 GHz and the phase noise of-108.85 dBc/Hz at 1 MHz offset from the carrier frequency of 10 GHz.The chip area of VCO is 500 μm× 685 μm and the power dissipation is 17.4 mW with the 1.2 V supply voltage.     

宽频率范围的单子带压控振荡器设计

基于TSMC 180 nm CMOS工艺,提出了一种振荡频率为2～3 GHz的宽频率范围、低相位噪声的单子带压控振荡器(VCO).采用双平衡吉尔伯特混频结构,将单子带5～6 GHz压控振荡器与固定频率3 GHz压控振荡器进行下混频,可得到振荡频率为2～3 GHz的单子带压控振荡器,实现相对带宽从18.18％到40％的展...     

推-推压控振荡器的仿真设计

在对构成推-推振荡器的基本振荡单元进行常规奇偶模分析的基础上,采用添加辅助信号源的方法,对合成后的频率调谐特性、输出功率及基波抑制特性进行了仿真模拟。并利用负载牵引法对二次谐波匹配网络进行了优化。根据仿真结果设计的X波段推-推压控振荡器,采用封装硅晶体管及砷化镓变容管,在1GHz调谐带宽内,输出功率2～8dBm。