Flip chip assembled MEMS inductors

High performance suspended MEMS inductors produced using a flip chip assembly approach are described. An inductor structure is fabricated on a carrier and then flip chip assembled onto a substrate to form a suspended inductor for RF-IC applications with significant improvement in Q-factor and frequency of operation over the conventional IC inductors. A spiral MEMS inductor has been successfully produced on a silicon substrate with an air gap of 26 /spl mu/m between the inductor structure and the substrate. The inductance of the device was measured to be /spl sim/2 nH and a maximum Q-factor of 19 at /spl sim/2.5 GHz was obtained after pad/connector de-embedding.     

Packaging-compatible high Q microinductors and microfilters forwireless applications

To meet requirements in mobile communication and microwave integrated circuits, miniaturization of the inductive components that many of these systems require is of key importance. At present, active circuitry is used which simulates inductor performance and which has high Q-factor and inductance; however, such circuitry has higher power consumption and higher potential for noise injection than passive inductive components. An alternate approach is to fabricate integrated inductors, in which lithographic techniques are used to pattern an inductor directly on a substrate or a chip. However, integrated inductors can suffer from low Q-factor and high parasitic effects due to substrate proximity. To expand the range of applicability of integrated microinductors at high frequency, their electrical characteristics, especially quality factor, should be improved. In this work, integrated spiral microinductors suspended (approximately 60 μm) above the substrate using surface micromachining techniques to reduce the undesirable effect of substrate proximity on the inductor performance are investigated. The fabricated inductors have inductances ranging from 15-40 nH and Q-factors ranging from 40-50 at frequencies of 0.9-2.5 GHz. Microfilters based on these inductors are also investigated by combining these inductors with integrated polymer filled composite capacitors     

High Q microwave inductors on silicon by surface tensionself-assembly

A new technique is presented for the fabrication of three-dimensional metal structures by surface tension-induced folding of flat structures. This fully parallel, low temperature method is suitable for post-processing on integrated circuits, and in a first application is used to decouple inductors for radio and microwave-frequency integrated circuits from their substrates, to reduce losses and parasitic capacitance. Meandered microwave inductors have been fabricated on a low resistivity silicon substrate. A peak Q of 10 was measured at 1 GHz, for a 2 nH inductor standing vertically, compared to a peak Q of 4 for the same structure before self assembly     

Micromachined high-Q inductors in a 0.18-μm copper interconnectlow-k dielectric CMOS process

On-chip spiral micromachined inductors fabricated in a 0.18-μm digital CMOS process with 6-level copper interconnect and low-K dielectric are described. A post-CMOS maskless micromachining process compatible with the CMOS materials and design rules has been developed to create inductors suspended above the substrate with the inter-turn dielectric removed. Such inductors have higher quality factors as substrate losses are eliminated by silicon removal and increased self-resonant frequency due to reduction of inter-turn and substrate parasitic capacitances. Quality factors up to 12 were obtained for a 3.2-nH micromachined inductor at 7.5 GHz. Improvements of up to 180% in maximum quality factor, along with 40%-70% increase in self-resonant frequency were seen over conventional inductors. The effects of micromachining on inductor performance was modeled using a physics-based model with predictive capability. The model was verified by measurements at various stages of the post-CMOS processing. Micromachined inductor quality factor is limited by series resistance up to a predicted metal thickness of between 6-10 μm     

RF circuit design aspects of spiral inductors on silicon

The design and optimization of spiral inductors on silicon substrates, the related layout issues in integrated circuits, and the effect of the inductor-Q an the performance of radio-frequency (RF) building blocks are discussed. Integrated spiral inductors with inductances of 0.5-100 nH and Q's up to 40 are shown to be feasible in very-large-scale-integration silicon technology. Circuit design aspects, such as a minimum inductor area, the cross talk between inductors, and the effect of a substrate contact on the inductor characteristics are addressed. Important RF building blocks, such as a bandpass filter, low-noise amplifier, and voltage-controlled oscillator are shown to benefit substantially from an improved inductor-Q     

新颖的衬底pn结隔离型硅射频集成电感

提出了一种新的减小硅集成电感衬底损耗的方法 .这种方法是直接在硅衬底形成间隔的 pn结隔离以阻止螺旋电感诱导的涡流 .衬底 pn结间隔能用标准硅工艺实现而不需另外的工艺 .本文设计和制作了硅集成电路 ,测量了硅集成电感的 S参数并且从测量数据提取了电感的参数 .研究了衬底结隔离对硅集成电感的品质因素 Q的影响 .结果表明一定深度的衬底结隔离能够取得很好的效果 .在 3GHz,衬底 pn结隔离能使电感的品质因素 Q值提高4 0 % .     

A broad-band lumped element analytic model incorporating skin effect and substrate loss for inductors and inductor like components for silicon technology performance assessment and RFIC design

We present a broad-band lumped element planar inductor model that is suitable for RFIC design in silicon technologies. We provide extensions of the modeling methodology to similar components such as differential inductors, baluns, and solenoid inductors. The analytic computation of the physics-based model components, incorporating both metal skin effect and substrate loss, is described. The model is validated using measured data from over 200 inductors made with five different silicon back-end process technologies. The physics-based implementation of the model allows its use for determining the optimum process technology characteristics for specific radio frequency integrated circuit (RFIC) designs. The analytical based implementation with lumped elements enables effective integration into a robust CAD system for efficient design of RFIC circuits.     

新颖的衬底pn结隔离型硅射频集成电感

提出了一种新的减小硅集成电感衬底损耗的方法.这种方法是直接在硅衬底形成间隔的pn结隔离以阻止螺旋电感诱导的涡流.衬底pn结间隔能用标准硅工艺实现而不需另外的工艺.本文设计和制作了硅集成电路,测量了硅集成电感的S参数并且从测量数据提取了电感的参数.研究了衬底结隔离对硅集成电感的品质因素Q的影响.结果表明一定深度的衬底结隔离能够取得很好的效果.在3GHz,衬底pn结隔离能使电感的品质因素Q值提高40%.     

Active inductors for GaAs and bipolar technologies

Integrated high performance gallium arsenide and silicon active inductor configurations for microwave frequencies are examined in this article. The existing topologies are considered and a new aspect of comparing the performance of different topologies based on a more complete analysis is utilised. Drawbacks of GaAs technology in this particular case are recognised, while benefits attained by using bipolar technology are presented. A theoretical basis for designing bipolar inductors is examined. On the basis of these studies a new method for raising the Q-factor of an active inductor is found and applied to two novel GaAs Q-enhanced active inductors. New applications for active high-Q resonators are found and their realisation aspects are considered. Integrated test circuits have been designed, and the simulated and experimental results are presented.     

Toroidal inductors for radio-frequency integrated circuits

Toroidal inductors achieve low loss by constraining magnetic flux to a well-defined path and away from ground planes and semiconducting substrates. This paper presents a micromachined implementation of the toroidal inductor, with focus primarily on microwave integrated circuits on a low-resistivity silicon wafer achieving a Q of 22 and a self-resonant frequency greater than 10 GHz. A verified analytic model is developed.     

CMOS-compatible micromachined edge-suspended spiral inductors with high Q-factors and self-resonance frequencies

This paper reports a new category of high-Q edge-suspended inductors (ESI) that are fabricated using CMOS-compatible micromachining techniques. This structure was designed based on the concept that the current was crowded at the edges of the conducting metal wires at high frequencies due to the proximity effect. The substrate coupling and loss can be effectively suppressed by removing the silicon around and underneath the edges of the signal lines. Different from the conventional air-suspended inductors that have the inductors built on membranes or totally suspended in the air, the edge-suspended structures have the silicon underneath the center of the metal lines as the strong mechanical supports. The ESIs are fabricated using a combination of deep dry etching and anisotropic wet etching techniques that are compatible with CMOS process. For a three-turn 4.5-nH inductor, a 70% increase (from 6.8 to 11.7) in maximum Q-factor and a 57% increase (from 9.1 to 14.3 GHz) in self-resonance frequency were obtained with a 11-/spl mu/m suspended edge in 25-/spl mu/m-wide lines.     

Surface micromachined solenoid on-Si and on-glass inductors for RFapplications

RF performance of surface micromachined solenoid on-chip inductors fabricated on a standard silicon substrate (10 Ω·cm) has been investigated and the results are compared with the same inductors on glass. The solenoid inductor on Si with a 15-μm thick insulating layer achieves peak quality (Q-) factor of 16.7 at 2.4 GHz with inductance of 2.67 nH. This peak Q-factor is about two-thirds of that of the same inductor fabricated on glass. The highest performance has been obtained from the narrowest-pitched on-glass inductor, which shows inductance of 2.3 nH, peak Q-factor of 25.1 at 8.4 GHz, and spatial inductance density of 30 nH/mm². Both on-Si and on-glass inductors have been modeled by lumped circuits, and the geometrical dependence of the inductance and Q-factor have been investigated as well     

Design and modeling of a micromachined high-Q tunable capacitor with large tuning range and a vertical planar spiral inductor

In wireless communication systems, passive elements including tunable capacitors and inductors often need high quality factor (Q-factor). In this paper, we present the design and modeling of a novel high Q-factor tunable capacitor with large tuning range and a high Q-factor vertical planar spiral inductor implemented in microelectromechanical system (MEMS) technology. Different from conventional two-parallel-plate tunable capacitors, the novel tunable capacitor consists of one suspended top plate and two fixed bottom plates. One of the two fixed plates and the top plate form a variable capacitor, while the other fixed plate and the top plate are used to provide electrostatic actuation for capacitance tuning. For the fabricated prototype tunable capacitors, a maximum controllable tuning range of 69.8% has been achieved, exceeding the theoretical tuning range limit (50%) of conventional two-parallel-plate tunable capacitors. This tunable capacitor also exhibits a very low return loss of less than 0.6 dB in the frequency range from 45 MHz to 10 GHz. The high Q-factor planar coil inductor is first fabricated on a silicon substrate and then assembled to the vertical position by using a novel three-dimensional microstructure assembly technique called plastic deformation magnetic assembly (PDMA). Inductors of different dimensions are fabricated and tested. The S-parameters of the inductors before and after PDMA are measured and compared, demonstrating superior performance due to reduced substrate loss and parasitics. The new vertical planar spiral inductor also has the advantage of occupying much smaller silicon areas than the conventional planar spiral inductors.     

Substrate noise coupling through planar spiral inductor

While precious studies on substrate coupling focused mostly on noise induced through drain-bulk capacitance, substrate coupling from planar spiral inductors at radiofrequency (RF) via the oxide capacitance has not been reported. This paper presents the experimental and simulation results of substrate noise induced through planar inductors. Experimental and simulation results reveal that isolation between inductor and noise source is less than -30 dB at 1 GHz. Separation by distance reduces coupling by less than 2 dB in most practical cases. Practical examples reveal an obstacle in integrating RF tuned-gain amplifier with sensitive RF receiver circuits on the same die. Simulation results indicate that hollow inductors have advantages not only in having a higher self-resonant frequency, but also in reducing substrate noise as compared to conventional inductors. The effectiveness of using a broken guard ring in reducing inductor induced substrate noise is also examined     

Physical modeling of spiral inductors on silicon

This paper presents a physical model for planar spiral inductors on silicon, which accounts for eddy current effect in the conductor, crossover capacitance between the spiral and center-tap, capacitance between the spiral and substrate, substrate ohmic loss, and substrate capacitance. The model has been confirmed with measured results of inductors having a wide range of layout and process parameters. This scalable inductor model enables the prediction and optimization of inductor performance     

双层螺旋RF MEMS电感的模拟与设计

分析了双层螺旋电感的等效电路模型,研究了一种与传统CMOS工艺兼容的MEMS工艺,通过腐蚀电感结构下的硅衬底使电感悬空.利用HFSS软件对一些双层螺旋微电感进行了模拟,模拟结果表明,相比传统单层电感,双层电感可以减少60%的芯片面积,10nH的电感也只需要很小的面积,经过MEMS后处理的双层螺旋电感的最大Q值都超过了20.     

应用于无线收发机关端的片上螺旋型电感的研究

这篇文章探讨了在现在的标准工艺条件下集成电感的设计和分析问题,包括片上螺旋型电感的有关版图,损耗机制,模型和参数提取问题,最后以一种被学术界广泛妆受的模拟工具对电感的有关设计进行了模拟,给出了模拟结果,并进行了分析,给出了设计片上电感应遵循的原,有着工艺技术和人们对电感的寄生效应的认识的加深,可以相信片上集成电感在高频电路中的应用将越来越广泛。     

Thermal effects in suspended RF spiral inductors

Self-heating effects on integrated suspended and bulk spiral inductors are explored. A dc current is fed through the inductors during measurement to emulate dc and radio frequency power loss on the inductor. A considerable drop in Q by /spl sim/18% at 36.5 mW is observed for suspended coils with 3-/spl mu/m aluminum metallization compared to reference inductors on bulk-Si. Simulations in Ansoft's ePhysics indicate that, due to the thermal isolation of the suspended coil, the power loss from resistive self-heating in the metal has to be transferred outwards through the metal turns. This also results in a thermal time constant. This time constant is measured to be /spl sim/10 ms, meaning that it can affect power circuits operating in pulsed mode.     

Design and simulation of integrated inductors on porous silicon in CMOS-compatible processes

We present a comprehensive approach of designing on-chip inductors using a CMOS-compatible technology on a porous silicon substrate. On-chip inductors realized on standard CMOS technology on bulk silicon suffer from mediocre Q-factor values partly because of the loss created by the Si substrate at higher frequencies, in addition to the metal losses. We examine the alternative of using porous Si as a thick layer isolating the Si substrate from the metallization in an otherwise standard CMOS technology. We present theoretical designs produced with full-wave Method-of-Moments simulations, verified by measurements in standard 0.18 μm CMOS technology using Al metallization. When porous Si is introduced in that technology, the same inductor metallization produced Q-factor enhancements of the order of 50%, compared to the same inductor on bulk crystalline silicon. We also produce optimized single-ended inductor designs using Cu on porous Si, in a 0.13 μm-compatible CMOS technology. The resulting Q-factors are enhanced by a factor of 2 and reach values of 30 or more in the 2–3 GHz frequency range. Even higher quality factors can be obtained in this technology when differential designs are used.     

Sub-nH Inductor Modeling and Design in 90-nm CMOS Technology for Millimeter-Wave Applications

Inductor design is an important issue in millimeter-wave CMOS circuits. In these frequencies the required inductance is very small and hence special structure is required for inductors. The quality factor is the most important design parameter for these inductors, especially in CMOS process. To incorporate these inductors in circuit simulation, a simple lumped model is necessary. This work proposes a simple and accurate model, developed for design and optimization of such inductors. This model is based on quasi-transverse-electromagnetic-mode assumption. To increase the model accuracy we have separately modeled the short-end section of the inductor. Model parameters are calculated using reported analytic equations and some new empirical equations. Using this model we have designed and optimized a 250-pH inductor with different shield layers, for STMicroelectronics 90-nm digital CMOS process. The accuracy of the model parameters and the evaluation of the model has been carried out using 2-D and method-of-momentss electromagnetic solvers in Advanced Design System, with the substrate modeled using foundry design kit data.