A Sub-0.2$^{circ}/$ hr Bias Drift Micromechanical Silicon Gyroscope With Automatic CMOS Mode-Matching

This paper describes a system architecture and CMOS implementation that leverages the inherently high mechanical quality factor (Q) of a MEMS gyroscope to improve performance. The proposed time domain scheme utilizes the often-ignored residual quadrature error in a gyroscope to achieve, and maintain, perfect mode-matching (i.e., $sim$0 Hz split between the high-Q drive and sense mode frequencies), as well as electronically control the sensor bandwidth. A CMOS IC and control algorithm have been interfaced with a 60 $mu{hbox {m}}$ thick silicon mode-matched tuning fork gyroscope $({rm M}^{2}mathchar"707B {rm TFG})$ to implement an angular rate sensing microsystem with a bias drift of 0.16$^{circ}/{hbox{hr}}$. The proposed technique allows microsystem reconfigurability—the sensor can be operated in a conventional low-pass mode for larger bandwidth, or in matched mode for low-noise. The maximum achieved sensor Q is 36,000 and the bandwidth of the microsensor can be varied between 1 to 10 Hz by electronic control of the mechanical frequencies. The maximum scale factor of the gyroscope is 88 ${hbox{mV}}/^{circ}/{hbox{s}}$ . The 3$~$ V IC is fabricated in a standard 0.6 $ mu{hbox {m}}$ CMOS process and consumes 6 mW of power with a die area of 2.25 ${hbox {mm}}^{2}$.      

A 2.4-GHz Resistive Feedback LNA in 0.13-$mu$m CMOS

A $g_{m}$-boosted resistive feedback low-noise amplifier (LNA) using a series inductor matching network and its application to a 2.4 GHz LNA is presented. While keeping the advantage of easy and reliable input matching of a resistive feedback topology, it takes an extra advantage of $g_{m}$ -boosting as in inductively degenerated topology. The gain of the LNA increases by the $Q$ -factor of the series RLC input network, and its noise figure (NF) is reduced by a similar factor. By exploiting the $g_{m}$-boosting property, the proposed fully integrated LNA achieves a noise figure of 2.0 dB, S21 of 24 dB, and IIP3 of ${- 11}~ hbox{dBm}$ while consuming 2.6 mW from a 1.2 V supply, and occupies 0.6 ${hbox {mm}}^{2}$ in 0.13-$mu{hbox {m}}$ CMOS, which provides the best figure of merit. This paper also includes an LNA of the same topology with an external input matching network which has an NF of 1.2 dB.      

Integrated Hydrogen-Sensing Amplifier With GaAs Schottky-Type Diode and InGaP–GaAs Heterojunction Bipolar Transistor

New hydrogen-sensing amplifiers are fabricated by integrating a GaAs Schottky-type hydrogen sensor and an InGaP–GaAs heterojunction bipolar transistor. Sensing collector currents ( $I_{rm CN}$ and $I_{rm CH}$) reflecting to $hbox{N}_{2}$ and hydrogen-containing gases are employed as output signals in common-emitter characteristics. Gummel-plot sensing characteristics with testing gases as inputs show a high sensing-collector-current gain $(I_{rm CH}/I_{rm CN})$ of $≫hbox{3000}$. When operating in standby mode for in situ long-term detection, power consumption is smaller than 0.4 $muhbox{W}$. Furthermore, the room-temperature response time is 85 s for the integrated hydrogen-sensing amplifier fabricated with a bipolar-type structure.      

Integrated Quadrature Couplers and Their Application in Image-Reject Receivers

Several fully-integrated multi-stage lumped-element quadrature hybrids that enhance bandwidth, amplitude and phase accuracies, and robustness are presented, and a fully-integrated double-quadrature heterodyne receiver front-end that uses two-stage Lange/Lange couplers is described. The Lange/Lange cascade exploits the inherent wide bandwidth characteristic of the Lange hybrid and enables a robust design using a relatively low transformer coupling coefficient. The measured image-rejection ratio is $>$ 55 dB over a 200 MHz bandwidth centered around 5.25 $~$GHz without any tuning, trimming, or calibration; the front-end features 23.5 dB gain, $-$79 dBm sensitivity, 5.6 dB SSB NF, $-$7$~$ dBm IIP3, $-$18 dB $S_{11}$ and a 1 mm $times$ 2 mm die area in 0.18$ mu{hbox {m}}$ CMOS.      

Arsenic-Segregated Rare-Earth Silicide Junctions: Reduction of Schottky Barrier and Integration in Metallic n-MOSFETs on SOI

As an attempt to considerably reduce the equivalent contact resistivity of Schottky junctions, this letter studies the integration of rare-earth silicides, known to feature the lowest Schottky barriers (SBs) to electrons, coupled with a dopant segregation based on arsenic $(hbox{As}^{+})$ implantation. Both erbium (Er) and ytterbium (Yb) have been considered in the implant-before-silicide (IBS) and implant-to-silicide flavors. It is shown that the two schemes coupled with a limited thermal budget (500 $^{circ}hbox{C}$) produce an SB below the target of 0.1 eV. The implementation of IBS arsenic-segregated $hbox{YbSi}_{1.8}$ junctions in an n-type SB-MOSFET is demonstrated for the first time resulting in a current-drive improvement of more than one decade over the dopant-free counterpart.      

A 5-GHz CMOS Type-II PLL With Low $K_{rm VCO}$ and Extended Fine-Tuning Range

A 5-GHz dual-path integer-$N$ Type-II phase-locked loop (PLL) uses an LC voltage-controlled oscillator and softly switched varactors in an overlapped digitally controlled integral path to allow a large fine-tuning range of approximately 160 MHz while realizing a low susceptibility to noise and spurs by using a low $K_{rm VCO}$ of 3.2 MHz/V. The reference spur level is less than $-$70 dBc with a 1-MHz reference frequency and a total loop-filter capacitance of 26 pF. The measured phase noise is $-$75 and $-$115 dBc/Hz at 10-kHz and 1-MHz offsets, respectively, using a loop bandwidth of approximately 30 kHz. This 0.25-${hbox{mm}}^{2}$ PLL is fabricated in a 90-nm digital CMOS process and consumes 11 mW from a 1.2-V supply.      

Cyclic Codes and Sequences From Generalized Coulter–Matthews Function

In this paper, we will study the exponential sum $sum_{xin {BBF}_q}chi(alpha x^{(p^k+1)/2}+beta x)$ that is related to the generalized Coulter–Matthews function $x^{(p^k+1)/2}$ with $k/{rm gcd}(m,k)$ odd. As applications, we obtain the following: the correlation distribution of a $p$-ary $m$-sequence and a decimated $m$-sequence of degree ${p^k+1 over 2}$;      

Single-Exclusion Number and the Stopping Redundancy of MDS Codes

For a linear block code ${cal C}$, its stopping redundancy is defined as the smallest number of check nodes in a Tanner graph for ${cal C}$, such that there exist no stopping sets of size smaller than the minimum distance of ${cal C}{bf .},$ Schwartz and Vardy conjectured that the stopping redundancy of a maximum-distance separable (MDS) code should only depend on its length and minimum distance.      

High-Voltage LDMOS With Charge-Balanced Surface Low On-Resistance Path Layer

A high-voltage lateral double-diffusion MOSFET (LDMOS) with a charge-balanced surface low on-resistance path (CBSLOP) layer is proposed and experimentally demonstrated using a modified CMOS process. The CBSLOP layer can not only provide a low on-resistance path in the on-state but also keep the charge balance between the N and P pillars of a surface low on-resistance path in the off-state, which results in improved breakdown voltage (BV). The experimental results show that the CBSLOP-LDMOS with a drift length of 35 $mu hbox{m}$ exhibits a BV of 500 V and specific on-resistance $(R_{{rm on}, {rm sp}}!)$ of 96 $hbox{m}Omega cdot hbox{cm}^{2}$, yielding to a power figure of merit $(BV^{2}!!/ !R_{{rm on}, {rm sp}})$ of 2.6 $hbox{MW}/hbox{cm}^{2}$ . The excellent device performances, coupled with a CMOS-compatible fabrication process, make the proposed CBSLOP-LDMOS a promising candidate for smart power integrated circuit.      

Wafer-Level Packaging With Soldered Stress-Engineered Micro-Springs

Micro-springs for integrated circuit test and packaging are demonstrated as soldered flip chip interconnects in a direct die to printed circuit board package. The spring interconnects are fabricated with thin film metallization as the last step in a wafer-scale process. The z-compliance of the interconnects can be used to test and/or burn-in parts in wafer form. After the parts are diced from the wafer, the springs then become the first-level (and often the last-level) interconnect between the chip and the board. The xy-compliance of the interconnect enables considerably large die to be soldered to an organic printed circuit board without underfill using a surface mount compatible process. To demonstrate this concept, daisy chain test vehicles were fabricated on die measuring 11.5 mm $times$ 6.5 mm with 48 spring contacts on a 0.8 mm $times$ 0.65 mm grid array, each spring measuring 400 $, mu$m $times$ 100 $mu$m. The parts were placed onto organic boards with screen printed solder paste using a pick and place machine. The parts were reflowed to complete the solder connection to each spring using eutectic and lead-free solder. Assembled parts have undergone ${>}20thinspace 000$ hot plate thermal cycles and ${>}1000$ oven thermal cycles without failure.      

A 3-D High-Frequency Array Based 16 Channel Photoacoustic Microscopy System for In Vivo Micro-Vascular Imaging

This paper discusses the design of a novel photoacoustic microscopy imaging system with promise for studying the structure of tissue microvasculature for applications in visualizing angiogenesis. A new 16 channel analog and digital high-frequency array based photoacoustic microscopy system (PAM) was developed using an Nd:YLF pumped tunable dye laser, a 30 MHz piezo composite linear array transducer, and a custom multichannel receiver electronics system. Using offline delay and sum beamforming and beamsteering, phantom images were obtained from a 6 $mu{hbox {m}}$ carbon fiber in water at a depth of 8 mm. The measured $-6~{rm dB}$ lateral and axial spatial resolution of the system was $100pm 5~mu{hbox {m}}$ and $45pm 5~mu{hbox {m}}$, respectively. The dynamic focusing capability of the system was demonstrated by imaging a composite carbon fiber matrix through a 12.5 mm imaging depth. Next, 2-D in vivo images were formed of vessels around 100 $mu{hbox {m}}$ in diameter in the human hand. Three-dimensional in vivo images were also formed of micro-vessels 3 mm below the surface of the skin in two Sprague Dawley rats.      

Lattice-Mismatched $hbox{In}_{0.4}hbox{Ga}_{0.6} hbox{As}$ Source/Drain Stressors With In Situ Doping for Strained $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Channel n-MOSFETs

We report the first demonstration of a strained $hbox{In}_{0.53} hbox{Ga}_{0.47}hbox{As}$ channel n-MOSFET featuring in situ doped $hbox{In}_{0.4}hbox{Ga}_{0.6}hbox{As}$ source/drain (S/D) regions. The in situ silicondoped $hbox{In}_{0.4}hbox{Ga}_{0.6}hbox{As}$ S/D was formed by a recess etch and a selective epitaxy of $hbox{In}_{0.4}hbox{Ga}_{0.6}hbox{As}$ in the S/D by metal–organic chemical vapor deposition. A lattice mismatch of $sim$0.9% between $ hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ and $hbox{In}_{0.4} hbox{Ga}_{0.6}hbox{As}$ S/D gives rise to lateral tensile strain and vertical compressive strain in the $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ channel region. In addition, the in situ Si-doping process increases the carrier concentration in the S/D regions for series-resistance reduction. Significant drive-current improvement over the control n-MOSFET with Si-implanted $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ S/D regions was achieved. This is attributed to both the strain-induced band-structure modification in the channel that reduces the effective electron mass along the transport direction and the reduction in the S/D series resistance.      

Universal Lossless Compression of Erased Symbols

A source ${mmb X}$ goes through an erasure channel whose output is ${mmb Z}$. The goal is to compress losslessly ${mmb X}$ when the compressor knows ${mmb X}$ and ${mmb Z}$ and the decompressor knows ${mmb Z}$. We propose a universal algorithm based on context-tree weighting (CTW), parameterized by a memory-length parameter $ell$. We show that if the erasure channel is stationary and memoryless, and ${mmb X}$ is stationary and ergodic, then the proposed algorithm achieves a compression rate of $H(X_0vert X_{-ell}^{-1}, Z^ell)$ bits per erasure.      

Analysis and Design of a CMOS UWB LNA With Dual- -Branch Wideband Input Matching Network

A wideband low-noise amplifier (LNA) based on the current-reused cascade configuration is proposed. The wideband input-impedance matching was achieved by taking advantage of the resistive shunt–shunt feedback in conjunction with a parallel LC load to make the input network equivalent to two parallel $RLC$-branches, i.e., a second-order wideband bandpass filter. Besides, both the inductive series- and shunt-peaking techniques are used for bandwidth extension. Theoretical analysis shows that both the frequency response of input matching and noise figure (NF) can be described by second-order functions with quality factors as parameters. The CMOS ultra-wideband LNA dissipates 10.34-mW power and achieves ${ S}_{11}$ below $-$8.6 dB, ${ S}_{22}$ below $-$10 dB, ${ S}_{12}$ below $-$26 dB, flat ${ S}_{21}$ of 12.26 $pm$ 0.63 dB, and flat NF of 4.24 $ pm$ 0.5 dB over the 3.1–10.6-GHz band of interest. Besides, good phase linearity property (group-delay variation is only $pm$22 ps across the whole band) is also achieved. The analytical, simulated, and measured results agree well with one another.      

AlGaN/GaN HEMTs With Low Leakage Current and High On/Off Current Ratio

In this letter, we propose using an oxide-filled isolation structure followed by $hbox{N}_{2}/hbox{H}_{2}$ postgate annealing to reduce the leakage current in AlGaN/GaN HEMTs. An off-state drain leakage current that is smaller than $hbox{10}^{-9} hbox{A/mm}$ (minimum $hbox{5.1} times hbox{10}^{-10} hbox{A/mm}$) can be achieved, and a gate leakage current in the range of $hbox{7.8} times hbox{10}^{-10}$ to $hbox{9.2} times hbox{10}^{-11} hbox{A/mm}$ ($V_{rm GS}$ from $-$10 to 0 V and $V_{rm DS} = hbox{10} hbox{V}$) is obtained. The substantially reduced leakage current results in an excellent on/off current ratio that is up to $hbox{1.5} times hbox{10}^{8}$. An improved flicker noise characteristic is also observed in the oxide-filled devices compared with that in the traditional mesa-isolated GaN HEMTs.      

High-Temperature High-Power Operation of GaInNAs Laser Diodes in the 1220–1240-nm Wavelength Range

We report on the high-temperature performance of high-power GaInNAs broad area laser diodes with different waveguide designs emitting in the 1220–1240-nm wavelength range. Large optical cavity laser structures enable a maximum continuous-wave output power of $>$8.9 W at ${T}=20 ^{circ}$C with emission at 1220 nm and are characterized by low internal losses of 0.5 cm$^{-1}$ compared to 2.9 cm$^{-1}$ for the conventional waveguide structures. High-power operation up to temperatures of 120 $^{circ}$C is observed with output powers of $>$4 W at ${T}=90 ^{circ}$C. This laser diode showed characteristic temperatures of ${T}_{0} =112$ K and ${T}_{1}=378$ K.      

A Low-Voltage Mobility-Based Frequency Reference for Crystal-Less ULP Radios

The design of a 100 kHz frequency reference based on the electron mobility in a MOS transistor is presented. The proposed low-voltage low-power circuit requires no off-chip components, making it suitable for application in wireless sensor networks (WSN). After a single-point calibration, the spread of its output frequency is less than 1.1% (3$sigma $) over the temperature range from $-{hbox{22}},^{circ}{hbox{C}}$ to 85$,^{circ}{hbox{C}}$ . Fabricated in a baseline 65$~$nm CMOS technology, the frequency reference circuit occupies 0.11$ hbox{mm}^{2}$ and draws 34 $ muhbox{A}$ from a 1.2 V supply at room temperature.      

Multigate GaN RF Switches With Capacitively Coupled Contacts

We present the analysis and the performance characteristics of novel III-Nitride multigate (MG) radio-frequency (RF) switches fabricated over AlGaN/GaN heterostructures using capacitively coupled contacts $(hbox{C}^{3})$. $ hbox{C}^{3}$ device technology does not require contact annealing and, thus, allows for fully self-aligned processing of MG devices with tight electrode spacing. The combination of $hbox{C}^{3}$ electrodes with MG RF switch design results in devices with significantly lower OFF-state capacitance, higher isolation, and higher RF switching power as compared to conventional FET-based RF switches.      

Investigation of Program Saturation in Scaled Interpoly Dielectric Floating-Gate Memory Devices

This paper investigates the program saturation in aggressively scaled interpoly dielectric (IPD) floating-gate (FG) cells for nand application. To describe the program saturation in IPD stacks containing thick suboxides $(geq hbox{4} hbox{nm})$ , a simple model was developed, directly yielding the maximum reachable programmed threshold voltage level for a given FG cell geometry. The presented model agrees very well to program saturation measurements carried out on a 48 nm FG nand technology with an IPD composed of $hbox{SiO}_{2}$ and $ hbox{Al}_{2}hbox{O}_{3}$. By extending the considerations to an arbitrary IPD, this paper represents the first attempt to quantify the IPD current blocking ability required for future scaled FG memory cells.      

Low On-Resistance High-Breakdown Normally Off AlN/GaN/AlGaN DHFET on Si Substrate

Ultrathin-barrier normally off AlN/GaN/AlGaN double-heterostructure field-effect transistors using an in situ SiN cap layer have been fabricated on 100-mm Si substrates for the first time. The high 2DEG density in combination with an extremely thin barrier layer leads to enhancement-mode devices with state-of-the-art combination of specific on-resistance that is as low as 1.25 $hbox{m}Omegacdothbox{cm}^{2}$ and breakdown voltage of 580 V at ${V}_{rm GS} = hbox{0} hbox{V}$ . Despite the 2-$muhbox{m}$ gate length used, the transconductance peaks above 300 mS/mm. Furthermore, pulsed measurements show that the devices are dispersion free up to high drain voltage ${V}_{rm DS} = hbox{50} hbox{V}$. More than 200 devices have been characterized in order to confirm the reproducibility of the results.