CMOS layout design of the hysteresis McCulloch-Pitts neuron

A McCulloch-Pitts neuron is the simplified neuron model which has been successfully used for many optimisation problems. The neural network with the hysteresis property can suppress the oscillatory behaviours of neural dynamics so that the convergence time is shortened. In this paper, digital CMOS layout design of the hysteresis McCulloch-Pitts neuron is presented. Based on simulation results using the hysteresis McCulloch-Pitts binary neuron model, a 6-bit fixed point 2's complement arithmetic was adopted for the calculation of the input U of each neuron. Each neuron needs 204 transistors and requires a 399 lambda *368 lambda layout area using the MOSIS scalable CMOS/bulk (SCMOS) VLSI technology with 2 mu m rule of P well, double level metal. Layout design of the hysteresis McCulloch-Pitts neuron chip was completed, and fabrication of the chip and the design for the test circuit for the fabricated CMOS VLSI chip are underway at present.<>     

A single-chip CMOS analog/digital mixed NTSC decoder

A single-chip CMOS LSI that integrates all analog-to-digital (A/D), digital-to-analog (D/A), peripheral, and digital signal processing circuits necessary for a digital National Television System Committee (NTSC) signal decoder is described. The LSI chip accepts composite NTSC video signals in analog form, digitizes them using the on-chip A/D converter, converts them to component RGB signals, and then converts the signals to analog form by using the on-chip D/A converters. The development of circuits that maximize use of the input digital data is discussed. A 6-b A/D circuit is used to reduce the circuit size. Circuits that help maintain acceptable picture quality despite 6-b resolution were developed. Besides analog NTSC signal input and RGB signal output, the IC can also input and output digital NTSC signals, Y/C (luminance, chrominance) signals, and RGB signals. Applications of the LSI are presented     

A CMOS analog timing recovery circuit for PRML detectors

A fully integrated analog timing recovery circuit for partial-response maximum-likelihood (PRML) detectors for digital magnetic storage is described. The circuit uses a decision-directed minimum mean-squared error (MMSE) algorithm and achieves phase acquisition within 100-bit periods at a maximum speed of 180 Mb/s. It dissipates 76 mW from a single 3.3-V supply and has an active die area of 1.8 mm² in a 1.2-μm CMOS process. At 180 Mb/s, the rms clock fitter is 15 ps and peak-to-peak jitter is 97 ps. The test results demonstrate the feasibility of an analog CMOS implementation of decision-directed MMSE timing recovery for PRML detectors     

0.3-μm mixed analog/digital CMOS technology for low-voltageoperation

A 0.3-μm mixed analog/digital CMOS technology for low-voltage operation has been demonstrated, including a new MOSFET structure with laterally doped buried layer (LDB) and a double-polysilicon capacitor with low voltage coefficient. The LDB-structure MOSFET provides constant threshold voltage which is independent of channel length, high current drivability 10% over that of a conventional structure, and low junction capacitance which is less than 1/2 that of the conventional structure. The double-polysilicon capacitor achieves a voltage coefficient of 1/10 that of a conventional capacitor by introducing arsenic ion implantation to the top polysilicon plate and a Si₃N₄ capacitor-insulator, despite the insulator thickness being scaled down to oxide-equivalent 20 nm     

Analog phase measuring circuit for digital CMOS ICs

A circuit measuring the phase of incoming asynchronous signals relative to the system clock in digital signal processing is described. The system clock can be in the range from 10 to 20 MHz, as is typical for video signal processing applications. As a reference in the asynchronous signal the positive or negative slope is taken. Its phase is measured with a resolution of 1/32 of a system clock cycle (approximately 1.5 to 3 ns). Pure digital CMOS technology without precision components is used, to enable combined integration on processor chips. Timing precision (jitter) is better than 200 ps without any adjustments. One external capacitor is needed     

An integrated analog CMOS Viterbi detector for digital magneticrecording

An analog Viterbi detector has been fabricated in a 2-μm double-poly p-well CMOS process. The detector takes a continuous-time analog input equalized to a class-IV partial response and produces the corresponding digital output at over 40 Mb/s while consuming less than 100 mW from a single 5-V supply. Measured performance is close to theoretical expectations and the performance is demonstrated to be robust with respect to changes in bias     

State of the art in the analog CMOS circuit design

This paper is not intended to cover CMOS analog circuit design exhaustively. Yet, it describes how much CMOS technology has been involved in analog circuit design despite the general opinion that CMOS is only suited for digital design. After some developments in the CMOS technology have been discussed, the analog building block scene is covered. The analog building blocks can roughly be divided into two subgroups: the switched-capacitor and the non-switched-capacitor building blocks. Following this subdivision different approaches are briefly looked at. Several tables conclude this review and indicate that new analog developments in CMOS circuit design are still to be expected. Next, the CAD tool development for analog CMOS is discussed, showing that there is still a lot to be done in the field of automated analog design. In conclusion, some ideas concerning analog CAD or, concerning CAD in a more general sense are described.     

A CMOS analog front-end circuit for an FDM-based ADSL system

A CMOS analog front-end circuit for an FDM-based ADSL system is presented. The circuit contains all analog functions including AGC amplifiers, continuous-time band pass filters, ΣΔ AD/DA converters, and digital decimation and interpolation filters. On-chip automatic tuning of the bandpass filters provides more than 300% center frequency range with 1% frequency accuracy. The higher-order ΣΔ AD/DA converters achieve 12-b data conversion at 1.54 Msamples/s with an oversampling ratio of only 32. The 0.7 μm CMOS circuit measures 65 mm² and consumes 1.9 W from a single 5 V power supply     

1-V bulk-driven CMOS analog programmable winner-takes-all circuit

In this paper, a 1-V bulk-driven analog winner-takes-all circuit with programmable k-winners capability is proposed. By presetting a set of binary bits, the desired k-winners-take-all or k-losers-take-all function is programmable. The proposed upward-and-downward searching greatly improves the response time. The chip has been fabricated with a 0.25-μm CMOS technology. Simulated results show that the response time of the winner-takes-all circuit is 50 μs under 5-mV identified resolution. The input range is approximately to be rail-to-rail. This work was in part supported by the Chip Implementation Center and the MOE Program of Promoting Academic Excellence of Universities under the Grant EX-93-E-FA09-5-4. Yu-Cherng Hung was born in Changhua, Taiwan, R.O.C., in 1964. He received the M. S. degree in electronics engineering from the National Chiao Tung University, Hsinchu, Taiwan, R.O.C., in 1992, and the Ph.D. degree in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 2004. From Dec. 1986 to Jan. 2005, he was with the Division of Computer/Information, Chinese Petroleum Corp., Taiwan. He is currently an Assistant Professor with the Department of Electronic Engineering, National Chin-Yi Institute of Technology, Taiwan, R.O.C. His main research interests include analog circuit design, low-voltage VLSI design, and neural network applications. Dr. Hung is a Member of Phi Tau Phi Honorary Scholastic Society, IEEE, and the Institute of Electronics, Information, and Communications Engineers (IEICE). Bin-Da Liu received the Ph.D. degrees in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1983. Since 1977, he has been on the faculty of the National Cheng Kung University, where he is currently a Distinguished Professor in the Department of Electrical Engineering and the Director of the SoC Research Center. During 1983–1984, he was a Visiting Assistant Professor in the Department of Computer Science, University of Illinois at Urbana-Champaign. During 1988–1992, he was the Director of Electrical Laboratories, National Cheng Kung University. He was the Associate Chair of the Electrical Engineering Department during 1996–1999 and the Chair during 1999–2002. Since 1995, he has been a Consultant of the Chip Implementation Center, National Applied Research Laboratories, Hsinchu, Taiwan. He has published more than 200 technical papers. He also contributed chapters in the book Neural Networks and Systolic Array Design (D. Zhang Ed. Singapore: World Scientific, 2002) and the book Accuracy Improvements in Linguistic Fuzzy Modeling (J. Casillas, O. Cordón, F. Herrera, and L. Magdalena Eds. Heidelberg, Germany: Springer-Verlag, 2003). His current research interests include low power circuit, neural network circuit, CMAC neural network, analog neural network architecture, design of programmable cellular neural networks, and very large-scale integration implementation of fuzzy/neural circuits and audio/video signal processors. Dr. Liu is a Fellow of IEEE and the Vice President of Region 10, IEEE Circuits and Systems Society. He served as a CAS Associate Editor of IEEE Circuits and Devices Magazine and an Associate Editor of IEEE Transactions on Circuits and Systems I: Regular Papers. He is serving as an Associate Editor of IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Chung-Yang Tsai was born in Mian-Li, Taiwan, R.O.C. He received the B.S. and M.S. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, R.O.C., in 2001 and 2003, respectively. His research interests include very large-scale integration design and signal processing.     

A broad-bandwidth mixed analog/digital integrated circuit for themeasurement of complex impedance

A broad-bandwidth measuring system for complex impedances is presented. The measuring principle, based on synchronous detection, is worked out mathematically. The final circuit is realized as a mixed analog/digital BiCMOS integrated circuit. The output of the IC is a modulated 100-Hz frequency and RS232. The phase accuracy of the system is 0.07° at 20 MHz and is mainly determined by the parameter deviation of transistors that share the same IC. The circuit enables measurement of a capacitance of up to 100 pF with an accuracy of ±1 pF, in parallel with a conductance of up to 100 mS. Apart from the impedance measuring circuit, the IC can process signals from other sensors, such as for temperature or pH. The design criteria for the IC are derived from the primary application in a sensor for water content and ionic concentration measurements in soil or other agricultural substrates     

CMOS digital duty cycle correction circuit for multi-phase clock

A digital duty cycle correction circuit with a fixed-delay rising-edge output is proposed for use in applications with the multi-phase clock and the standby mode. Two integrators are used in the duty cycle detector to eliminate the effect of reference voltage variations. The output duty cycle is adjusted to 50/spl plusmn/0.25% throughout the input duty cycle range from 20% to 80% at the frequency of 1.25 GHz. 0.18 /spl mu/m CMOS technology is used in this work.     

CMOS analog front end of a transceiver with digital echocancellation for ISDN

A CMOS analog front-end which contains a novel pulse-shaping circuit, an extremely linear-line-driver state, an oversampling second-order noise-shaping coder, and a wake-up signal detector is discussed. An analog front-end for 4B 3T coded signals is realized in a 2.5-μm CMOS technology and operates up to 4.5 km with 0.4-mm-diameter lines, needing only one 5-V power supply. It is possible to transmit 2B 1Q coded signals also, using a modified pulse-shaping circuit     

VLSI for analog/digital communications

Present trends and future prospects are discussed, emphasizing the prospects for fuller VLSI integration of low-power digital radio, for applications such as in-building wireless radio receivers. The main concern is with the front end of the receiver, including continuous-time analog and sampled analog VLSI filtering, and technologies that can mix analog and digital on the same chip. Prospects for the use of bipolar complementary metal-oxide semiconductor (BiCMOS) technology in communications are examined. Continuous-time monolithic filtering is discussed. As an example of a central receiver/transmitter component that one would like to integrate monolithically, the frequency synthesizer is considered     

标准CMOS工艺在高速模拟电路和数模混合电路中的应用展望

从速度、集成度、功耗和成本等几个方面深入的分析了利用标准CMOS工艺来设计开发高速模拟器件和混合处理芯片的现状及发展潜力。     

Monolithic analog adaptive equalizer integrated circuit for wide-band digital communication networks

This equaliser is presented with particular emphasis on architecture and performance. To reduce the size, cost, and power dissipation, and to improve the operation speed and performance, this equalizer IC employs many techniques such as all analog signal processing with parallel updating the weights and eliminating the offset according to the least mean-square algorithm, MOS VLSI fabrication process and switched capacitor technique. As the key building blocks, low- and high-speed MOS operational amplifiers and four-quadrant analog multipliers are specially developed. The 16 mm/SUP 2/ chip providing 5 taps operates on /spl plusmn/5 and 10 V power supplies with power dissipation of 570 mW. The maximum data rate is more than 200 kHz. For the linear adaptive equalizer configuration operating at a data rate of 100 kHz, the residual RMS distortion and convergence time are measured to be -40 dB and about 2 ms (200 iterations), respectively, when a binary signal with an initial RMS distortion of 40 percent (-7.96 dB) is applied.     

Hot-carrier-reliability design rules for translating devicedegradation to CMOS digital circuit degradation

Long term ring-oscillator hot-carrier degradation data and simulation results are compared to demonstrate that a circuit reliability simulator BERT can predict CMOS digital circuit speed degradation from transistor DC stress data. Initial fast degradation is noted and attributed to the “zero crossing” effect caused by PMOSFET current enhancement. Saturation drain current, measured at V_gs=V_ds=Vdd/2, is a better monitor for CMOS circuit hot-carrier reliability. We present generalized hot-carrier-reliability design rules, lifetime and speed factors, that translate DC device lifetime to CMOS digital circuit lifetime. The design rules can roughly predict CMOS circuit degradation during the initial design and can aid reliability engineers to quickly estimate the overall product hot-carrier reliability. The NMOSFET and PMOSFET lifetime factors are found to obey 4/ft_rise and 10/ft_fall, respectively. Typically, the NMOSFET and PMOSFET speed degradation factors are 1/4 and 1/2, respectively, with saturation region drain current as the monitor while, for a 100 MHz operating frequency and for an input rise time of 0.35 ns, the NMOSFET and PMOSFET lifetime factors are 120 and 300, respectively     

手持数字存储示波表模拟信号调理电路的设计

手持数字存储示波表在野外和现场测试中应用广泛,示波表模拟信号调理单元关系到示波表带宽和垂直测量精度.是示波表的关键电路单元.基于元源衰减网络、MAXIM公司MAX4534、MAX4518多路复用器以及EL5160、MAX4012低功耗、高速宽带运算放大嚣,给出数字存储示波表模拟信号调理单元的完整设计方案.该方案具有可程控、具备故障保护功能、耐高电压输入、垂直通道测量误差小于1%、电路带宽可达100 MHz、电路简单等特点,具有很高的实用价值.     

An 0.18-μm CMOS for mixed digital and analog applications withzero-volt-Vth epitaxial-channel MOSFETs

An 0.18-μm CMOS technology with multi-V_ths for mixed high-speed digital and RF-analog applications has been developed. The V _ths of MOSFETs for digital circuits are 0.4 V for NMOS and -0.4 V for PMOS, respectively. In addition, there are n-MOSFET's with zero-volt-V_th for RF analog circuits. The zero-volt-V_th MOSFETs were made by using undoped epitaxial layer for the channel regions. Though the epitaxial film was grown by reduced pressure chemical vapor deposition (RP-CVD) at 750°C, the film quality is as good as the bulk silicon because high pre-heating temperature (940°C for 30 s) is used in H₂ atmosphere before the epitaxial growth. The epitaxial channel MOSFET shows higher peak g_m and f_T values than those of bulk cases. Furthermore, the g_m and f_T values of the epitaxial channel MOSFET show significantly improved performances under the lower supply voltage compared with those of bulk. This is very important for RF analog application for low supply voltage. The undoped-epitaxial-channel MOSFETs with zero-V_th will become a key to realize high-performance and low-power CMOS devices for mixed digital and RF-analog applications     

An LP/CBP reconfigurable analog baseband circuit for software-defined radio receivers in 65 nm CMOS

A low pass (LP) and complex band pass (CBP) reconfigurable analog baseband circuit for software-defined radio (SDR) receivers is presented. It achieves 1–15 MHz LP bandwidth, 2–8 MHz CBP bandwidth and 0–36 dB gain range with 1 dB step. Nulling-resistor Miller feed-forward (NRMFF) differential-mode compensation, passive left half-plane (LHP) zero common-mode compensation and Quasi-Floating Gate (QFG) technique are proposed to improve the high frequency performance and driving capability of the embedded fully differential operational amplifier (Op-Amp). The analog baseband circuit has been implemented in 65 nm CMOS. It achieves 15.2 dB m/27.1 dB m IB/OB-IIP3, −2 dB m IP1dB and 71 dB m IIP2 while consuming 3.6–9.1 mW from a 1.2 V power supply and 0.75 mm² chip area.