利用UML-RT序列图支持基于事务的SoC系统级功能验证

SoC基于事务的验证方法面临的一个重要问题是如何设计验证系统级复杂交互行为的事务测试序列。基于场景的序列图是设计人员捕获系统级功能规约的良好方法。本文提出了一种利用UML-RT序列图捕获SoC各个IP核之间的通信协作行为,为基于事务的验证建立高层规约,指导系统级测试序列生成的方法。我们自行开发了一个基于构件的事务验证环境SoC-CBTVE,并在该环境中利用本文的方法对一个典型的SoC设计进行了验证和分析。实验结果表明,利用UML-RT序列图能够捕获SoC系统级IP核之间的复杂通信行为,有效支持SoC系统级功能验证。     

基于UML的SoC建模设计方法研究

随着集成电路制造工艺的发展, 嵌入式计算机应用向着SoC的方向发展.为了适应制造工艺对SoC设计能力的要求,提高SoC的设计效率,成为了很紧迫的必要任务.采用统一的 SoC系统级建模语言SystemC、软/硬件协同设计技术、基于IP核复用等技术的SoC设计流程, 在一定程度上满足了SoC设计要求.在现有SoC设计流程基础上,结合UML的模型驱动框架(M DA)设计方法,在当前的SoC设计流程的系统需求规约描述、硬件实时反应式系统建模、软件模块设计实现中采用UML针对SoC的轻量型扩展特性,可以很大程度地改进提高SoC的设计流程效率.     

片上系统高层等价性检验研究进展

针对近年来SoC领域的工作,首先分析了高层等价性检验的难点;然后从算法类型归类角度对各种高层等价性检验方法进行了概述评论,同时分析了各类算法的优缺点和现有算法的主要技术手段;最后讨论了SoC高层等价性检验方法目前面临的挑战,并对该领域今后的研究方向进行了展望.     

基于软件模拟的SoC功能验证技术研究进展

软件模拟验证在SoC设计中得到了广泛的研究和应用,是目前SoC功能验证的主要方法.文中从高度抽象化、可重用和自动化三个方面梳理和综述了基于软件模拟的SoC功能验证技术的研究进展.同时,基于断言的验证在SoC的功能验证技术中起到重要的辅助性作用,文中阐述了断言技术的研究进展.最后,对软件模拟验证技术的发展趋势进行了展望.     

基于UML的SoC建模设计方法研究

随着集成电路制造工艺的发展,嵌入式计算机应用向着SoC的方向发展。为了适应制造工艺对SoC设计能力的要求,提高SoC的设计效率,成为了很紧迫的必要任务。采用统一的SoC系统级建模语言SystemC、软/硬件协同设计技术、基于IP核复用等技术的SoC设计流程,在一定程度上满足了SoC设计要求。在现有SoC设计流程基础上,结合UML的模型驱动框架（MDA）设计方法,在当前的SoC设计流程的系统需求规约描述、硬件实时反应式系统建模、软件模块设计实现中采用UML针对SoC的轻量型扩展特性,可以很大程度地改进提高SoC的设计流程效率。     

SoC通讯体系结构的高层建模技术研究

片上通讯设计是SoC系统设计的关键。本文着重从高层建模上研究SOC通讯体系结构设计。首先概述了SoC的通讯体系结构设计,其次介绍了片上通讯体系结构的高层建模方法,然后介绍了高层片上通讯体系结构的快速仿真方法,最后介绍了我们设计实现的Hi-SoComm系统。     

智能语音SoC模拟前端研究进展

在人工智能语音交互应用中,语音SoC中的模拟前端电路承担着将麦克风输出模拟信号数字化的重任,是语音模拟信号与数字处理单元的桥梁。由于复杂语音环境应用、器件失配等非理想因素的影响,模拟前端的功能和动态性能受到极大限制。对语音SoC中的模拟前端电路进行了分析,重点论述了目前模拟前端设计的结构特点以及发展现状,并对设计面临的挑战提出了研究思路,展望了发展趋势。     

操作系统可配置智能卡SoC设计

在普通智能卡SoC系统结构基础上,通过引入存储器管理机制,提出了一种可通过总线接口实现操作系统再配置的智能卡SoC设计.在所给出的智能卡SoC系统中,通过存储器管理机制可根据实际需要调节代码区与数据区存储器容量,继而对系统中的存储器资源进行有效整合,充分利用存储器资源.针对操作系统的下载配置,设计了一种用于模拟总线接口通信的仿真测试方法,很好的模拟了操作系统配置全过程,给出了仿真波形.     

大规模SoC设计中的高效FPGA验证技术的研究与实现

一种针对大规模SoC设计的高效FPGA验证流程,分析了该流程所涉及的关键技术:通用硬件平台设计、FPGA软件环境设计和软硬件协同验证等。采用这些技术,FPGA平台可以快速且真实地模拟芯片应用平台,从而实现软硬件并行设计和协同验证。该验证流程已灵活应用于大规模SoC项目设计中,大大提高了SoC产品的研发效率。     

基于uC/OS-II的“龙芯1”SoC验证方法

片上系统(SoC)的设计日益复杂,规模趋于庞大,这使得SoC的功能验证与测试成为IC设计的瓶颈.uC/OS-II是一种简洁的、可移植的、可裁减的与支持多任务的嵌入式实时操作系统.本文介绍了uC/OS-II在基于"龙芯1"SoC上的移植工作,重点讨论了在虚拟仿真与FPGA验证平台两种环境下运行uC/OS-II及其上层应用程序来测试"龙芯1"SoC的方法,并取得了良好的效果.     

可重构片上系统设计流程中的动态重构问题研究

近年来,可重构片上系统已成为科学研究及嵌入式应用领域中应对复杂计算需求的有效技术解决方案.针对目前缺少一个从系统级设计到应用实现,统一、综合规划动态重构问题的系统设计流程,以及动态重构过程对系统设计人员不透明等问题,在系统设计层给出了一种过程级软硬件统一编程模型.在此框架内,设计人员通过调用已根据应用特性进行优化的软硬件协同函数,即可利用高级语言完成系统功能描述;在细节设计层提出了基于单位面积加速比的软硬件任务调度算法,实时管理动态可重构资源;在应用实现层,以可重构专用图形加速卡为原型系统,论述动态可重构系统实现中的关键技术.实验及测试结果验证了通过将动态重构问题置于整个系统设计流程中予以考虑,能够达到提升系统开发效率之目的.     

Interface design for core-based systems

The authors propose the use of temporal abstraction in system-on-chip design and describe its benefits vis-a-vis traditional approaches. Their approach allows rapid integration of legacy cores to meet high-level system requirements     

A Functional Programming Framework for Latency Insensitive Protocol Validation

Latency insensitive protocols (LIPs) have been proposed as a viable means to connect synchronous IP blocks via long interconnects in a system-on-chip. The reason why one needs to implement LIPs on long interconnects stems from the fact that with increasing clock frequencies, the signal delay on some interconnects exceeds the clock period. Correctness of a system composed of synchronous blocks communicating via LIPs is established by showing latency equivalence between a completely synchronous composition of the blocks, and the LIP based composition. A design flow based on a synchronous composition specification, and stepwise refinement to LIP composition can be easily conceived, and a proof obligation to show latency equivalence between the synchronous specification and the refinement needs to be discharged. In this work, we propose a functional programming based framework for modeling and simulating LIP, and implement the semantics of various refinement steps in the programming model, so we can validate the LIP model against the original system within this functional programming framework. Such validation becomes easier due to the inherent denotational model of functional languages. We specifically use Standard ML to model the original system implementation as well as its latency insensitive version and compare the two by creating a model that contains both, giving them the same inputs and checking their outputs to be latency equivalent.     

GNU Emacs as a dynamically extensible programming environment

GNU Emacs is usually used only as an extensible editor. However, the ability to integrate inferior processes into GNU Emacs makes it an attractive programming environment. Like Interlisp and Smalltalk-80, GNU Emacs can be extended dynamically by its user. Unlike these programming environments, it can be used easily as a programming environment for an arbitrary programming language, and not just for its extension language. This paper discusses the methods of extending GNU Emacs and how we have applied them in creating a programming environment for a high-level specification language called AGENT.     

A rule-based system for generating a ladder logic control program from a high-level systems model

In this article an interface between a high-level specification of a system and a logic controller of that system is developed. The interface is based on a number of rules to transform an IDEF0 specification into an intermediate-level Petri-net-based controller and to transform the intermediate specification into a ladder logic program which can be run on a PLC. These rules could be used as a basis for developing an expert system to handle the interface. Such an expert system provides an environment for rapid prototyping and analysis of controllers.     

NoC synthesis flow for customized domain specific multiprocessor systems-on-chip

The growing complexity of customizable single-chip multiprocessors is requiring communication resources that can only be provided by a highly-scalable communication infrastructure. This trend is exemplified by the growing number of network-on-chip (NoC) architectures that have been proposed recently for system-on-chip (SoC) integration. Developing NoC-based systems tailored to a particular application domain is crucial for achieving high-performance, energy-efficient customized solutions. The effectiveness of this approach largely depends on the availability of an ad hoc design methodology that, starting from a high-level application specification, derives an optimized NoC configuration with respect to different design objectives and instantiates the selected application specific on-chip micronetwork. Automatic execution of these design steps is highly desirable to increase SoC design productivity. This work illustrates a complete synthesis flow, called Netchip, for customized NoC architectures, that partitions the development work into major steps (topology mapping, selection, and generation) and provides proper tools for their automatic execution (SUNMAP, xpipescompiler). The entire flow leverages the flexibility of a fully reusable and scalable network components library called xpipes, consisting of highly-parameterizable network building blocks (network interface, switches, switch-to-switch links) that are design-time tunable and composable to achieve arbitrary topologies and customized domain-specific NoC architectures. Several experimental case studies are presented In the work, showing the powerful design space exploration capabilities of the proposed methodology and tools.     

一种扩展UML/UP的需求分析方法

UML是面向对象分析和设计的工业标准;UP(Unified Process,统一过程)是使用UML作为建模语言的软件工程过程.UML和UP结合在一起成为一种很强大的软件工程方法学.UML/UP作为方法学,在需求方面存在两大不足:需求表达能力不强;需求表达与后续的系统分析和设计有较大的鸿沟.分析了需求工程中用例和场景分析以及用例图示的高层设计方法.在此基础上,提出了在需求方面增强了UML/UP方法.     

A 15 Year Perspective on Automatic Programming

Automatic programming consists not only of an automatic compiler, but also some means of acquiring the high-level specification to be compiled, some means of determining that it is the intended specification, and some (interactive) means of translating this high-level specification into a lower-level one which can be automatically compiled.     

支持双拓扑结构的片上网络评估高层仿真平台

为实现高效的NoC（片上网络）性能评估, 缩短系统芯片的开发周期, 针对时钟精确级的NoC仿真方法进行研究, 提出了一种新型的高层次、高效率仿真平台, 与仅支持网格拓扑结构的传统仿真器相比, 其创新地支持了网格和环型双拓扑结构的性能评估, 同时支持虚通道扩展的路由器结构设计, 能快速得到网络的延迟、吞吐率、功耗等性能结果。实验结果表明, 该仿真平台能准确模拟NoC功能行为, 快速获得其仿真性能, 为NoC设计验证提供了高效的方法。