基于脉动阵列的FIR滤波器设计

为了提高FIR滤波器的运算速度,把脉动阵列的处理器结构和FIR滤波器相结合,设计了高效的FIR滤波器。该结构具有模块化、规则性和高度流水的特点。在FPGA上验证,实验结果表明,该设计达到了较高的运算速度,可以满足数字信号处理中高效、实时的要求。而且该结构易于扩展,可实现任意阶的FIR滤波器。     

基于并行流水线结构的可重配FIR滤波器的FPGA实现

数字信号处理常常是计算密集和高性能应用所要求的.FIR滤波器由于具有稳定性和简单性,在数字信号处理中常被采用.随着实时性和低成本要求的提高,对FIR滤波器的要求也越来越高.单一的流水结构和并行FIR结构都不能很好地满足要求.因此,提出一种FPGA实现的并行流水结构的FIR滤波器的实现方案.     

基于并行流水线结构的可重配FIR滤波器的FPGA实现

数字信号处理,常常是计算密集和高性能需求的。FIR滤波器由于其稳定和简单,在数字信号处理中常被采用。随着实时性和低成本要求的提高,对FIR滤波器的要求也越来越高。单一的流水结构和并行FIR结构都不能很好地满足实现性要求。因此,在这里提出一种用于FPGA实现的并行流水结构的FIR滤波器的实现方案。     

基于FPGA的高速数字FIR滤波器设计

本文在分析传统FIR数字滤波器的基础上,设计了一种面向时序和面积优化的高速数字FIR滤波器结构。和传统的数字FIR滤波器比较,该结构具有速度快,面积小,易于扩展等特点。采用该结构,实现了一个基于FPGA的14阶的数字FIR滤波器。     

多级并行流水FIR数字滤波器的设计与验证

在雷达接收、语音图像处理、模式识别、无线通信等领域,数字滤波器已经成为重要组成部分。通过分析和研究FIR数字滤波器的结构特点,结合实际的工程实践需求,设计了一种多级并行流水FIR数字滤波器,并提出了一种精确而又简便的冲击响应系数的量化方法,即基于最小冲击响应系数按等比例量化的方法。这种方法不仅可以根据具体的设计要求随意更改设计位宽,还能保障设计的精度。通过编写Verilog HDL进行了设计实现,Modelsim仿真与Matlab仿真对比结果表明,各项参数均满足设计要求。     

数字多普勒系统中的窄带滤波器的设计方法

随着软件无线电技术的发展,使信号的采样频率越来越高,而在高采样率的条件下,进行窄带FIR滤波器的设计是非常困难的。本文采用多抽样率结构来设计窄带FIR滤波器,使窄带FIR滤波器易于实现。另外利用多级结构并使用特殊滤波器可以有效地实现窄带FIR滤波器,通过多个滤波器的级联,放宽了对每个滤波器的要求,从而使滤波器的总的乘法系数个数减少,乘法运算率减小,同时又不增加滤波器结构的复杂。     

FPGA实现FIR抽取滤波器的设计

采用基于分布式算法思想的方法来设计FIR滤波器,利用FDAtool设计系统参数,计算滤波器系数,同时为了要满足系统要求考虑系数的位数。根据FIR数字滤波器结构,对FIR数字滤波器的FPGA实现方法进行分析。     

基于TMS320C5402的FIR数字滤波器的设计

DSP由于其本身具有并行的硬件乘法器、流水结构以及快速的片内存储器等资源，其技术已广泛地应用于数字信号处理的各个领域。本文主要研究了FIR滤波器的窗函数算法的基本思想及在定点DSP芯片上实现FIR数字滤波器设计方法，讨论了在具体实现时如何提高数字滤波器的计算精度和防止输出结果溢出问题，最后给出在C54系列DSK进行验证的程序和滤波前后的时域、频域的对比图。实践证明，该滤波器准确度高、稳定性好，易于移植使用，具有较强的实用性与灵活性。     

基于FPGA的FIR滤波器设计

数字滤波器在数字信号处理中占有很重要的地位,该文介绍了FIR滤波器的两种实现算法：乘累加算法和优化的分布式算法,其中分布式算法作为优化算法进行研究。其次,根据FIR滤波器理论,采用线性相位结构优化滤波器的设计。并给出了FIR滤波器的模块划分和FIR滤波器的主要模块的实现,最后对FIR滤波器进行了系统仿真和验证。     

利用常系数乘法器设计高效FIR滤波器

介绍了一种用常系数乘法器 (KCM )来设计FIR滤波器的方法。详细阐述了FIR滤波器的结构、设计过程及其用KCM设计方法的优越性     

A low power 8-tap digital FIR filter for PRML read channels

This paper presents a low power 8-tap digital Fourier infrared (FIR) filter for partial response signalling with maximum likelihood (PRML) disk-drive read channels. Enhancements on power consumption and speed are achieved by adopting the row compression scheme with a proposed conditional carry selection method. The 8-tap digital FIR filter is fabricated by 0.8µm CMOS technology and occupies by 3.9mm × 1.5mm. The experimental results show that the FIR filter operates up to 180MHz and dissipates 1.4mW MHz^?1 with 3.7V power supply. It is proved that 20% power reduction is readily attainable with the proposed scheme.     

DSSS系统中基于WHT的自适应干扰抑制

本文提出了一种新的DSSS系统自适应干扰抑制方案。针对Wigner-Ville分布的不足,采用WHT来分析接收信号,并从中提取干扰瞬时频率以设计时变IIR滤波器。和通常采用的线性相位FIR滤波器相比,IIR滤波器具有理想的点阻特性。仿真结果证实IIR滤波器的BER性能好于FIR滤波器。     

Power-efficient FIR filter architecture design for wireless embedded system

This paper presents a novel approach for implementing power-efficient finite-impulse response (FIR) filters that requires less power consumption than traditional FIR filter implementation in wireless embedded systems. The proposed schemes can be adopted in the direct form FIR filter and achieve a large amount of reduction in the power consumption. By using a combination of proposed methods, balanced-modular techniques with retiming and separated processing data-flow scheme with modified canonical signed digit (CSD) representation, experimental results show that the proposed scheme reduce 76% power consumption of the original direct-form structure with slight area overhead.     

Low power multiplication scheme for FIR filter implementation onsingle multiplier CMOS DSP processors

A new multiplication scheme is proposed, for application to single multiplier CMOS based DSP processors, for the implementation of low-power digital FIR filters through the reduction of switching activity within the multiplier section of the filter. The scheme operates in conjunction with a transpose direct form FIR filter structure and a modified DSP processor architecture, through a significant reduction in power can be obtained by using algorithms to order the filter coefficients. This reduction is demonstrated using two basic examples, with different wordlengths and filter orders, achieving up to 63% reduction in switching activity     

Design of linear combination of weighted medians

This paper introduces a novel nonlinear filtering structure: the linear combination of weighted medians (LCWM). The proposed filtering scheme is modeled on the structure and design procedure of the linear-phase FIR highpass (HP) filter in that the linear-phase FIR HP filter can be obtained by changing the sign of the filter coefficients of the FIR lowpass (LP) filter in the odd positions. The HP filter can be represented as the difference between two LP subfilters that have all positive coefficients. This representation of the FIR HP filter is analogous to the difference of estimates (DoE) such as the difference of medians (DoM). The DoM is essentially a nonlinear HP filter that is commonly used in edge detection. Based on this observation, we introduce a class of LCWM filters whose output is given by a linear combination of weighted medians of the input sequence. We propose a method of designing the 1-D and 2-D LCWM filters satisfying required frequency specifications. The proposed method adopts a transformation from the FIR filter to the LCWM filter. We show that the proposed LCWM filter can offer various frequency filtering characteristics including “LP,” “bandpass (BP),” and “HP” responses     

High-performance FIR filter design based on sharing multiplication

Finite impulse response (FIR) filtering can be expressed as multiplications of vectors by scalars. We present high-speed designs for FIR filters based on a computation sharing multiplier which specifically targets computation re-use in vector-scalar products. The performance of the proposed implementation is compared with implementations based on carry-save and Wallace tree multipliers in 0.35-/spl mu/m technology. We show that sharing multiplier scheme improves speed by approximately 52 and 33% with respect to the FIR filter implementations based on the carry-save multiplier and Wallace tree multiplier, respectively. In addition, sharing multiplier scheme has a relatively small power delay product than other multiplier schemes. Using voltage scaling, power consumption of the FIR filter based on computation sharing multiplier can be reduced to 41% of the FIR filter based on the Wallace tree multiplier for the same frequency of operation.     

Modified RHKF Filter for Improved DR/GPS Navigation against Uncertain Model Dynamics

In this paper, an error compensation technique for a dead reckoning (DR) system using a magnetic compass module is proposed. The magnetic compass‐based azimuth may include a bias that varies with location due to the surrounding magnetic sources. In this paper, the DR system is integrated with a Global Positioning System (GPS) receiver using a finite impulse response (FIR) filter to reduce errors. This filter can estimate the varying bias more effectively than the conventional Kalman filter, which has an infinite impulse response structure. Moreover, the conventional receding horizon Kalman FIR (RHKF) filter is modified for application in nonlinear systems and to compensate the drawbacks of the RHKF filter. The modified RHKF filter is a novel RHKF filter scheme for nonlinear dynamics. The inverse covariance form of the linearized Kalman filter is combined with a receding horizon FIR strategy. This filter is then combined with an extended Kalman filter to enhance the convergence characteristics of the FIR filter. Also, the receding interval is extended to reduce the computational burden. The performance of the proposed DR/GPS integrated system using the modified RHKF filter is evaluated through simulation.     

TDD-CDMA系统的一种新的多径发送分集方案

本文提出了ＴＤＤ－ＣＤＭＡ系统的一种新的多径分集方案。它在发送端采用一个ＦＩＲ滤波器,面在接收端采用ＲＡＫＥ接收机实现多径合并。分析结果表明对ＦＩＲ滤波器的系统进行优化的问题椒于求解矩阵的牲玫特征向量的问题,而最大的特征值所对应的特征向量就是最佳ＦＩＲ滤波器的抽头系数。本文还分析了多天线的情况,此时相当于２维时空信号处理。数值分析表明采用上述方案的系统的输出信噪比（ＳＮＲ）较之通道的ＲＡＫＥ系统或     

Missing Data Compensation for Safety-Critical Components in a Drive-by-Wire System

In this article, a new multistep ahead predictive filtering scheme is introduced. The proposed technique is essential for proper operation of safety-critical components in a drive-by-wire car. Because limited computational time and memory are available in drive-by-wire systems, the main advantage of our scheme is that it only requires one set of finite impulse response (FIR) filter weights to be tuned while it can be used for different numbers of steps ahead predictions. To verify and compare the proposed filter, our model and four competing methods were applied to predict up to four missing samples of displacement sensor data from a brake pedal in a brake-by-wire system. Experimental results show that prediction performance of our proposed FIR filter is higher than, or at least comparable to, other filters with the same memory requirements and the computational overhead of data missing handling by our proposed method is considerably lower than other comparable methods. Hence, the proposed filter has a superior performance in missing data compensation for drive-by-wire systems.     

内插FIR数字滤波器的多相实现

提出一种内插FIR数字滤波器基于多相结构的优化实现方法.利用多相结构各子滤波器的自身对称和镜像对称特性,复用加权求和单元,显著降低了实现复杂度.以384阶、4倍内插SRRC滤波器的FPGA实现为例.验证了所提多相结构优化实现方法的优越性.