基于PI7C9X130的PCIE转PCI电路设计与实现

很多技术和设备都是基于外设部件互连标准(PCI)的,因接口技术等原因并没有大面积过渡到高速串行计算机扩展总线标准(PCIE),需要将PCIE与PCI进行数据转换后接入这些设备,所以有必要对PCIE转PCI数据转换技术进行研究.为了更加方便且高效地进行PCIE转PCI总线高速数据转换,设计了基于PI7C9X130的PCI...     

基于PCIE的多FC子卡测试设备的设计与实现

通过对FC子卡测试需求的分析,文章提出了一种基于PCIE接口的多FC子卡测试设备的设计方法.主要采用PCIE交换进行总线扩展,最后经过实现和验证,结果显示该设计可以很好的满足测试和试验要求,并且该设计通用性好,通过对该设计的升级改进,可以适用更多的PCI/PCIE设备,具有一定的实用意义.     

基于PCIE总线的多DSP系统接口设计和驱动开发

开发了多DSP雷达信号处理板卡。对DSP互连、DSP与FPGA通信以及基于Xilinx FPGA的PCIE总线进行设计。系统可扩展性好、效率高。用DriverStudio开发了WDM总线驱动程序,具有很好的通用性和可移植性。     

一种自路由群组交换结构的无缓存能耗优化模型

考虑到缓存是路由交换通信设备能耗的主要来源,该文从交换网络无缓存节能的构想出发,提出了一种自路由群组交换结构的无缓存能耗优化模型。该模型采用G倍统计线复用路由单元和Banyan类交换互连建立群组交换结构,在满足业务对阻塞率和时延性能要求的基础上,采用无内部缓存、路由单元输入输出端口数扩展和级间互连线优化设计来达到节能的目的。相同网络性能下,缓存能耗和结构能耗的量化比较表明该无缓存结构能耗小。仿真实验结果证明:结构参数G越大,网络级数k越小,路由单元能耗越小,在Banyan类交换互连结构中,分治(Divide-and-Conquer, DC)互连方式的级连线能耗最小。     

IDT支持基于标准的交换和互连解决方案

一年前,IDT在收购ZettaCom公司后成立了串行交换部门,旨在推动基于标准的交换和互连技术。在分析了各种互连协议及交换和互连市场的发展趋势后,IDT确定了今后重点支持的四个方向,分别为:针对服务器和存储市场优化的PCI Express,针对通信市场优化的先进交换互连(ASI)技术,针对通     

帧中继及其应用

帧中继是局域网(LAN)远程互连的重要手段之一,也是一个新型的数据通信业务.本文围绕以帧—元交换技术实现帧中继的Stratacom的高速分组交换设备,系统地讨论了帧中继技术及其应用.     

基于ATM交换的虚拟网

基于ＡＴＭ交换的虚拟网●许毅平胡为周曼丽自网络诞生以来，局域网互连一直是人们普遍关注的问题。第一代局域网互连设备网桥，是基于网络第二层的互连，其速度快但缺乏智能性，随着网络结构复杂程度的扩大，容易导致广播风暴和网络的不稳定性。路由器作为第二代网络互连...     

基于FPGA的FC交换机设计与验证

为了满足现代航空电子系统大规模数据传输的要求,带宽高且延时低的FC技术(Fibre Channel)逐渐取代传统1553总线,成为新一代航电系统的数据总线。FC交换机是以光纤作为主要传输介质,完成FC网络系统中各节点的信息交换功能的设备。文中设计使用Xilinx公司的FPGA逻辑电路开发套件,根据FC协议设计FC-1层和FC-2层以完成普通帧和ASM帧的转发,参照Round_Robin算法实现交换机转发调度,分析研究Xilinx PCIE硬核模块,实现具有PCIE主机接口的FC光纤交换机。方案给出了关键模块的结构图和设计思想,实现的功能经过仿真,达到了设计要求。     

JZH-01智能人工长途系统的技术分析

JZH-01智能人工长途电话交换系统是以计算机网络技术、数字交换技术和通信技术为基础,以长途人工通信体制、规范为依据研制出来的新一代长话设备.该设备是在由NOVELL计算机局域网与数字交换网络互连形成的智能综合业务平台上完成的,计算机座席通过键盘操作完成对交换网络、线路的接续控制,实现了在数字交换机上完成传统人工插塞及电话业务的快速连接操作,并     

基于PCIE驱动程序的数据传输卡DMA传输

为提高数据传输速度,研制了一套基于PCIE接口的数据发送和接收系统。该系统主要由4部分组成:数据发送卡、数据接收卡、PCIE驱动程序以及上位机应用程序。文中介绍了数据传输卡的基本原理和构成,重点研究了在Windows XP系统下利用WinDriver开发PCIE设备驱动程序的主要步骤、DMA数据传输的实现和中断响应的处理。经测试,该数据传输系统比较稳定,开发的驱动程序可以实现数据的高速传输。     

A Preliminary Study about SEU Effects on Programmable Interconnections of SRAM-based FPGAs

SRAM-based Field Programmable Gate Arrays (SRAM-FPGA) are more and more employed in today’s applications. In space and avionic applications their operations might be harmed by occurrence of radiation-induced upsets, or Single Event Upsets (SEU), which require the adoption of mitigation techniques. In these devices the majority of the configuration memory rules the interconnection setting. In devices employing “switch matrix” routing, the density of interconnections in switch arrays seems to be a critical point. The higher the interconnection density (i.e., the higher the number of interconnection segments activated by the same switch matrix), the higher the probability of an upset due to a configuration bit controlling the switch matrix. This paper presents an approach to estimate the SEU sensitivity of programmable interconnections of SRAM-based FPGAs as a function of the density of programmable interconnection points inside device configurable logic blocks. A probabilistic model of the SEU effects in programmable interconnection points of Xilinx SRAM-FPGAs is described. The application of the proposed approach to a set of sample designs is illustrated.     

Crosspoint switch equipped with an interface for serial opticalinterconnection

A crosspoint switch was developed that has an interface for serial optical interconnection. By using optoelectronic devices, cascaded switching was achieved through serial optical interconnection up to a bit rate of 10 Gb/s     

TORUS: terabit-per-second ATM switching system architecture basedon distributed internal speed-up ATM switch

A high-speed and distributed ATM switch architecture, called the TORUS switch, is proposed with the aim of achieving a terabit-per-second ATM switching system. The switch is a distributed and scalable internal speed-up crossbar-type ATM switch with cylindrical structure. The self-bit-synchronization technique and optical interconnection technology are combined to achieve gigabit-rate cell transmission, where high-density implementation technologies such as multichip module technology are not required at all. Also, distributed contention control based on the fixed output-precedence scheme is newly adopted. This control is very suitable for high-speed devices because its circuit is achieved with only one gate in each crosspoint. A TORUS switch is fabricated as a 4×2 switch module using optical interconnection technology and very high-speed crosspoint LSIs, constructed using an advanced Si-bipolar process. Measured results confirm that the TORUS switch can be used to realize an expandable terabit-rate ATM switch     

基于RapidIO的双主机节点嵌入式系统互联设计

分布式并行计算的发展对嵌入式系统互联技术提出了更高的要求,RapidIO可提供芯片间、板间的高性能互联,传输效率高于PCIE和千兆以太网。文中给出了一种基于RapidIO的双主机节点嵌入式系统互联的设计方案、硬件设计及其软件实现,并对系统功能和性能进行验证。验证结果表明,该系统性能稳定、可靠,并为新一代高性能嵌入式系统互联提供了良好的解决方案。     

Ultra-high-bit-rate networking: from the transcontinental backboneto the desktop

The advances in photonic device technologies are bringing ultra-high-bit-rate networking-at speeds towards 100 Gb/s and beyond-much closer to practical reality. It is increasingly likely that in the longer term ultrafast optical time-division techniques-together with wavelength multiplexing-will be used in networks at all levels, from the transcontinental backbone to the desktop. Examples of devices include a subpicosecond clock source packaged inside a laptop personal computer and an OTDM switch on a single semiconductor chip, both produced at HHI. Advances similar to these make it possible now to envisage the use of OTDM techniques, not just in the highest layers of national and international networks, but also much closer to the user-such as the world-first demonstrations at BT Laboratories of a 40 Gb/s TDMA LAN and a 100 Gb/s packet self-routing switch for multiprocessor interconnection. Ultrafast networks might even provide the interconnection backplane inside future desktop routers and servers with massive throughput     

Description and evaluation of the FAST-Net smart pixel-basedoptical interconnection prototype

The design, packaging approach, and experimental evaluation of the free-space accelerator for switching terabit networks (FAST-Net) smart-pixel-based optical interconnection prototype are described. FAST-Net is a high-throughput data-switching concept that uses a reflective optical system to globally interconnect a multichip array of smart pixel devices. The three-dimensional optical system links each chip directly to every other with a dedicated bidirectional parallel data path. in the experiments, several prototype smart-pixel devices were packaged on a common multichip module (MCM) with interchip registration accuracies of 5-10 μm. The smart-pixel arrays (SPAs) consist of clusters of oxide-confined vertical-cavity surface-emitting lasers and photodetectors that are solder bump-bonded to Si integrated circuits. The optoelectronic elements are arranged within each cluster on a checkerboard pattern with 125-μm pitch. The experimental global optical interconnection module consists of a mirror and lens array that are precisely aligned to achieve the required interchip parallel connections between up to 16 SPAs. Five prototype SPAs were placed on the MCM to allow the evaluation of a variety of interchip links. Measurements verified the global link pattern across several devices on the MCM with high optical resolution and registration. No crosstalk between adjacent channels was observed after alignment. The I/O density and efficiency results suggest that a multi-terabit switch module that incorporates global optical interconnection to overcome conventional interconnection bottlenecks is feasible     

硅基光开关及阵列研究进展北大核心

随着网络传输数据的爆炸式增长,传统集成电路芯片面临着难以进一步提升交换速率及继续扩大容量等挑战。相较于传统电子芯片,硅基光子器件具有交换速度快、功耗低、带宽大和与CMOS工艺兼容性好等优点,可满足下一代全光交换网络、数据中心和高性能计算光互连的迫切需求,被视为在后摩尔时代突破芯片容量最具前途的解决方案,受到日益广泛关注。文章介绍了硅基光子芯片中光开关单元及阵列的技术原理和发展现状,重点论述了MZI型、MRR型开关单元,以及常见阵列拓扑结构,介绍了近年来大规模光开关阵列的国内外研究进展,讨论了未来硅基光开关及阵列研究中面临的主要问题和解决方法。     

Experiment on deflector-selector optical switch matrix

An electro-optic switch matrix composed of planar waveguide (free-space) interconnection and deflectors is proposed. The architecture offers one solution for the interconnection problem imposed on an optical switch matrix.<>     

SLOB: a switch with large optical buffers for packet switching

Recently, optical packet switch architectures, composed of devices such as optical switches, fiber delay lines, and passive couplers, have been proposed to overcome the electromagnetic interference (EMI), pinout and interconnection problems that would be encountered in future large electronic switch cores. However, attaining the buffer size (buffer depth) in optical packet switches required in practice is a major problem; in this paper, a new solution is presented. An architectural concept is discussed and justified mathematically that relies on cascading many small switches to form a bigger switch with a larger buffer depth. The number of cascaded switches is proportional to the logarithm of the buffer depth, providing an economical and feasible hardware solution. Packet loss performance, control and buffer dimensioning are considered. The optical performance is also modeled, demonstrating the feasibility of buffer depths of several thousand, as required for bursty traffic     

Modeling of optical devices for the design of multistage interconnection network systems

Guidelines of the modeling of an all-optical architecture is presented. This basic architecture is universal and flexible. It can be used as the switching building block for a number of interconnection networks. The power analysis of an all optical buffering architecture [1] that can be interfaced with such an element is discussed. The modeling analysis is given in terms of the switch model, the multistage model and the power analysis of the optical buffer. The architecture uses bistable optical devices such as Fabry-Perot etalons, SEED and S-SEED. A number of important issues remain to be addressed, such as the use of different nonlinear optical devices, synchronization, and simulation.