A low-power charge-recycling ROM architecture

This paper describes a newly proposed low-power charge-recycling read-only memory (CR-ROM) architecture. The CR-ROM reduces the power consumption in bit lines, word lines, and precharge lines by recycling the previously used charge. In the proposed CR-ROM, bit-line swing voltage is lowered by the charge recycling between bit lines. When N bit lines recycle their charges, the swing voltage and the power of the bit lines become 1/N and 1/N/sup 2/ compared to the conventional ROMs, respectively. As the number of N increases, the power saving in bit lines becomes salient. Also, power consumption in word lines and precharge lines can be reduced theoretically to half by the proposed charge-recycling techniques. The simulation results show that the CR-ROM consumes 60%/spl sim/85% of the conventional low-power ROMs with 1 K /spl times/ 32 b. A CR-ROM with 32 Kb was implemented in a 0.35-/spl mu/m CMOS process. The power dissipation is 6.60 mW at 100 MHz with 3.3 V and the maximum operating clock frequency is 150 MHz.     

Novel circuits for high speed ROMs

Novel approaches in circuit design, such as overlap timing without precharge, complementary ROM cells with two access lines, and overall chain-delay optimization, greatly increase the operational speed of ROMs. The innovative circuits fabricated with an advanced CMOS/SOS process resulted in an experimental 18-kbit (2K/spl times/9) look-up ROM performing a cycle time of 4 ns, a silicon area of 7.2 kmil/SUP 2/ and a radiation hardness of >10/SUP 5/ rad(Si). The overlap timing can multiply the address and data change rate without reducing the overall chain delay. The utilization of complementary ROM cells increases data processing speed, noise margin, and radiation hardness. The overall chain delay is greatly reduced by finding the minimum of a device size dependent time function. The complementary cell features a size of 12/spl times/17.2 /spl mu/m, shared contacts, and tantalum polycide access lines. The circuits discussed here can be used for any high-speed memory design, although the demonstration vehicle is a CMOS/SOS ROM.     

The design and performance of CMOS 256K bit DRAM devices

The design and performance of CMOS 256K bit dynamic random access memory devices with 256K/spl times/1 and 64K/spl times/4 output configurations are presented. An advanced CMOS technology, with device scaling to the HMOS-III level, is used to provide effective solutions to critical device and circuit problems in DRAM design and to offer features not previously implemented in NMOS designs. The cell and die area are 70 /spl mu/m/SUP 2/ and 253 mil /spl square/ (6.3 mm /spl square/), respectively. The typical row access time is less than 100 ns. The p-channel memory array used in this design improves the memory refresh characteristics and reduces the soft error rates. The use of static and clocked CMOS circuits provides lower active power, wide operating margins, microwatt standby power, and high column data bandwidth. The 256K bit devices are designed with two output modes, namely, ripplemode and static column mode, selected by a metal mask option.     

A 25-ns 1-Mbit CMOS SRAM with loading-free bit lines

A 128 K/spl times/8-b CMOS SRAM is described which achieves a 25-ns access time, less than 40-mA active current at 10 MHz, and 2-/spl mu/A standby current. The novel bit-line circuitry (loading-free bit line), using two kinds of NMOSFETs with different threshold voltages, improves bit-line signal speed and integrity. The two-stage local amplification technique minimizes the data-line delay. The dynamic double-word-line scheme (DDWL) allows the cell array to be divided into 32 sections along the word-line direction without a huge increase in chip area. This allows the DDWL scheme to reduce the core-area delay time and operating power to about half that of other conventional structures. A double-metal 0.8-/spl mu/m twin-tub CMOS technology has been developed to realize the 5.6/spl times/9.5-/spl mu//SUP 2/ cell size and the 6.86/spl times/15.37-mm/SUP 2/ chip size.     

Injection-coupled memory: A high-density static bipolar memory

The design of a new static bipolar memory comparable with dynamic FET storages in density, but superior in performance and power dissipation is discussed. The concept of direct minority carrier injection is utilized for both the cell current supply and the coupling to the read/write lines. This has led to an extremely high degree of device integration resulting in a cell size of 3.1 mil/SUP 2/ using a standard buried layer process with 5-/spl mu/ line dimensions and single layer metallization. Investigations on exploratory chips containing small arrays have fully verified the feasibility. The cells have been operated at an extremely small d.c. standby power of below 100 nW. For a 4K b chip of about 160/spl times/150 mil/SUP 2/, an access time around 50 ns can be projected from the measurements simulating a 64/spl times/64 bit array. An extrapolation of the memory cell layout with oxide isolation and self-aligned N/SUP +/ contacts has resulted in a 1.1-mil/SUP 2/ cell with 5-/spl mu/ line dimensions.     

High-voltage regulation and process considerations for high-density 5 V-only E/SUP 2/PROM's

A high density 5-V-only HMOS 1 FLOTOX E/SUP 2/PROM technology has been developed using stepper lithography and dry etching techniques. A 1.5-/spl mu/m minimum feature size and 0.5-/spl mu/m registration result in a FLOTOX cell with an area of 270 /spl mu/m/SUP 2/. This represents a 50% reduction of the original cell size. Equivalent endurance (10K cycles) and data retention (10 years) have been obtained. Improved critical dimension control has increased the uniformity of the new cell within the array. Junction leakage has been reduced by using an extended low-temperature anneal cycle. Circuit techniques have been developed to ensure full temperature range (-55-125/spl deg/C) operation. A capacitive voltage divider in a feedback loop, an E/SUP 2/ trimmable voltage reference, and a switched-capacitor RC network are employed to produce a temperature-stable programming pulse with a rising edge time constant of ~ 600 /spl mu/s. The programming voltage can be trimmed with an accuracy of /spl plusmn/ 0.5 V over a typical range of 19-24 V in order to match the requirements of the array. 16K and 64K 5-V-only E/SUP 2/PROMs with die sizes of 128 /spl times/ 182 mil and 223 X 278 mil have been fabricated.     

An 80 ns 1 Mbit MASK ROM with a new memory cell

A high-speed 1-Mb MASK ROM incorporating a new through-hole programmed memory cell, named THOLE CELL, and a full CMOS static sense amplifier is described. The ROM has been fabricated using a double-polysilicon p-well CMOS technology. As a result of achieving a compact ROM cell that is as small as 5.2-/spl times/6.4 /spl mu/m/SUP 2/, even with relatively conservative 2.0 /spl mu/m design rules, a small die size of 7.08/spl times/7.7 mm/SUP 2/ is realized. The ROM organization is 128K/spl times/8 bit and has a typical access time of 80 ns. A typical active current of 8 mA is achieved, in spite of the fully static system. This ROM offers high speed and low power characteristics, while achieving small die size and short turnaround time.     

A CMOS/SOS 4K static RAM

Discusses high density CMOS/SOS technology used to develop a fully static 4096-bit RAM with a five-transistor storage cell. Selection of a five-transistor memory cell has reduced the access to the flip-flop storage element to a single word line transistor and bit line. The word line transistor must be able to prevent data altering currents from entering the memory cell at all times except for the write operation. The write operation is enhanced by reducing the bias voltage across the memory cell, thereby making the current needed to alter the cell smaller. Through the use of a 5 /spl mu/m design rule, the memory cell occupies 2913 /spl mu/m/SUP 2/. The 4096-bit static CMOS/SOS RAM contains 22553 transistors in 20 mm/SUP 2/. Organised as 1024 4-bit words, the RAM has a read cycle time of 350 ns and standby power dissipation of 50 /spl mu/W at V/SUB cc/=5 V and temperature of 27/spl deg/C.     

Two-13 ns-64K CMOS SRAM's with very low active power and improved asynchronous circuit techniques

64K/spl times/1 and 16K/spl times/4 CMOS SRAMs which achieve an access time of 13 ns and less than 12-mA active current at 10 MHz are described. A double-metal 1.5-/spl mu/m p-well process is used. A chip architecture with local amplification improves signal speed and data integrity. Address stability detection techniques are introduced as a method of assuring full asynchronicity over a wide range of conditions. A chip-select speed-up circuit allows high-speed access from a power-down mode. A memory cell design is presented which has improved layout efficiency (area of 189 /spl mu/m/SUP 2/), yet provides a very high cell ratio of 3:1 for signal stability and margin. Experimental results are presented which demonstrate full performance under address skews and other asynchronous input conditions. High-speed enable access and address access are observed over a wide range of operating conditions.     

A precision curvature-compensated CMOS bandgap reference

A precision curvature-compensated switched-capacitor bandgap reference is described which uses a standard digital CMOS process and achieves temperature stability significantly lower than has previously been reported for CMOS circuits. The theoretically achievable temperature coefficient approaches 10 ppm//spl deg/C over the commercial temperature range and uses a straightforward room temperature trim procedure. Experimental data from monolithic prototype samples are presented which are consistent with theoretical predictions. The experimental prototype circuit occupies 3500 mil/SUP 2/ and dissipates 12 mW with /spl plusmn/5 V power supplies. The proposed reference is believed to be suited for use in monolithic data acquisition systems with resolutions of 10 to 12 bits.     

16K CMOS/SOS asynchronous static RAM

A new CMOS/SOS `buried-contact' process allows fabrication of dense static memory cells. The technology is applied in a 16K RAM with 1150 /spl mu/m/SUP 2/ (1.78 mil/SUP 2/) cells based on 5 /spl mu/m design rules.     

A 4-Mbit DRAM with half-internal-voltage bit-line precharge

A single 5-V supply 4-Mb dynamic random access memory (DRAM) was developed by using a buried-storage-electrode memory cell, a half-internal-voltage bit-line precharge method combined with a constant voltage converter, and a high signal-to-noise ratio sensing scheme. The chip was designed in a double-polycide, single-Al, epitaxial substrate NMOS technology with a 0.8-/spl mu/m minimum design rule. As a result, a 4M word/spl times/1-bit DRAM with 95-ns typical access time and 99.2-mm/SUP 2/ chip area was attained by 10.58-/spl mu/m/SUP 2/ storage cells.     

A fault-tolerant 30 ns/375 mW 16K/spl times/1 NMOS static RAM

A fault-tolerant 30950 mil/SUP 2/ (19.9 mm/SUP 2/) 16K/spl times/1 static MOS RAM has been fabricated with a single polysilicon E/D NMOS process. Using circuit techniques normally restricted to dynamic RAMs, but adapted for asynchronous operation, the device achieves a typical access time of 30 ns while dissipating only 375 mW. Among the topics discussed in a new single-polysilicon memory cell configuration, the first truly asynchronous bootstrap circuit, an active bit-line equilibration and precharge scheme, and a new power-efficient substrate bias generator. Also described is an on-chip redundancy scheme which consumes approximately 2 percent of the total chip area, does not compromise access time and can be programmed using standard test equipment.     

A 1-Mbit CMOS DRAM with fast page mode and static column mode

A 1-Mb words/spl times/1-bit CMOS dynamic RAM fabricated with an advanced n-well CMOS technology is described. More than 2.2 million devices are integrated on a 62.5 mm/SUP 2/ silicon chip by utilizing an n-channel memory cell of triple-level poly Si structure and a 1.2-/spl mu/m feature size VLSI process. Novel CMOS circuit design techniques such as the half V/SUB cc/ bitline precharge scheme are successfully applied to realize the excellent performance combination of high-speed operation and low-power dissipation. The CMOS peripheral circuitry is capable of the new operating functions, fast page mode, or static column mode with metal mask options. The typical RAS access time is 56 ns, the active current is 30 mA at a 190-ns cycle time, and the standby current is 0.2 mA.     

A DOL CMOS static memory cell

A new CMOS static memory cell, called the double-lambda diode (DOL), is described. It offers the speed and the power dissipation advantages of conventional CMOS static memory cells at half the area. The cell uses complementary depletion MOS devices. The processing technology is based on a twin-tub CMOS process. Using 2.5 /spl mu/m design rules the cell area is 500 /spl mu/m/SUP 2/. In addition, a 300 /spl mu/m/SUP 2/ single-lambda diode (SIL) cell using a poly resistor as a load is discussed. Comparisons of these cells with other MOS static memory cells are presented.     

An EEPROM for microprocessors and custom logic

An EEPROM extension to a 2.5-/spl mu/ n-well CMOS technology has been developed. In this technology an EEPROM has been designed that is suitable for integration with (existing) microprocessors in a baseline 5 V technology. A 2K EEPROM memory module, usable as a building block in a cell library for custom logic, measures 3.2 mm/SUP 2/ with a memory cell area of 440 /spl mu/m/SUP 2/.     

A 240K transistor CMOS array with flexible allocation of memory and channels

A CMOS masterslice containing about 240K transistors is described. A new basic cell was designed for efficient construction of both logic and memory cells. For flexible allocation of wiring channels, logic unit cells, and memory blocks, about 30000 basic cells with no dedicated channel regions are spread throughout the chip, except in the I/O region. Logic and memory blocks can be placed anywhere on the chip. A test chip, developed to investigate the feasibility of the masterslice design, reveals densities of 230 gates/mm/SUP 2/, 230 bit/mm/SUP 2/, and 1900 bit/mm/SUP 2/ for a 16/spl times/16-bit multiplier, a 1K SRAM, and a 4K ROM, respectively.     

A 70 ns high density 64K CMOS dynamic RAM

A 64K /spl times/ 1 CMOS dynamic RAM has been developed in a double-poly n-well CMOS technology with device scaling to the HMOS III level. A p-channel memory array with n-well protection reduced the operating soft error rate to less than one FIT. Periphery complexity is simplified due to CMOS circuits resulting in a size of 30,464 mil/SUP 2/ with a redundancy efficiency of 68%. The RAM has a typical access time of 70 ns and a CMOS standby power of 25 /spl mu/W. In addition, a static column design offers 35-ns data cycle time for high-bandwidth application.     

HMOS-CMOS-a low-power high-performance technology

HMOS-CMOS, a new high-performance bulk CMOS technology, is described. This technology builds on HMOS II, and features high resistivity p-substrate, diffused n-well and scaled n- and p-channel devices of 2-/spl mu/m channel length and 400-/spl Aring/ gate oxide thickness. The aggressive scaling of n and p devices results in 350-ps minimum gate delay and 0.04-pJ power delay product. HMOS-CMOS is a single poly technology suitable for microprocessor and static RAM applications. A 4K static RAM test vehicle is described featuring fully CMOS six-transistor memory cell, a chip size of 19600 mil/SUP 2/, 75 /spl mu/W standby power, data retention down to a V/SUB cc/ voltage of 1.5 V and a minimum chip select and address access time of 25 ns.