A 2 Gb/s Bi-Directional Inter-Chip Data Transceiver With Differential Inductors for High Density Inductive Channel Array

A 2 Gb/s bi-directional inter-chip data transceiver is experimentally demonstrated for the first time in 180 nm CMOS technology. Two orthogonal differential inductor pairs are vertically overlapped to make a bi-directional channel. Using these channels, bi-directional communication system is established without any complex circuit techniques. The crosstalk interference problem in channel array is also considered. Differential inductors, due to their noise immunity can make shorter pitches possible in channel array. Compared with the data link with conventional inductor array, this proposed technique achieves 64% area reduction with the same speed.      

Three-dimensional substrate impedance engineering based on p/sup -//p/sup +/ Si substrate for mixed-signal system-on-chip (SoC)

A novel approach for three-dimensional substrate impedance engineering of p/sup -//p/sup +/ Si substrate is described for mixed-signal integrated circuit applications. This technology requires minimum intrusion to conventional Si CMOS processing, but offers astounding improvements with regard to radio frequency (RF) crosstalk via substrate and on-chip inductor performance. Electroless plating or electro-plating is used to fabricate Faraday cage for crosstalk isolation as well as to provide "true ground" contacts. A self-limiting porous Si (PS) formation process is employed to allow the insertion of PS regions from the backside of the wafer, eliminating completely the waste of chip surface area. On-chip inductors are situated above the semi-insulating PS regions allowing for greatly increased Q-factor and resonance frequency (f/sub r/). RF crosstalk is reduced to the level limited by that across the air gap between the measurement probes.     

超深亚微米高速互连的信号串扰研究

探讨了超深亚微米设计中的高速互连线串扰产生机制,提出了一种描述高速互连串扰的电容、电感耦合模型,通过频域变换方法对模型的有效性进行了理论分析。针对0.18μm工艺条件提出了该模型的测试结构,进行了流片和测量。实测结果表明,该模型能够较好地表征超深亚微米电路的高速互连串扰效应,能够定量计算片上互连线间的耦合串扰,给出不同工艺的互连线长度的优化值。     

Design of low distortion active inductor and its applications

This paper proposes a novel distortion reduction technique for active inductors. A bias current of a MOSFET, which acts as transconductor in an active inductor, is controlled to reduce a distortion of a active inductor. When an input voltage increases, the bias current is decreased by a control circuit. As a result of this control, transconductance of the MOSFET remains constant. An active inductor using this technique is free from distortion caused by a transconductance variation of a MOSFET. The proposed technique is applied to two different conventional active inductors and novel low distortion active inductors are derived. Computer simulations show that distortion of the proposed active inductor is very low. The proposed low distortion active inductors are applied to a second order bandpass filter and a voltage controlled oscillator. Thanks to the proposed technique, distortion of these circuits are reduced and their performance is improved.     

Design and testing of a power electronic synthetic inductor

In many applications inductors are often replaced with circuits, typically based upon operational amplifiers, which emulate an inductance for reasons of package size or to closer approximate the desired ideal behaviour. A power electronic synthetic inductor offers an alternative circuit which can emulate an inductor with relatively low power consumption, as well as provide a flexible circuit topology that is not limited to inductive behaviour. In this article, a power electronic synthetic inductor topology and control system is developed. A prototype synthetic inductor was built and tested, and its operation was explored and compared with an operational-amplifier-based synthetic inductor. A minor modification of the circuit allows the emulation of a negative resistance in parallel with the synthesised inductor, which can increase the quality factor of the system beyond that associated with an ideal inductor. Experimental results reveal that the power electronic synthetic inductor has significantly lower power consumption than an operational-amplifier-based synthetic inductor.     

Micromachined high-Q inductors in a 0.18-μm copper interconnectlow-k dielectric CMOS process

On-chip spiral micromachined inductors fabricated in a 0.18-μm digital CMOS process with 6-level copper interconnect and low-K dielectric are described. A post-CMOS maskless micromachining process compatible with the CMOS materials and design rules has been developed to create inductors suspended above the substrate with the inter-turn dielectric removed. Such inductors have higher quality factors as substrate losses are eliminated by silicon removal and increased self-resonant frequency due to reduction of inter-turn and substrate parasitic capacitances. Quality factors up to 12 were obtained for a 3.2-nH micromachined inductor at 7.5 GHz. Improvements of up to 180% in maximum quality factor, along with 40%-70% increase in self-resonant frequency were seen over conventional inductors. The effects of micromachining on inductor performance was modeled using a physics-based model with predictive capability. The model was verified by measurements at various stages of the post-CMOS processing. Micromachined inductor quality factor is limited by series resistance up to a predicted metal thickness of between 6-10 μm     

A Noise Reduction and Linearity Improvement Technique for a Differential Cascode LNA

A typical common source cascode low-noise amplifier (CS-LNA) can be treated as a CS-CG two stage amplifier. In the published literature, an inductor is added at the drain of the main transistor to reduce the noise contribution of the cascode transistors. In this work, an inductor connected at the gate of the cascode transistor and capacitive cross-coupling are strategically combined to reduce the noise and the nonlinearity influences of the cascode transistors in a differential cascode CS-LNA. It uses a smaller noise reduction inductor compared with the conventional inductor based technique. It can reduce the noise, improve the linearity and also increase the voltage gain of the LNA. The proposed technique is theoretically formulated. Furthermore, as a proof of concept, a 2.2 GHz inductively degenerated CS-LNA was fabricated using TSMC 0.35 mum CMOS technology. The resulting LNA achieves 1.92 dB noise figure, 8.4 dB power gain, better than 13 dB S11, more than 30 dB isolation (S12), and -2.55 dBm IIP3, with the core fully differential LNA consuming 9 mA from a 1.8 V power supply.     

Current control technique for improving EMC in power converters

A chaotically modulated OFF-time current mode control for DC-DC converters which spreads the inductor current spectrum is presented. Comparison with other methods proposed in the literature shows that this new technique is more suitable for reduction of inductor current spikes and therefore improves electromagnetic compatibility     

Asymmetrically coupled silicon-on-insulator microring resonators for compact add-drop multiplexers

We report on improved filter characteristics of microring resonators (MRs) used as add-drop multiplexers for integrated photonic circuits. By introducing an asymmetrical coupling of the signal waveguides to the resonator, a higher throughput attenuation and drop efficiency is attained. The throughput attenuation is the decisive property for the application of microrings in photonic networks since it determines the crosstalk between drop signal and add signal at the throughput channel of an add-drop multiplexer. Experimental results are compared with analytical relations. MRs with a free-spectral range of 24 nm are fabricated on silicon-on-insulator substrates. A crosstalk reduction by 8.8 dB due to asymmetrical coupling is demonstrated.     

A New On-Chip Substrate-Coupled Inductor Model Implemented With Scalable Expressions

Accurate modeling of the on-chip inductor is essential for the design of high-speed, low-power, and low-noise radio-frequency integrated circuits. The conventional model has a measurable discrepancy as the current flowing in the substrate is not correctly considered. The substrate-coupled inductor model, however, considers the losses generated in both the vertical and horizontal directions. This model gives an intelligent explanation of the reduction in equivalent resistance between terminals with increasing frequency as well as the inductance and quality factor (Q-factor). In order to implement a fully scalable model, the circuit elements in the substrate-coupled inductor model are expressed as monomial equations in terms of physical geometry. These equations consider the physical implications of the parameters as well as employing a mathematical fit for extrapolation. Measurements are made on inductors fabricated using a standard 0.35-mum CMOS process and a 0.15-mum silicon-on-insulator CMOS process to successfully verify this model     

Far-end crosstalk reduction in double-layered dielectricinterconnects

The problem of far-end crosstalk reduction is considered. Various cases of far-end crosstalk reduction in single and cascaded sections of two coupled interconnects in a double-layered dielectric environment are investigated by computer modeling of capacitive and inductive couplings and by simulation of far-end crosstalk waveforms     

Clear as a bell [controlling crosstalk in uniform interconnections]

Designers are aware of several approaches to reduce crosstalk, such as the use of shields or differential links that require a particular structure for the interconnection. This article discusses known crosstalk mitigation methods and presents a different technique applicable in various situations, which provides a drastic reduction of crosstalk     

Crosstalk and Wire Length Reduction in the Non-Manhattan Channel Routing

With the recent advances in VLSI fabrication technology, the device sizes have shrunk blow 0.1 μm. Due to the scaling down of device geometry in deep-submicron technologies, the crosstalk between adjacent nets has become a major concern in high performance VLSI circuit design. Increased crosstalk can cause signal delays, logic hazards, and even malfunctioning of circuits, and thus controlling the level of crosstalk in a chip has become an important task for IC designers. It’s well known …     

Crosstalk-aware multi-bit flip-flop generation for power optimization

Applying multi-bit flip-flops (MBFFs) for clock power reduction in modern nanometer ICs has been becoming a promising lower-power design technique. Many previous works tried to utilize as more MBFFs with larger number of bits as possible to gain more clock power saving. However, an MBFF with larger number of bits may lead to serious crosstalk due to the close interconnecting wires belonging to different signal nets which are connected to the same MBFF. This paper analyzes, evaluates, and compares the relationship between power consumption and crosstalk when applying MBFFs with different numbers of bits. To solve the addressed problem, a novel crosstalk-aware power optimization approach is further proposed to optimize power consumption while satisfying the crosstalk constraint. Experimental results show that the proposed approach is very effective in crosstalk avoidance when applying MBFFs for power optimization.     

基于信道传输矩阵逆矩阵减小微带线间串扰

针对现有串扰减小方法效果有限、成本高、资源消耗多等问题,提出了一种基于信道传输矩阵逆矩阵减小微带线间串扰的方法。该方法通过将信道传输矩阵化为单位阵来实现串扰减小。根据理论分析设计了该方法的电路结构。仿真结果表明,使用该方法进行串扰抵消后串扰幅度和抖动都有明显改善,且该方法的电路结构简单。     

A 200-Mbps 0.02-nJ/b Dual-Mode Inductive Coupling Transceiver for cm-Range Multimedia Application

A 200-Mbps 0.02-nJ/b dual-mode inductive coupling transceiver is proposed for cm-range multimedia application. The inductive link geometry and the advantage of the pulse-based inductive coupling are explained. In this paper, the parallel capacitor connected with the TX inductor, the intersymbol interference (ISI) reduction scheme, and the pulse generation scheme are newly proposed. The parallel capacitor connected with the TX inductor increases the transmitter impedance so that it enhances the transmission distance by twofold, and the ISI reduction scheme pushes data rate up to 200 Mbps. Moreover, the pulse generation scheme reduces the energy consumption as low as 0.02 nJ/b. Maximum data rate and energy consumption are achieved in simulation. The transceiver occupies $0.012~{hbox {mm}}^{2}$ in 0.25-$mu{hbox {m}}$ CMOS process.      

Crosstalk reduction in mixed-signal 3-D integrated circuits with interdevice layer ground planes

We show nearly 8 dB of crosstalk reduction using ground planes between active device layers in three-dimensional (3-D) integrated circuits. Our experimental work utilizes two planes of MOS transistors with tungsten or polysilicon ground planes designed to attenuate crosstalk. Theoretical simulations, using an electromagnetic solver, and the experimental results are consistent with analytical results. The key result verified is that a ground plane, whose footprint shadows the device area, is sufficiently large for effective attenuation. The interdevice layer ground plane provides an effective means to achieve crosstalk reduction in 3-D mixed-signal/RF integration because of simple fabrication and high coupling isolation.     

Design and Fabrication of 1.25-Gb/s Full-Triplex Transceiver Module With PLC on a Lossy Si Substrate for G/E-PONs

1.25 Gb/s optoelectronic full-triplex transceiver module with planar-lightwave-circuits was designed and fabricated for the fiber-to-the-home services according to G/E-PONs standards. A low electrical crosstalk of the critical characteristics for the reliable operation of the 1.25 Gb/s full-triplex transceiver module is intensively investigated because the electrical crosstalk on a resistive silicon substrate is more serious than that on a dielectric substrate. It is observed that the performances of the transmitter and receiver satisfy the transmitter and receiver specifications defined in the standards. From this proposed module layout, a design convenience as well as a great reduction of the silicon substrate size by about 50% was completely achieved. Consequently, the 1.25 Gb/s full-triplex transceiver module was fabricated with electrical and mechanical packaging technologies such of a low crosstalk design and a passive alignment method.     

The influence of aperture size and shape on crosstalk level in free-space grating demultiplexers for WDM networks

A simple method is presented to calculate crosstalk caused by aberrations and diffraction at the aperture edges in free-space grating demultiplexers for wavelength-division multiplexed (WDM) communication systems. The influence of circular and square aperture sizes is described for ideal and aberrated optical systems. It is shown that aperture enlargement is not critical to aberrations whilst providing significant crosstalk reduction. The minimum crosstalk value is obtained when the dispersion plane is parallel to the diagonal of the square aperture. -60 dB crosstalk is attainable for moderately aberrated systems with 80 channels (0.5 nm spacing) in the range 1530-1570 nm.     

A 3$,times,$5-Gb/s Multilane Low-Power 0.18-$mu{hbox {m}}$ CMOS Pseudorandom Bit Sequence Generator

A low-power, three-lane, pseudorandom bit sequence (PRBS) generator has been fabricated in a 0.18-mum CMOS process to test a multilane multi-Gb/s transmitter that cancels far-end crosstalk. Although the proposed PRBS generator was designed to produce three uncorrelated 12-Gb/s PRBS sequences, measurement results included in this paper have been obtained at only 5 Gb/s due to test setup limitations. The prototype employs a CMOS latch optimized to operate at frequencies close to the of the process and a current-mode logic (CML) MUX with modified active inductor loads for better high-speed large-signal behavior. In order to reduce the power consumption, a quarter-clock rate linear feedback shift register (LFSR) core in a power-efficient parallel architecture has been implemented to minimize the use of power-hungry, high-speed circuitry. Further power reduction has been achieved through the clever partitioning of the system into static logic and CML. In addition, the prototype design produces three uncorrelated 12-Gb/s data streams from a single quarter-rate LFSR core, thereby amortizing the power across multiple channels which lowers the power per channel by 3 times. The total measured power consumption at 5 Gb/s is 131 mW per lane and the calculated figure of merit per lane is 0.84 pJ/bit, which is significantly better than previously published designs.