共查询到20条相似文献,搜索用时 31 毫秒
1.
《Electron Devices, IEEE Transactions on》1987,34(7):1470-1481
The orientation dependence of the threshold voltage and device transconductance of ion-implanted GaAs FET's has been investigated and modeled. The threshold voltages of the devices along the [011] and [01bar{1} ] directions are different when the gate length is short (≤ 3 µm). Experimental results and theoretical calculations show that this is primarily due to the strain in the active channel, induced by the dielectric overlayer. For the short self-aligned gate structure, the lateral spread of the ion-implanted n+layer is important as well. When these two effects are taken into account, calculated results agree well with the experimental data for standard self-aligned gate structures, and self-aligned structures with a sidewall or T-gate, fabricated using lamp- or furnace-annealing processes. This model also allows us to simulate the threshold voltage and transconductance dependence on the annealing time for different device parameters (such as gate length and channel doping)and process variables (i.e., sidewall or T-gate dimensions and impurity diffusion constant). We also calculated the gate length dependence of the transconductance for devices fabricated using a sidewall process. Results of this calculation are compared with the experimental data for different sidewall thicknesses. 相似文献
2.
Sang Lam Hui Wan Pin Su Wyatt P.W. Chen C.L. Niknejad A.M. Chenming Hu Ko P.K. Chan M. 《Electron Device Letters, IEEE》2003,24(4):251-253
The metal T-gate structure in fully-depleted (FD) silicon-on-insulator (SOI) MOSFET's is investigated from the RF perspective. With the expected low gate resistance R/sub G/, the metal T-gate FD-SOI MOSFET achieves a higher f/sub max/ of 67 GHz as compared with 12.5 GHz in the silicided polysilicon gate counterpart. However, the metal T-gate FD-SOI MOSFET has a lower f/sub T/ of 35 GHz as compared with 44 GHz for the self-aligned polysilicon gate. The extracted parameters reveal that the T-gate structure results in an extra 40% and 80% increase in the parasitic capacitances C/sub gs/ and C/sub gd/ respectively. The metal gate structure together with the source-drain structure have to be co-optimized to boost the RF performance of FD-SOI MOSFET. A simple guideline to optimize the structure is included. 相似文献
3.
Improvements in the microwave performance and noise performance of buried p-layer self-aligned gate (BP-SAINT) FETs are discussed. Specifically, a self-aligned gate electrode and an asymmetric n+ -layer structure are investigated. The self-aligned gate electrode reduces parasitic gate capacitances by 0.13 to 0.23 pF/mm compared with a conventional BP-SAINT FET. The asymmetric n+-layer structure reduces short-channel effects (drain conductance, threshold voltage shift, etc.) and gate-drain capacitance. A 0.3-μm gate-length FET was realized without an increase of short-channel effects by using an asymmetric n+-layer structure (advanced SAINT). Improvement of microwave performance is confirmed in this FET structure 相似文献
4.
5.
Thelander C. FrobergFroberg L.E. Rehnstedt C. Samuelson L. Wernersson L.-E. 《Electron Device Letters, IEEE》2008,29(3):206-208
We present results on fabrication and dc characterization of vertical InAs nanowire wrap-gate field-effect transistor arrays with a gate length of 50 nm. The wrap gate is defined by evaporation of 50-nm Cr onto a 10-nm-thick HfO2 gate dielectric, where the gate is also separated from the source contact with a 100-nm SiOx, spacer layer. For a drain voltage of 0.5 V, we observe a normalized transconductance of 0.5 S/mm, a subthreshold slope around 90 mV/dec, and a threshold voltage just above 0 V. The highest observed normalized on current is 0.2 A/mm, with an off current of 0.2 mA/mm. These devices show a considerable improvement compared to previously reported vertical InAs devices with SiNx, gate dielectrics. 相似文献
6.
Wiring Effect Optimization in 65-nm Low-Power NMOS 总被引:1,自引:0,他引:1
《Electron Device Letters, IEEE》2008,29(11):1245-1248
7.
Dong Xu Kong W.M.T. Xiaoping Yang Smith P.M. Dugas D. Chao P.C. Cueva G. Mohnkern L. Seekell P. Pleasant L.Mt. Schmanski B. Duh K.H.G. Karimy H. Immorlica A. Komiak J.J. 《Electron Device Letters, IEEE》2008,29(1):4-7
We report the design, fabrication and characterization of ultrahigh gain metamorphic high electron-mobility transistors. In this letter, a high-yield 50-nm T-gate process was successfully developed and applied to epitaxial layers containing high indium mole fraction InGaAs channels grown on GaAs substrates. A unique gate recess process was adopted to significantly increase device gain by effectively suppressing output conductance and feedback capacitance. Coupled with extremely small 10 mum times 25 mum via holes on substrates thinned to 1 mil, we achieved a 13.5 dB maximum stable gain (MSG) at 110 GHz for a 30-mum gate-width device. To our knowledge, this is the highest gain performance reported for microwave high electron-mobility transistor devices of similar gate periphery at this frequency, and equivalent circuit modeling indicates that this device will operate at frequencies beyond 300 GHz. 相似文献
8.
We proposed a new bulk FinFET that has a p+/n+ poly-Si gate consists of p+ region near the source and n+ region near the drain and analyzed current-voltage characteristics and electric field profiles of 50-nm devices by changing the n+ poly-Si gate length (Ls). For given gate length (Lgles50 nm) and fin body width (Wfinles30 nm), Ls was designed to satisfy the I off requirement (i.e., 1 fA) of DRAM cell. Optimum Ls /Lg of 30-nm device was ~0.4 at a Wfin of 10 nm and ~0.2 at a Wfin of 15 nm 相似文献
9.
Kadow C. Dahlstrom M. Bae J.-U. Lin H.-K. Gossard A.C. Rodwell M.J.W. Brar B. Sullivan G.J. Nagy G. Bergman J.I. 《Electron Devices, IEEE Transactions on》2005,52(2):151-158
We report a submicrometer, self-aligned recess gate technology for millimeter-wave InAs-channel heterostructure field effect transistors. The recess gate structure is obtained in an n/sup +/-InAs-InAlAs double cap layer structure with a citric-acid-based etchant. From molecular-beam epitaxy-grown material functional devices with 1000-, 500-, and 200-nm gate length were fabricated. From all three device geometries we obtain drive currents of at least 500 mA/mm, gate leakage currents below 2 mA/mm, and RF-transconductance of 1 S/mm. For the 200-nm gate length device f/sub /spl tau// and f/sub max/ are 162 and 137 GHz, respectively. For the 500-nm gate length device f/sub /spl tau// and f/sub max/ are 89 and 140 GHz, respectively. We observe scaling limitations at 200-nm gate length, in particular a negative threshold voltage shift from -550 to -810 mV, increased kink-effect, and a high gate-to-drain capacitance of 0.5 pF/mm. The present limitations to device scaling are discussed. 相似文献
10.
This paper reports on self-aligned T-gate InGaP/GaAs FETs using n +/N+/δ(P+)/n structures. N+ -InGaP/δ(P+)-InGaP/n-GaAs forms a planar-doped barrier. The inherent ohmic gate of camel-gate FETs together with a highly selective etch between an InGaP and a GaAs layers offers a self-aligned T-shape gate with a reduced effective length. A fabricated device with a reduced gate dimension of 1.5×100 (0.6×100) μm2 obtained from 2×100 (1×100) μm2 gate metal exhibits an extrinsic transconductance, unity-current gain frequency, and unity-power gain frequency of 78 (80) mS/mm, 9 (19.5), and 28 (30) GHz, respectively 相似文献
11.
Sub-50 nm P-channel FinFET 总被引:6,自引:0,他引:6
Xuejue Huang Wen-Chin Lee Kuo C. Hisamoto D. Leland Chang Kedzierski J. Anderson E. Takeuchi H. Yang-Kyu Choi Asano K. Subramanian V. Tsu-Jae King Bokor J. Chenming Hu 《Electron Devices, IEEE Transactions on》2001,48(5):880-886
High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) regions; 3) raised S/D regions; and 4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of fabrication. The 45-nm gate-length p-channel FinFET showed an Idsat of 820 μA/μm at Vds=Vgs=1.2 V and T ox=2.5 mm. Devices showed good performance down to a gate-length of 18 nm. Excellent short-channel behavior was observed. The fin thickness (corresponding to twice the body thickness) is found to be critical for suppressing the short-channel effects. Simulations indicate that the FinFET structure can work down to 10 nm gate length. Thus, the FinFET is a very promising structure for scaling CMOS beyond 50 nm 相似文献
12.
《Electron Device Letters, IEEE》2009,30(7):748-750
13.
Yo-Sheng Lin Shey-Shi Lu Yo-Jen Wang 《Electron Devices, IEEE Transactions on》1997,44(6):921-929
Ga0.51In0.49P/GaAs MISFET's, in which Ga0.51In0.49P insulating layer was inserted between the gate metal and the channel layer, were compared with MESFET's experimentally and theoretically in terms of DC and microwave performance. Devices performance were evaluated by varying the thickness of the insulating layer. Wide and flat characteristics of gm, gt, and fmax versus drain current (or gate voltage) together with a high maximum current density (above 610 mA/mm) were achieved for devices with insulating layer thickness of 50 mn and 100 mm. Moreover, the maximum values of Jt's and fmax 's for a 1-μm gate length device both occurred when t was between 50 and 100 mn. We also observed that parasitic capacitances and gate leakage currents were minimized by using the airbridge gate structure, and thus high-frequency and breakdown characteristics were greatly improved, These results demonstrate that Ga0.51In0.49P/GaAs airbridge gate MISFET's with insulating layer thickness between 50 and 100 mn were very suitable for microwave high-power device applications 相似文献
14.
《Solid-State Circuits, IEEE Journal of》1982,17(2):226-230
A multiple self-aligned structure that facilitates high packing density and high speed in bipolar VLSI's is proposed. The device has polysilicon sidewall base electrodes to reduce parasitic junction capacitances. The new devices indicate that capacitances between the base and collector regions are reduced to 1/4 and the ratio of reverse-to-forward current gain is increased about 5 times that of conventional bipolar transistor structures, and gate delay in IIL circuits is about 1 ns/gate. The structure opens the way for further scaled-down VLSI. 相似文献
15.
Koga J. Takahashi M. Niiyama H. Iwase M. Fujisaki M. Toriumi A. 《Electron Devices, IEEE Transactions on》1994,41(7):1179-1183
Under cryogenic operation, a low Vth realizes a high speed performance at a greatly reduced power-supply voltage, which is the most attractive feature of Cryo-CMOS. It is very important in sub-0.25 μm Cryo-CMOS devices to reconcile the miniaturization and the low Vth. Double implanted MOSFET's technology was employed to achieve the low Vth while maintaining the short channel effects immunity. We have investigated both the DC characteristics and the speed performance of 0.25 μm gate length CMOS devices for cryogenic operation. The measured transconductances in the saturation region were 600 mS/mm for 0.2 μm gate length n-MOSFET's and 310 mS/mm for 0.25 μm gate length p-MOSFET's at 80 K. The propagation delay time in the fastest CMOS ring oscillator was 22.8 ps at Vdd=1 V at 80 K. The high speed performance at extremely low power-supply voltages has been experimentally demonstrated. The speed analysis suggests that the sub-l0 ps switching of Cryo-CMOS devices will be realized by reducing the parasitic capacitances and through further miniaturization down to 0.1 μm gate length or below 相似文献
16.
Singisetti U. Wistey M.A. Burek G.J. Baraskar A.K. Thibeault B.J. Gossard A.C. Rodwell M.J.W. Byungha Shin Kim E.J. McIntyre P.C. Bo Yu Yu Yuan Wang D. Yuan Taur Asbeck P. Yong-Ju Lee 《Electron Device Letters, IEEE》2009,30(11):1128-1130
Abstract-We report Al2O3Zln0.53Ga0.47As MOSFETs having both self-aligned in situ Mo source/drain ohmic contacts and self-aligned InAs source/drain n+ regions formed by MBE regrowth. The device epitaxial dimensions are small, as is required for 22-nm gate length MOSFETs; a 5-nm In0.53Ga0.47As channel with an In0.4sAl0.52As back confinement layer and the n++ source/drain junctions do not extend below the 5-nm channel. A device with 200-nm gate length showed ID = 0.95 mA/mum current density at VGS = 4.0 V and gm = 0.45 mS/mum peak transconductance at VDS = 2.0 V. 相似文献
17.
《Electron Device Letters, IEEE》2009,30(8):793-795
18.
《Electron Devices, IEEE Transactions on》1982,29(4):596-600
A multiple self-aligned structure that facilitates high packing density and high speed in bipolar VLSI's is proposed. The device has polysilicon sidewall base electrodes to reduce parasitic junction capacitances. The new devices indicate that capacitances between the base and collector regions are reduced to 14 and the ratio of reverse-to-forward current gain is increased about 5 times that of conventional bipolar transistor structures, and gate delay in IIL circuits is about 1 ns/gate. The structure opens the way for further scaled-down VLSI. 相似文献
19.
Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors 总被引:1,自引:0,他引:1
Mohapatra N.R. Desai M.P. Narendra S.G. Ramgopal Rao V. 《Electron Devices, IEEE Transactions on》2003,50(4):959-966
In deep submicrometer MOSFETs the device performance is limited by the parasitic capacitance and resistance. Hence a circuit model is needed to treat these effects correctly. In this work, we have developed circuit models for the parasitic capacitances in conventional and high-K gate dielectric MOS transistors by taking into account the presence of source/drain contact plugs. The accuracy of the model is tested by comparing the modeled results with the results obtained from three-dimensional (3-D) Monte-Carlo simulations and two-dimensional (2-D) device simulations over a wide range of channel length and oxide thickness. The model is also used to study the dependence of parasitic capacitance on gate length, gate electrode thickness, gate oxide thickness, gate dielectric constant, and spacer width. 相似文献
20.
Alatise O.M. Olsen S.H. Cowern N. O'Neill A.G. Majhi P. 《Electron Devices, IEEE Transactions on》2009,56(10):2277-2284
The short-channel performance of compressively strained Si0.77Ge0.23 pMOSFETs with HfSiOx/TiSiN gate stacks has been characterized alongside that of unstrained-Si pMOSFETs. Strained-SiGe devices exhibit 80% mobility enhancement compared with Si control devices at an effective vertical field of 1 MV middotcm-1. For the first time, the on-state drain-current enhancement of intrinsic strained-SiGe devices is shown to be approximately constant with scaling. Intrinsic strained-SiGe devices with 100-nm gate lengths exhibit 75% enhancement in maximum transconductance compared with Si control devices, using only ~20% Ge (~0.8% strain). The origin of the loss in performance enhancement commonly observed in strained-SiGe devices at short gate lengths is examined and found to be dominated by reduced boron diffusivity and increased parasitic series resistance in compressively strained SiGe devices compared with silicon control devices. The effective channel length was extracted from I- V measurements and was found to be 40% smaller in 100-nm silicon control devices than in SiGe devices having the same lithographic gate lengths, which is in good agreement with the metallurgical channel length predicted by TCAD process simulations. Self-heating due to the low thermal conductivity of SiGe is shown to have a negligible effect on the scaled-device performance. These findings demonstrate that the significant on-state performance gains of strained-SiGe pMOSFETs compared with bulk Si devices observed at long channel lengths are also obtainable in scaled devices if dopant diffusion, silicidation, and contact modules can be optimized for SiGe. 相似文献