整数5/3小波变换的VLSI结构设计

在JPEG 2000中,无损图像压缩是采用整数5/3小波变换实现的.JPEG 2000也给出了5/3小波基于提升方法的算法.对提升方法的整数5/3小波变换算法进行了研究,针对二维的变换提出一种VLSI结构.该结构由4个模块构成,模块之间并行运行,模块内部采用流水线技术.对多级变换,级间的运算还可交叉,体现了提升方法的优势,较大地提高了硬件效率.其主要优点是消耗资源少且运算速度高,同时也适用于其他整数小波变换.     

基于FPGA的5/3提升小波优化算法

为了实现线阵CCD空间相机图像的实时压缩处理,在提升算法的基础上,提出了一种适用于FPGA的二维提升小波变换结构与实现方案.该系统利用FPGA片内的存储资源,采用乒乓操作实现了行列变换之间的数据缓存传输,降低了功耗,提高了硬件利用率和运算速度.并且为了适应硬件实现速度,在进行小波边界处理时不需要额外的边界延拓过程,很大程度上降低了算法的复杂度;整个模块采用verilog HDL语言进行设计,并在QuestaSim下进行了仿真试验.实验结果表明,该系统工作稳定可靠,完全满足实时处理的要求,并适用于JPEG2000的多级二维5/3小波变换.     

二维提升小波的VLSI结构设计及FPGA验证

针对JPEG2000中小波变换的硬件实现占用资源量大、速度慢等问题,提出了一种有效的二维小波硬件实现模型。该模型采用流水线并行结构,即对图像中各行像素进行流水线处理的同时,对小波分解的各级采用并行结构处理。这样的结构提高了小波变换的处理速度,实现了实时处理,节省了硬件的片上存储及外部存储资源。用FPGA对此模型进行验证。验证实验采用Xinlinx公司的SPARTEN-3系列芯片,对1 024×2 048的大图像进行处理,图像处理速度达到80Mpixels/s,满足实时性要求。     

JPEG2000小波变换器的VLSI结构设计

新一代静止图像压缩标准JPEG2000将离散小波变换(DWT)作为其核心变换技术,并推荐采用推举体制(lifting)快速算法来实现.空间组合推举体制算法(SCLA)大大降低了lifting的运算量.当选用9/7小波滤波器时,SCLA的乘法运算量只有lifting的7/12.本文提出了一种实现SCLA算法的VLSI结构,降低了基于lifting实现的运算量, 加快了变换的速度,减小了电路的规模.本文的二维正反小波变换器已经作为单独的IP核应用于我们目前正在开发的JPEG2000图像编解码芯片中.     

提升算法离散小波变换的硬件实现

本文介绍一种小波变换提升算法的硬件实现，它可以设置为5／3和9／7小波变换并用于JPEG2000中。该硬件实现采用了折叠结构以达到减少硬件开销和提高硬件使用率的目的。其中的乘法部分采用了正则符号编码（CSD，Canoni Csigned digit）把乘法运算转化为移位加／减操作，加快了变换速度。同时采用了嵌入式延拓进行数据延拓，也达到了加快运算速度和减少存储要求的目的。整个架构采用VHDL实现并通过仿真验证。     

低功耗并行的提升式5/3二维离散小波变换的VLSI架构

离散小波变换需要较大的运算量和运算空间,为了提高JPEG2000图像压缩速度,提出一种基于提升算法的二维离散5/3小波变换的VLSI架构,这种结构同时进行行变换和列变换。文章对于VLSI架构的五大模块(行小波变换运算模块、两个列小波变换模块、FIFO寄存组和系统整体控制模块)的硬件实现给出了相应的方案。在Quartus II 7.2的平台下对于设计的该系统的时序仿真测试结果表明,综合分析后系统最小组合逻辑时延为7.142ns,可达到的最高频率为140.02MHz。时序仿真测试中当系统工作频率为100MHz,数据吞吐率达到773.944Mbit/s。     

小波提升算法及其在图像处理中的应用

小波提升算法是一种新的双正交小波构造方法，通过预测算子，确定高频信息，并初步确定低频信息，然后通过更新算子，对初步确定的低频信息进行修正，从而确定低频信息。它在空域对信号进行变换，完成了对信号频域的分析。在图像处理中，基于离散小波变换的提升算法比传统的卷积算法运算简单，实时性好，易于实现，因而被新一代图像压缩标准JPEG2000所采用。文中简要介绍了小波提升算法的原理，分析了其特点，并介绍了JPEG2000标准中采用的W5／3、D9／7两种小波的提升格式和实现算法。     

基于小波变换的几种图像压缩方法研究

利用小波变换进行图像编码已成为近年来的研究热点.采用不同的小波变换和量化,就形成了不同的压缩方案.本文选用了Daubechies9/7小波和基于提升框架的线性插值小波变换,并基于现在最流行的JPEG2000标准,采用标量量化及嵌入式编码等不同方法,对几种压缩方法的实验效果进行了比较.     

二维9/7小波变换VLSI设计

为了提高JPEG2000图像压缩速度,提出一种基于提升算法的二维离散9/7小波变换(DWT)Mesh结构的VLSI设计方案,利用这种Mesh结构的VLSI能够实现并行处理一个图像的所有像素点.这种并行处理的Mesh结构可提高小波变换电路速度,以及图像压缩的速度.     

5/3小波图像压缩TMS320C6416实现关键技术

对于高分辨率相机所成图像来说，数据量是非常巨大的，光用软件来进行压缩远远不能满足实时性的要求。离散小波变换是当今许多图像处理和压缩技术的基础。JPEG2000是最新的静态图像压缩标准,其核心算法是小波变换。5/3小波提升方法在JPEG2000中主要用于无损图像压缩。本文详细介绍了第二代小波的构造方法—基于因式分解的提升格式,提出对5/3小波的改进，并采用了TMS320C6416实现的了该算法。DSP实验结果证明提升5/3小波变换具有处理速度快、实时性强、压缩比大、恢复效果好的特点。     

Block DCT to wavelet transcoding in transform domain

The Discrete Cosine Transform (DCT) to wavelet transcoding provides input for several wavelet-based post-processing techniques of the DCT-coded image/video signals. Transcoding in domain transform avoids inverse transform and retransform operations and saves computation. In this paper, we propose a new technique for transcoding the DCT blocks to wavelet coefficients directly in the transform domain. We perform filtering, IDCT and downsampling operations in a single combined step. The proposed technique achieves the same computational result as that of a spatial domain technique. The transcoding matrices used in the proposed technique are found to satisfy certain symmetric and sparse properties, which are exploited to reduce the computational cost. As the number of zeros in the DCT coefficients is significantly higher compared to the spatial domain, computational cost reduces significantly. Also, with the proposed technique, it is possible to speedup the operation by ignoring some elements in the filtering matrices whose magnitudes are smaller than a threshold value. We demonstrate the application of the proposed transcoding for deblocking of the DCT-coded images in wavelet domain.     

SPECK图像编码的改进算法

为了解决SPECK（Set Partitioning Embedded Block Coder集合分裂嵌入块）算法占用大量存储空间的问题，给出了一种无链表SPECK图像压缩算法LSK。LSK编码算法不需要链表，算法简单编码速度很快，适合硬件实现。改进方法用状态表来代替链表保存编码的码块和信息，状态表中每个小波系数由2个比特来表示。图像数据以z字形扫描后的一维数组形式储存，这种方法计算高效，算法简单。文中小波变换采用9／7提升分解算法，量化为均匀标量量化。实验结果表明，该算法与SPECK相近，比SPIHT效果好。     

Popular biorthogonal wavelet filters via a lifting scheme and its application in image compression

A technique using a lifting scheme is presented for constructing compactly supported wavelets whose coefficients are composed of free variables locating in an interval. An efficient approach-based wavelet for image compression is developed by selecting the coefficients of the 9-7 wavelet filter and associated lifting scheme. Furthermore, the rationalised coefficients wavelet filter that can be implemented with simple integer arithmetic is achieved and its characteristic is close to the well known original irrational coefficients 9-7 wavelet filters developed by A. Cohen et al. (Commun. Pure Appl. Maths., vol.45, no.1, p.485-560, 1992). To reduce the computational cost of image coding applications further, an acceleration technique is proposed for the lifting steps. Software and hardware simulations show that the new method has very low complexity, and simultaneously preserves the high quality of the compressed image.     

提升小波高速分解的系统设计与实现

为了解决小波变换在图像实时处理系统中的瓶颈问题,提出了一种硬件实现9/7整形小波高速变换的方法。该方法使用新的小波变换结构和小波变换基,采用一种基于行列同时变换的多级同时变换方式,即进行多级同时变换,且每一级的行列变换也同时进行。使用现场可编程逻辑门阵列（FPGA,Field Programmable Gate Array）的IP核实现片内缓存,降低了设计的复杂度,实现了图像的高速分解。整个设计采用VHDL对算法完成建模和实现,综合和仿真结果表明,该系统占用的资源少,分解速度很快,实现了高速的图像数据流输出,可应用到图像压缩的很多领域。     

An Integrated Systolic Array Design for Video Compression

This paper presents an integrated systolic array design for implementing full-search block matching, 2-D discrete wavelet transform, and full-search vector quantization on the same VLSI architecture. These functions are the prime components in video compression and take a great amount of computation. To meet the real-time application requirements, many systolic array architectures are proposed for individually performing one of those functions. However, these functions contain similar computational procedure. The matrix-vector product forms of the three functions are quite analogous. After extracting the common computation component, we design an integrated one-dimensional systolic array that can perform aforementioned three functions. The proposed architecture can efficiently perform three typical functions: (1) the full-search block matching with block of size 16 × 16 and the search are from –8 to 7; (2) the 2-D 2 level Harr transform with block of size 8 × 8; and (3) the full-search vector quantization with input vector of size 2 × 2. A utilization rate of 100% to 97% is achieved in the course of executing full-search block matching and full-search vector quantization. When it comes to perform 2-D discrete wavelet transform, the utilization rate is about 32%. The proposed integrated architecture has lowered hardware cost and reduced hardware structure. It befits the VLSI implementation for video/image compression applications.     

9/7提升小波变换图像处理算法的高速FPGA实现

提升结构(Lifting Scheme)是一种新的双正交小波变换构造方法.这种方法使得计算复杂度大大降低,有效地减少了运行时间.介绍了基于FPGA的高速9/7提升小波变换的设计,提出采用多级流水线硬件结构实现一维离散小波变换(1-D DWT).该结构使系统吞吐量提高到原来的3倍,面积仅增加40%.在实现二维离散小波变换(2-D DWT)时采用基于行的结构,可以提高片内资源利用率和运行速度,满足小波变换实时性的要求.     

A New Design Method of 9-7 Biorthogonal Filter Banks Based on Odd Harmonic Function

The floating-point implementation of a CDF-9-7 wavelet transform with irrational coefficients on a resource limited hardware platform is a challenging task. This paper presents a new design method of 9-7 biorthogonal wavelet filter bank (FB) based on classical Fourier theory, the so-called odd harmonic function (OHF) analysis. Three types of binary rational 9-7 biorthogonal wavelet FBs have been derived, considering vanishing moments in addition to the rationality of filter coefficients. The extensive experiments for the implementation of the new design on the SPIHT (Set Partitioning In Hierarchical Trees) platform have been conducted and the results show that the performance of the proposed new biorthogonal FBs is equal to, or in several cases outperforms the, CDF-9-7 FB.     

基于有记忆信源模型的视频编码量化算法研究

针对视音频优化量化算法研究,本文通过模拟最佳软判决量化特点,引入系数间的相关性,在硬判决量化基础上提出一种有记忆信源模型的量化算法.该模型统计了量化块中每个位置编码比特节省估计量,利用贝叶斯二值判别法计算出可区分量化结果的最佳估计阈值,二值做差得到码率节省余量,利用码率节省余量实现对量化偏移量的动态调节,从而优化量化算法.实验表明,基于本文的有记忆信源模型相较于传统硬判决量化有显著性能提升,BD-PSNR有0.0964dB提升,相当于3.5723％码率节省.本文偏移量模型基于离线建模,实时计算所需额外计算复杂度较小,适合硬件编码器架构设计实现.     

Motion-compensated 3-D subband coding of video

This paper describes a video coding system based on motion-compensated three-dimensional (3-D) subband/wavelet coding (MC-3DSBC), which can overcome the limits of both 3-D SBC and MC prediction-based coding. In this new system, spatio-temporal subbands are generated by MC temporal analysis and a spatial wavelet transform, and then encoded by 3-D subband-finite state scalar quantization (3DSB-FSSQ). The rate allocation from the GOP level to each class of subbands is optimized by utilizing the structural property of MC-3DSBC that additive superposition approximately holds for both rate and distortion. The proposed video coding system is applied to several test video clips. Its performance exceeds that of both a known MPEG-1 implementation and a similar subband MC predictive coder while maintaining modest computational complexity and memory size.