Comparative assessment of III–V heterostructure and silicon underlap double gate MOSFETs

Comparative assessment of III?CV heterostructure and silicon underlap DG-MOSFETs, is done using 2D Sentaurus TCAD simulation. III?CV heterostructure device has narrow-band In_0.53Ga_0.47As and wide-band InP layers for body, and high-K gate dielectric. Density gradient model is used for simulation and interface traps are considered. Benchmarking of simulation results show that III?CV device provides higher on current, lesser delay, lower energy-delay product and lower DIBL than silicon device. However III?CV device has higher SS and lower I _on/I _off than silicon device. The results indicate that there is a need to optimize the I _on/I _off, SS and DIBL values for specific circuits.     

Impact of leakage current in germanium channel based DMDG TFET using drain-gate underlap technique

In this work, a dual metal (DM) double-gate (DG) Tunnel Field Effect Transistor (DMDG-TFET) with drain-gate underlap is proposed to overcome the challenges in conventional TFET. The ON-current (I_on), OFF-current (I_off), I_on/I_off ratio, subthreshold swing (SS) and ambipolar current (I_ambi) of the proposed device with drain underlap are investigated as gate length is scaled (L_GATE) down. The proposed device gives a better suppression in leakage current and low ambipolar current. The suppressed leakage current (I_off) and ambipolar current (I_ambi) are 9.49 × 10⁻¹⁴ A/µm and 1.95 × 10⁻¹² A/µm respectively for a gate length (L_GATE) of 36 nm and a channel length (L_Ch) of 50 nm for a supply voltage of 0.5 V. Excellent switching behavior is achieved when gate length (L_GATE) is 72% of the channel length (L_Ch). The proposed architecture is suitable for low power applications.     

A study of the linearity between Ion and log Ioff of modern MOS transistors and its application to stress engineering

The authors observed that the on-current (I_on) and the logarithm of the off-current (log(I_off)) of modern submicron MOS transistors tend to follow a very good linear relationship. This paper shall provide a tentative explanation on this experimentally observed linear relationship. Our experimental data show that I_on has a very good linear relationship with drain induced barrier lowering (DIBL). Similarly, log I_off has a very good linear relationship with DIBL. Thus, the mathematical elimination of DIBL will imply a very good linear relationship between I_on and log I_off. Finally, we will demonstrate the application of our theory to both n-channel and p-channel MOS transistors with and without tensile stress.     

Modeling of gate underlap junctionless double gate MOSFET as bio-sensor

In this work, the sensitivity of two types gate underlap Junctionless Double Gate Metal-Oxide-Semiconductor Field-Effect Transistor (JL DG MOSFET) has been compared when the analytes bind in the underlap region. Gate underlap region considered at source end and drain end once at a time in the channel of JL DG MOSFET. Separate models have been derived for both types of gate underlap JL DG MOSFETs and verified through device simulation TCAD tool sprocess and sdevice. To detect the bio-molecules, Dielectric Modulation technique has been used. The shift in the threshold voltage has been pondered as the sensing parameter to detect the presence of biomolecules when they are bound in gate underlap channel region of the devices.     

Novel attributes in scaling issues of carbon nanotube field-effect transistors

For the first time, we present a scaling study of carbon nanotube field-effect transistors (CNTFETs) using a two-dimensional model. We investigate the scaling issues in device performance focusing on transconductance characteristics, output characteristics, average velocity, I_on/I_off ratio, subthreshold swing and drain-induced barrier lowering (DIBL) with different gate oxide thicknesses and carbon nanotube (CNT) diameters. We concluded that the I_on/I_off ratio increases with the gate oxide thickness reduction and increase in the CNT diameter and lead to a high on-state current. Furthermore, leakage current reduces with decrease in the gate oxide thickness, but it becomes higher in CNTFETs with larger CNT diameter. Also, our results show the output conductance, transconductance, voltage gain and average electron velocity at the top of the barrier improve in CNTFETs with thinner gate oxide and larger CNT diameter. In addition, the investigation of short channel effects shows that CNTFETs with thinner gate oxide offer lower DIBL and subthreshold swing, but in the CNTFETs with larger CNT diameter DIBL and subthreshold swing become worse.     

Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET

In this article, surface-potential-based analytical threshold voltage model for underlap Fully Depleted Silicon-On-Insulator MOSFET (underlap-SOI) is developed by solving two-dimensional Poisson equation. The gate underlap at source/drain (S/D) has different boundary conditions as compared to channel region under the gate dielectric that divide the whole channel into three regions. It leads us to derive the new surface potential model for three different channel regions, i.e. the region under the gate dielectric and two gate underlap regions at S/D. The effects of underlap length, channel length, body thickness, channel doping concentration, metal gate work function and gate dielectric constant on threshold voltage have been included in our model. The threshold voltage dependence on different device parameters has been studied using analytical model and simulations. The closeness between the simulation results and model results show that the analytical model accurately calculate the threshold voltage values for large range of device parameters.     

Analysis of Harmonic distortion in asymmetric underlap DG-MOSFET with high-k spacer

In analog and RF circuit applications Harmonic distortion (HD) is an important reliability issue that arises due to non-linear performance of devices. In this paper, the asymmetric underlap double gate MOSFET (AUDG-MOSFET) is analyzed for the HD with high-k spacers. In this analysis the devices are compared for their primary distortion components designated by the second order distortion (HD2), the third order distortion (HD3) and the total harmonic distortion (THD). The distortion characteristics of the device are studied as a function of the gate voltage (V_gs) and the transconductance generation factor (g_m/I_d) considering the influence of drain current (I_d) and the transconductance (g_m). A significant improvement on the HD of the device by using high-k spacers is inferred, thereby ascertaining better reliability for RF applications. In addition to this, the distortion in the output characteristics of Cascode and differential amplifier circuits designed with AUDG-MOSFET device is also analyzed in detail.     

Modeling and simulation of enhancement mode p-GaN Gate AlGaN/GaN HEMT for RF circuit switch applications

An enhancement mode p-GaN gate AlGaN/GaN HEMT is proposed and a physics based virtual source charge model with Landauer approach for electron transport has been developed using Verilog-A and simulated using Cadence Spectre, in order to predict device characteristics such as threshold voltage, drain current and gate capacitance. The drain current model incorporates important physical effects such as velocity saturation, short channel effects like DIBL (drain induced barrier lowering), channel length modulation (CLM), and mobility degradation due to self-heating. The predicted I_d-V_ds, I_d-V_gs, and C-V characteristics show an excellent agreement with the experimental data for both drain current and capacitance which validate the model. The developed model was then utilized to design and simulate a single-pole single-throw (SPST) RF switch.     

Flicker and thermal noise in an n-channel underlap DG FinFET in a weak inversion region

We propose an analytical model for drain current and inversion charge in the subthreshold region for an underlap DG FinFET by using the minimum channel potential method,i.e.,the virtual source.The flicker and thermal noise spectral density models are also developed using these charge and current models expression.The model is validated with already published experimental results of flicker noise for DG FinFETs.For an ultrathin body,the degradation of effective mobility and variation of the scattering parameter are considered.The effect of device parameters like gate length L_g and underlap length L_un on both flicker and thermal noise spectral densities are also analyzed.Increasing L_g and L_un,increases the effective gate length,which reduces drain current,resulting in decreased flicker and thermal noise density.A decrease of flicker noise is observed for an increase of frequency, which indicates that the device can be used for wide range of frequency applications.     

Investigation of temperature variations on analog/RF and linearity performance of stacked gate GEWE-SiNW MOSFET for improved device reliability

In this paper, reliability issues of Stacked Gate (SG)-Gate Electrode Workfunction Engineered (GEWE)-Silicon Nanowire (SiNW) MOSFET is examined over a wide range of ambient temperatures (200–600 K) and results so obtained are simultaneously compared with conventional SiNW and GEWE-SiNW MOSFET using 3D-technology computer aided design quantum simulation. The results indicate that two temperature compensation points (TCP) are obtained: one for drain current (I_ds) and other for cut-off frequency (f_T) where device Figure Of Merits (FOMs) become independent of temperature, and it is found at 0.65 V in SG-GEWE-SiNW in comparison to other devices, hence will open opportunities for wide range of temperature applications. Furthermore, significant improvement in Analog/RF performance of SG-GWEW-SiNW is observed in terms of I_on/I_off, Subthreshold Swing (SS), device efficiency, f_T, noise conductance and noise figure as temperature reduces. It is also observed that at low temperature SG-GEWE-SiNW unveils highly stable linearity performance owing to reduced distortions. These results explain the improved reliability of SG-GEWE-SiNW at low temperatures over GEWE-SiNW MOSFET.     

Design of a novel double doping polysilicon gate MOSFET

In this paper, a novel design of the double doping polysilicon gate MOSFET device is proposed, which has a p+ buried layer near the drain, and relatively thicker D-gate oxide film (DDPGPD MOSFET). The detailed fabrication process for this device is designed using process simulation software called TSUPREM, and the device structure plan is further used in MEDICI simulation. The effect of gate doping concentration is investigated, and it is found that the device V_th is only influenced by the S-gate; furthermore, the device can get a larger driving current by increasing the doping concentration of D-gate. Compared to other conventional DDPG MOSFETs, the short-channel effects (SCEs) including the off-state current, the gate leakage current and the drain induced barrier lowering effect (DIBL) can be effectively suppressed by the p+ buried layer and thicker D-gate oxide film. Additionally, the other parameters of the device such as the driving current are not seriously affected by the proposed design modifications.     

Modeling and performance study of nanoscale double gate junctionless and inversion mode MOSFETs including carrier quantization effects

In this report we focus on the performance of nanoscale double gate (DG) junctionless (JL) and inversion mode (IM) MOSFETs. The study is performed using an analytical 2-D modeling approach from our previous work and an extension for the inclusion of carrier quantization effects (QEs). The model itself is physics-based, predictive and valid in all operating regimes. Important device metrics such as the drain-induced barrier lowering (DIBL), subthreshold slope (S  ) and the _Ion/_Ioff$I_{\mathit{on}}/I_{\mathit{off}}$ ratios are in focus and discussed. The model is compared versus 2-D numerical simulation results from TCAD Sentaurus. To stand the pace with recent ITRS requirements for future CMOS technology, we target devices with a minimum channel length of 16 nm and channel thicknesses down to 3 nm. The purpose of the research is to gain knowledge about the device?s performance at such aggressively scaled dimensions.     

Area efficient layout design of CMOS circuit for high-density ICs

Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher I_on to I_off ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.     

Analog and radio-frequency performance analysis of silicon-nanotube MOSFETs

This work presents a comparative study of the influence of various parameters on the analog and RF properties of silicon-nanotube MOSFETs and nanowire-based gate-all-around (GAA) MOSFETs. The important analog and RF performance parameters of SiNT FETs and GAA MOSFETs, namely drain current (I_d), transconductance to drain current ratio (g_m/I_d), I_on/I_off, the cut-off frequency (f_T) and the maximum frequency of oscillation (f_MAX) are evaluated with the help of Y- and H-parameters which are obtained from a 3-D device simulator, ATLAS^TM. It is found that the silicon-nanotube MOSFETs have far more superior analog and RF characteristics (g_m/I_d, f_T and f_MAX) compared to the nanowire-based gate-all-around GAA MOSFETs. The silicon-nanotube MOSFET shows an improvement of~2.5 and 3 times in the case of f_T and f_MAX values respectively compared with the nanowire-based gate-all-around (GAA) MOSFET.     

Performance analysis of 20 nm gate-length In0.2Al0.8N/GaN HEMT with Cu-gate having a remarkable high ION/IOFF ratio

Abstract： We propose a new structure of InxAll-xN/GaN high electron mobility transistor （HEMT） with gate length of 20 nm. The threshold voltage of this HEMT is achieved as -0.472 V. In this device the InA1N barrier layer is intentionally n-doped to boost the ION/IOFF ratio. The InAlN layer acts as donor barrier layer for this HEMT which exhibits an ION = 10-4.3 A and a very low IOFF = 10-14.4 A resulting in an ION/IoFF ratio of 1010.1. We compared our obtained results with the conventional InAlN/GaN HEMT device having undoped barrier and found that the proposed device has almost l0s times better ION/IOFF ratio. Further, the mobility analysis in GaN channel of this proposed HEMT structure along with DC analysis, C-V and conductance characteristics by using small-signal analysis are also presented in this paper. Moreover, the shifts in threshold voltage by DIBL effect and gate leakage current in the proposed HEMT are also discussed. InAlN was chosen as the most preferred barrier layer as a replacement of AlGaN for its excellent thermal conductivity and very good scalability.     

Impact of gate metal work-function engineering for enhancement of subthreshold analog/RF performance of underlap dual material gate DG-FET

This work presents a systematic comparative study of analog/RF performance for underlap dual material gate (U-DMG) DG NMOSFET. In previous works, improved device performances have been achieved by use of high dielectric constant (k) spacer material. Although high-k spacers improve device performance, the intrinsic gain of the device reduces. For the analog circuits applications intrinsic gain is an important parameter. Hence, an optimized spacer material having dielectric constant, k = 7.5 has been used in this study and the gain is improved further by dual-material gate (DMG) technology. In this paper we have also studied the effect of gate material having different work function on the U-DMG DG NMOSFETs. This device exploits a step function type channel potential created by DMG for performance improvement. Different parameters such as the transconductance (g_m), the gain per unit current (g_m/I_ds), the intrinsic gain (g_mR_o), the intrinsic capacitance, the intrinsic resistance, the transport delay and, the inductance of the device have been analyzed for analog and RF performance analysis. Analysis suggested that the average intrinsic gain, g_m/I_d and g_m are increase by 22.988%, 16.10% and 27.871% respectively compared to the underlap single-material gate U-DG NMOSFET.     

Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity: a novel approach

In this paper TCAD-based simulation of a novel insulated shallow extension (ISE) cylindrical gate all around (CGAA) Schottky barrier (SB) MOSFET has been reported,to eliminate the suicidal ambipolar behavior (bias-dependent OFF state leakage current) of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions.This novel structure offers low barrier height at the source and offers high ON-state current.The ION/IoFF of ISE-CGAA-SB-MOS-FET increases by 1177 times and offers steeper subthreshold slope (～60 mV/decade).However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate,dual metal gate,single metal gate with ISE,and dual metal gate with ISE has been presented.The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design.The numerical simulation is performed using the ATLAS-3D device simulator.     

Comparative study of AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with Al2O3 and HfO2 gate oxide

AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOSHFETs) with Al₂O₃ gate oxide which was deposited by atomic layer deposition (ALD) were fabricated and their performance was then compared with that of AlGaN/GaN MOSHFETs with HfO₂ gate oxide. The capacitance (C)-voltage (V) curve of the Al₂O₃/GaN MOS diodes showed a lower hysteresis and lower interface state density than the C-V curve of the HfO₂/GaN diodes, indicating better quality of the Al₂O₃/GaN interface. The saturation of drain current in the I_D-V_GS relation of the Al₂O₃ AlGaN/GaN MOSHFETs was not as pronounced as that of the HfO₂ AlGaN/GaN MOSHFETs. The gate leakage current of the Al₂O₃ MOSHFET was five to eight orders of magnitude smaller than that of the HfO₂ MOSHFETs.     

Polarization-Engineered Ga-Face GaN-Based Heterostructures for Normally-Off Heterostructure Field-Effect Transistors

Polarization-engineered Ga-face GaN-based heterostructures with a GaN cap layer and an AlGaN/p-GaN back barrier have been designed for normally-off field-effect transistors (FETs). The simulation results show that an unintentionally doped GaN cap and p-GaN layer in the buffer primarily deplete electrons in the channel and the Al_0.2Ga_0.8N back barrier helps to pinch off the channel. Experimentally, we have demonstrated a normally-off GaN-based field-effect transistor on the designed GaN cap/Al_0.3Ga_0.7N/GaN channel/Al_0.2Ga_0.8N/p-GaN/GaN heterostructure. A positive threshold voltage of 0.2 V and maximum transconductance of 2.6 mS/mm were achieved for 80-μm-long gate devices. The device fabrication process does not require a dry etching process for gate recessing, while highly selective etching of the GaN cap against a very thin Al_0.3GaN_0.7N top barrier has to be performed to create a two-dimensional electron gas for both the ohmic and access regions. A self-aligned, selective etch of the GaN cap in the access region is introduced, using the gate metal as an etch mask. The absence of gate recess etching is promising for uniform and repeatable threshold voltage control in normally-off AlGaN/GaN heterostructure FETs for power switching applications.     

Impact of lateral straggle on analog and digital circuit performance using independently driven underlap DG-MOSFET

In this work, the effect of lateral straggle on independently driven underlap double gate MOSFET (IDUDGMOS) is presented based on analog and digital circuit performances. The lateral straggle in IDUDGMOS devices is due to process induced source/drain out diffusion and it varies the desired device characteristics. For the analysis of this variation on circuit performance of the device, an Amplitude Modulator (AM) circuit and a SRAM circuit is considered for analog and digital circuit application considerations respectively. For the analysis of the device in AM circuit the parameters studied are the bandwidth, the gain and the linearity, correspondingly for SRAM circuit the parameters studied are the Static Noise Margin (SNM) and the circuit delay. The analysis of the AM circuit designed using the IDUDGMOS suggested that the power loss and the bandwidth of the circuit degrade with increasing lateral straggle. For the SRAM circuit the analysis suggests that larger straggle lengths in the device results in reduced time delay but, the SNM is smaller as well.