栅控二极管R-G电流法表征SOI-MOS器件埋氧层界面陷阱的敏感性分析

通过数值模拟手段,用归一化的方法研究了界面陷阱、硅膜厚度和沟道掺杂浓度对R-G电流大小的影响规律.结果表明:无论在FD还是在PD SOI MOS器件中,界面陷阱密度是决定R-G电流峰值的主要因素,硅膜厚度和沟道掺杂浓度的影响却因器件的类型而异.为了精确地用R-G电流峰值确定界面陷阱的大小,器件参数的影响也必须包括在模型之中.     

栅控二极管正向 R- G电流对 SOI体陷阱特征和硅膜结构的依赖性

使用半导体器件数值分析工具 DESSISE- ISE,对侧向的 P+ P- N+栅控二极管的正向 R- G电流对 SOI体陷阱特征和硅膜结构的依赖性进行了详尽的研究 .通过系统地改变硅膜体陷阱的密度和能级分布 ,得出了相应的 P+ P-N+ 栅控二极管的正向 R- G电流的变化 .同时 ,表征硅膜结构的参数如沟道掺杂和硅膜厚度的变化也使器件从部分耗尽向全耗尽方向转化 ,分析了这种转化对 R- G电流大小和分布的影响     

亚100nm SOI器件的结构优化分析

分析了SOI器件各结构参数对器件性能的影响,给出了器件各结构参数的优化方向,找出了可行硅膜厚度和可行沟道掺杂浓度之间的设计容区.在部分耗尽与全耗尽SOI器件的交界处,阈值电压的漂移有一个峰值,在器件设计时应避免选用这一交界区.此外,随着硅膜厚度的减小,器件的泄漏电流随着沟道掺杂浓度的不同,有一个极小值.通过模拟分析发现,只要合理选择器件的结构参数,就能得到性能优良的SOI器件.     

亚100nm SOI器件的结构优化分析

分析了SOI器件各结构参数对器件性能的影响,给出了器件各结构参数的优化方向,找出了可行硅膜厚度和可行沟道掺杂浓度之间的设计容区.在部分耗尽与全耗尽SOI器件的交界处,阈值电压的漂移有一个峰值,在器件设计时应避免选用这一交界区.此外,随着硅膜厚度的减小,器件的泄漏电流随着沟道掺杂浓度的不同,有一个极小值.通过模拟分析发现,只要合理选择器件的结构参数,就能得到性能优良的SOI器件     

对异型硅岛实现的厚膜全耗尽SOIMOSFET的模拟研究

本文提出了用异型硅岛实现的厚膜全耗尽(FD)SOI MOSFET的新结构,并分析了其性能与结构参数的关系.通过在厚膜SOI MOSFET靠近背栅的界面形成一个相反掺杂的硅岛,从而使得厚膜SOI MOSFET变成全耗尽器件.二维模拟显示,通过对异型硅岛的宽度、厚度、掺杂浓度以及在沟道中位置的分析与设计,厚膜SOI MOSFET不仅实现了全耗尽,从而克服了其固有的Kink效应,而且驱动电流也大大增加,器件速度明显提高,同时短沟性能也得到改善.模拟结果证明:优化的异型硅岛应该位于硅膜的底部中央处,整个宽度约为沟道长度的五分之三,厚度大约等于硅膜厚度的一半,掺杂浓度只要高出硅膜的掺杂浓度即可.重要的是,异型硅岛的设计允许其厚度、宽度、掺杂浓度以及位置的较大波动.可以看出,异型硅岛实现的厚膜全耗尽 SOI MOSFET 为厚膜SOI器件提供了一个更广阔的设计空间.     

栅控二极管正向R-G电流对SOI体陷阱特征和硅膜结构的依赖性

使用半导体器件数值分析工具DESSISE-ISE,对侧向的P＋P－N＋栅控二极管的正向R-G电流对SOI体陷阱特征和硅膜结构的依赖性进行了详尽的研究．通过系统地改变硅膜体陷阱的密度和能级分布,得出了相应的P＋P－N＋栅控二极管的正向R-G电流的变化．同时,表征硅膜结构的参数如沟道掺杂和硅膜厚度的变化也使器件从部分耗尽向全耗尽方向转化,分析了这种转化对R-G电流大小和分布的影响．     

SOI和体硅MOSFET大信号非准静态效应比较研究

研究了全耗尽SOI、部分耗尽SOI和体硅NMOS器件中源、漏、栅和衬底电流的非准静态现象。研究表明,在相同的结构参数下,体硅器件的非准静态效应最强,PDSOI次之,FDSOI最弱。指出了沟道源、漏端反型时间和反型程度的不同是造成非准静态效应的内在原因。最后提出临界升压时间的概念,以此对非准静态效应进行定量表征,深入研究器件结构参数对非准静态效应的影响规律。结果显示,通过缩短沟道长度、降低沟道掺杂浓度、减小硅膜厚度和栅氧厚度、提高埋氧层厚度等手段,可以弱化SOI射频MOS器件中的非准静态效应。     

GaN基HEMT器件结构设计及其性能仿真北大核心

利用Silvaco TCAD器件模拟软件研究了AlGaN/GaN高电子迁移率晶体管(HEMT)器件势垒层的厚度、沟道宽长比和掺杂浓度对器件的转移特性和跨导曲线的影响。结果表明,器件势垒层厚度的变化可以调节器件的电流开关比和开启电压,实现由耗尽型器件向增强型器件的转变;沟道宽长比的改变可以调节器件的开启电压,并且随着沟道宽长比的增加,栅极电压控制量子阱中二维电子气的能力增强;势垒层适量掺杂提高了输出电流,并且使跨导的峰值增大,但过度掺杂会造成器件不易关断情况出现。     

An Analytical Threshold Voltage Model for Fully Depleted SOI MOSFETs

提出了一种新的全耗尽SOI MOSFETs阈值电压二维解析模型.通过求解二维泊松方程得到器件有源层的二维电势分布函数,氧化层-硅界面处的电势最小值用于监测SOI MOSFETs的阈值电压.通过对不同栅长、栅氧厚度、硅膜厚度和沟道掺杂浓度的SOI MOSFETs的MEDICI模拟结果的比较,验证了该模型,并取得了很好的一致性.     

复合栅控二极管新技术提取热载流子诱生的NMOS/SOI器件界面陷阱的横向分布

提出了用复合栅控二极管新技术提取MOS/SOI器件界面陷阱沿沟道横向分布的原理,给出了具体的测试步骤和方法.在此基础上,对具有体接触的NMOS/SOI器件进行了具体的测试和分析,给出了不同的累积应力时间下的界面陷阱沿沟道方向的横向分布.结果表明:随累积应力时间的增加,不仅漏端边界的界面陷阱峰值上升,而且沿沟道方向,界面陷阱从漏端不断向源端增生.     

Numerical Analysis of Characterized Back Interface Traps of SOI Devices by R-G Current

Characterized back interface traps of SOI devices by the Recombination\|Generation (R\|G) current has been analyzed numerically with an advanced semiconductor simulation tool,namely DESSIS\|ISE.The basis of the principle for the R\|G current's characterizing the back interface traps of SOI lateral p\++p\+-n\++ diode has been demonstrated.The dependence of R\|G current on interface trap characteristics has been examined,such as the state density,surface recombination velocity and the trap energy level.The R\|G current proves to be an effective tool for monitoring the back interface of SOI devices.     

A novel subthreshold slope technique for the extraction of theburied-oxide interface trap density in the fully depleted SOIMOSFET

A novel experimental technique, based on the double-gate operation, is proposed for extracting the back interface trap density of the fully depleted SOI MOSFET. The method relies on simple current-voltage measurements, requires no prior knowledge of the silicon film thickness, and successfully eliminates inaccuracies arising from thickness variations of the accumulation layer, by maintaining both interfaces in depletion. The sensitivity of the technique is shown to depend on the ratio of the interface trap and oxide capacitances of the buried oxide, and is thus limited only by the buried oxide thickness. The technique has been successfully used to monitor the increase in back interface trap density following Fowler-Nordheim stress     

复合栅控二极管新技术提取热载流子诱生的NMOS/SOI器件界面陷阱的横向分布

提出了用复合栅控二极管新技术提取MOS/SOI器件界面陷阱沿沟道横向分布的原理,给出了具体的测试步骤和方法.在此基础上,对具有体接触的NMOS/SOI器件进行了具体的测试和分析,给出了不同的累积应力时间下的界面陷阱沿沟道方向的横向分布.结果表明:随累积应力时间的增加,不仅漏端边界的界面陷阱峰值上升,而且沿沟道方向,界面陷阱从漏端不断向源端增生.     

Reduction of threshold voltage sensitivity in SOI MOSFET's

The threshold voltage sensitivity, of fully depleted SOI MOSFET's to variations in SOI silicon film thickness was examined through both simulation and device experiments. The concept of designing the channel V_th implant to achieve a constant dose within the film, rather than a constant doping concentration, was studied for a given range of film thicknesses. Minimizing the variation in retained dose reduced the threshold voltage sensitivity to film thickness for the range of t_si examined. One-dimensional process simulations were performed to determine the optimal channel implant condition that would reduce the variation in retained dose using realistic process parameters for both NMOS and PMOS device processes. SOI NMOS transistors were fabricated. The experimental results confirmed the simulation findings and achieved a reduced threshold voltage sensitivity     

Unified MOSFET Short Channel Factor Using Variational Method

It is well known that short channel effect is one of the most important constraints that determine the downscaling of MOSFET's.The relationship between the device structure configuration and short channel effect is first expressed empirically in Ref.[1].And recently,due to...     

Unified MOSFET Short Channel Factor Using Variational Method

A new natural gate length scale for MOSFET's is presented using Variational Method. Comparison of the short channel effects is conducted for the uniform channel doping bulk MOSFET, intrinsic channel doping bulk MOSFET, SOI MOSFET and double gated MOSFET. And the results are verified by the 2D numerical simulation. Taken all the 2-D effects on front gate dielectric, back gate dielectric and silicon film into account, the data validity of electrical equivalent oxide thickness is investigated by this model, as shows that it is valid only when the gate dielectric constant is relatively small.