A CMOS current-mode design of modified learning-vector-quantization neural networks

A modification of LVQ model, Modified LVQ (MLVQ) model, is proposed for the estimation of centroid in pattern recognition. Computer simulation results are presented which demonstrate the behavior of the MLVQ model in estimating the class centroid by utilizing the distance-dependent step size. The results indicate the high potential of less dependence on the initial point as well as the precise settlement of the weight vectors to the centroids. The main feature is that the proposed model is robust to the noise perturbation between two pattern distributions in practical applications.To take advantage of this MLVQ model with the faster training and recalling process for patterns, a hybrid analogdigital processing system is designed by the CMOS current-mode integrated circuit (IC) technology and offers the best attributes of both analog and digital computation. This hybrid processing system operates at microsecond time scale, which enables it to produce real time solutions for complex spatiotemporal problems found in high speed signal processing applications. The overall neural processing system has also been simulated and verified by the HSPICE circuit simulator.     

Novel CMOS sampled-data VLSI implementation of artificial neural networks

A mixed-mode VLSI implementation of artificial neural networks offers a tradeoff solution for speed, area saving, and flexibility. A novel CMOS sampled-data programmable synapse and a simple CMOS analogue neuron have been developed. Using a 1.2 mu m CMOS technology, the synapse consumed 120*120 mu m/sup 2/ and the neuron consumed 120*260 mu m/sup 2/.<>     

High-performance current-mode CMOS simultaneous implementation of window-literal operations for multi-valued logic

A new current-mode CMOS circuit for simultaneous implementation of literal and complementary literal operations is presented. It is shown that the proposed circuit exhibits superior performance compared to its previous counterparts in terms of speed power dissipation and robustness with much smaller area. These advantages make the circuit a very useful design block for multivalued logic function realisations.     

基于神经网络的自学习非特定人语音识别研究

详细介绍一种基于神经网络的自学习非特定人语音识别方法,首次介绍一种语音识别知识的自动检验方法——LVV法,给出系统原理图和知识库的自动完善原理;介绍一种LEA判别法,实现梯度牛顿有效结合神经网络快速学习方法,并给出了实验结果。     

Smart-pixel cellular neural networks in analog current-mode CMOStechnology

This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities. These chips consist of regular arrangements of elementary units, called smart pixels. Light detection is made with vertical CMOS-BJT's connected in a Darlington structure. Pixel smartness is achieved by exploiting the cellular neural network paradigm, incorporating at each pixel location an analog computing cell which interacts with those of nearby pixels. We propose a current-mode implementation technique and give measurements from two 16 x 16 prototypes in a single-poly double-metal CMOS n-well 1.6-μm technology. In addition to the sensory and processing circuitry, both chips incorporate light-adaptation circuitry for automatic contrast adjustment. They obtain smart-pixel densities up to 89 units/mm², with a power consumption down to 105 μW/unit and image processing times below 2 μs     

CMOS continuous-time current-mode filters for high-frequencyapplications

Design considerations for high-frequency CMOS continuous-time current-mode filters are presented. The basic building block is a differential current integrator with its gain constant set by a small-signal transconductance and a gate capacitance. A prototype fifth-order low-pass ladder filter implemented in a standard digital 2 μm n-well CMOS process achieved a -3 dB cutoff frequency (f ₀) of 42 MHz; f₀ was tunable from 24 to 42 MHZ by varying a reference bias current from 50 to 150 μA. Using a single 5 V power supply with a nominal reference current of 100 μA, the five-pole filter dissipated 25.5 mW. The active filter area was 0.056 mm²/pole. With the minimum input signal defined as the input-referred noise integrated over a 40 MHz bandwidth, and the maximum input signal defined at the 1% total intermodulation distortion (TIMD) level, the measured dynamic range was 69 dB. A third-order elliptic low-pass ladder filter was also integrated in the 2 μm n-well CMOS process to verify the implementation of finite transmission zeros     

Neural networks for statistical recognition of continuous speech

In recent years there has been a significant body of work, both theoretical and experimental, that has established the viability of artificial neural networks (ANN's) as a useful technology for speech recognition. It has been shown that neural networks can be used to augment speech recognizers whose underlying structure is essentially that of hidden Markov models (HMM's). In particular, we have demonstrated that fairly simple layered structures, which we lately have termed big dumb neural networks (BDNN's), can be discriminatively trained to estimate emission probabilities for an HMM. Recently simple speech recognition systems (using context-independent phone models) based on this approach have been proved on controlled tests, to be both effective in terms of accuracy (i.e., comparable or better than equivalent state-of-the-art systems) and efficient in terms of CPU and memory run-time requirements. Research is continuing on extending these results to somewhat more complex systems. In this paper, we first give a brief overview of automatic speech recognition (ASR) and statistical pattern recognition in general. We also include a very brief review of HMM's, and then describe the use of ANN's as statistical estimators. We then review the basic principles of our hybrid HMM/ANN approach and describe some experiments. We discuss some current research topics, including new theoretical developments in training ANN's to maximize the posterior probabilities of the correct models for speech utterances. We also discuss some issues of system resources required for training and recognition. Finally, we conclude with some perspectives about fundamental limitations in the current technology and some speculations about where we can go from here     

A programmable analog CMOS synapse for neural networks

This paper presents a programmable analog synapse for use in both feedforward and feedback neural networks. The synapse consists of two complementary floating-gate MOSFETs which are programmable in both directions by Fowler-Nordheim tunneling. The P-transistor and the N-transistor are programmable independently with pulses of different amplitude and duration, and hence finer weight adjustment is made possible. An experimental 4×4 synapse array has been designed, which in addition has 32 analog CMOS switches and x–y decoders to select a synapse cell for programming. It has been fabricated using a standard 2-m, double-polysilicon CMOS technology. Simulation results confirm that output current of synapse is proportional to the product of the input voltage and weight and also shows both inhibitory and excitatory current. Current summing effect has been observed at the input of a neuron. This array is designed using modular and regular structured elements, and hence is easily expandable to larger networks.     

Parallel implementation of neural networks

This paper presents systematic methods, based on graph theoretic approach, for mapping of neural networks onto mesh connected SIMD arrays. The methods are applicable to a large class of multilayer network models, which can be represented in terms of sparse matrix vector operations. The class of computers, that the mappings are suitable for, encompasses most of the experimental and commercial mesh-connected SIMD arrays of processors. There are three methods described in the paper, one for the case of a processor array, which is larger or equal to the network size and two for the partitioned case, i.e. array smaller than the input data size. The methods are illustrated on an example of a multilayer perceptron with back-propagation learning, which consists ofn nuerons ande synaptic connections. For the first method, the processor array is assumed to be of sizeN×N, whereN ² n+e, and the required local memory of processors is limited to only a few registers. The implementation of a single iteration of a recall phase according to the method requires 24(N-1) shifts. For this method we have developed a software tool, which generates a sequence of pseudo instructions, such as elemental data shift and arithmetic operations, that implement a given neural network on a given size processor array. For the two partitioned methods, the processor array is of sizeP×P, whereP ²n+e, and the local memory in the processors is of sizeO(K). The faster of the two methods requiresO(N ³/P ³ K) time for an iteration of the recall or learning phase.This research was supported in part by the National Science Foundation under grant MIP-8714689 and IRI-9145810.Preliminary versions of the results contained in this paper appear in the International Conference on Applications-Specific Array Processors 1990 and the IEEE Workshop on VLSI Signal Processing 1990.     

Analog implementation of neural networks

Analog silicon-based neural hardware, which represents a large category among special-purpose analog and digital neurocomputers, and neural processing algorithms are reviewed. Artificial neural networks usually contain a large number of synaptic connections and many fewer processing neurons. The central problem in implementing artificial neural networks-making weights that are continuously adjustable, preferably in response to an analog control signal-is discussed. A simple integrated-circuit analog multiplier built from all-MOS components for use in electrically tunable synapses is described     

Physically realistic fault models for analog CMOS neural networks

A general methodology for the development of physically realistic fault models for VLSI neural networks is presented. The derived fault models are explained and characterized in detail. The application of this methodology to an analog CMOS implementation of fixed-weight (i.e., pretrained), binary-valued neural networks is reported. It is demonstrated that these techniques can be used to accurately evaluate defect sensitivities in VLSI neural network circuitry. It is also shown that this information can be used to guide the design of circuitry which fully utilizes a neural network's potential for defect tolerance     

A four-quadrant CMOS analog multiplier for analog neural networks

A four-quadrant CMOS analog multiplier is presented. The multiplier uses the square-law characteristic of an MOS transistor in saturation. Its major advantage over other four-quadrant multipliers is its combination of small area and low power consumption. In addition, unlike almost all other designs of four-quadrant multipliers, this design has single ended inputs so that the inputs do not need to be pre-processed before being fed to the multiplier, thus saving additional area. These properties make the multiplier very suitable for use in the implementation of artificial neural networks. The design was fabricated through MOSIS using the standard 2 μm CMOS process. Experimental results obtained from it are presented     

SIMPLIFICATION OF CURRENT-MODE MULTIVALUED CMOS CIRCUITS

This paper proposes a simplification method for realization of current-mode multivalued CMOS circuits. The key of this method is to find a cover on the K-map for a given multivalued function, which fits to the realization of current-mode CMOS circuits. The design example shows that the design presented in this paper is better than the design proposed by G. W. Dueck et al. (1987).     

Specific emitter identification for satellite communication using probabilistic neural networks

Electromagnetic signal emitted by satellite communication (satcom) transmitters are used to identify specific individual uplink satcom terminals sharing the common transponder in real environment, which is known as specific emitter identification (SEI) that allows for early indications and warning (I&W) of the targets carrying satcom furnishment and furthermore the real time electromagnetic situation awareness in military operations. In this paper, the authors are the first to propose the identification of specific transmitters of satcom by using probabilistic neural networks (PNN) to reach the goal of target recognition. We have been devoted to the examination by exploring the feasibility of utilizing the Hilbert transform to signal preprocessing, applying the discrete wavelet transform to feature extraction, and employing the PNN to perform the classification of stationary signals. There are a total of 1000 sampling time series with binary phase shift keying (BPSK) modulation originated by five types of satcom transmitters in the test. The established PNNs classifier implements the data testing and finally yields satisfactory accuracy at 8 dB(±1 dB) carrier to noise ratio, which indicates the feasibility of our method, and even the keen insight of its application in military.     

Learning capacitive weights in analog CMOS neural networks

Implementations of artificial neural networks as analog VLSI circuits differ in their method of synaptic weight storage (digital weights, analog EEPROMs, or capacitive weights) and in whether learning is performed locally at the synapses or off-chip. In this paper, we explain the principles of analog networks with in situ or local synaptic learning of capacitive weights, with test results of CMOS implementations from our laboratory. Synapses for both simple Hebbian and mean field networks are investigated. Synaptic weights may be refreshed by periodic rehearsal on the training data, which compensates for temperature drift or other nonstationarity. Compact high-performance layouts have been obtained in which learning adjusts for component variability.     

DESIGN OF SYMMETRIC TERNARY CURRENT-MODE CMOS CIRCUITS

By applying switch-signal theory, the theory of transmission current-switches based on symmetric ternary logic is proposed, this theory is suitable to design symmetric ternary current-mode CMOS circuits. The symmetric ternary current-mode CMOS circuits designed by using this theory not only have simpler circuit structures and correct logic functions, but also can process bidirectional signals.     

Comparative study between traditional and modified probabilistic neural networks

Probabilistic neural network (PNN) is a kind of supervised neural network, proposed by Specht as an alternative to back-propagation neural network. The key advantages of PNN are that, training requires only a single pass, and decision surfaces are guaranteed to approach the Bayes-optimal decision boundaries, as the number of training samples grows. Furthermore, shape of the decision surface can be made as complex as necessary, or as simple as desired, by choosing an appropriate value of the smoothing parameter; erroneous samples can be tolerated, and sparse samples are adequate for network performance. This paper reviews the PNN, modified PNN, various learning approaches employed to train the PNN and some comparisons of various types of PNN. Experimental results have been carried out to verify the ability of modified PNN in achieving good classification rate over traditional PNN, BPNN and KNN.     

An integrated CMOS current-sensing circuit for low-Voltage current-mode buck regulator

An integrated current-sensing circuit for low-voltage buck regulator is presented. The minimum achievable supply voltage of the proposed current-sensing circuit is 1.2 V implemented in a CMOS technology with V/sub TH/=0.85 V, and the current-sensing accuracy is higher than 94%. With the developed current-sensing circuit, a buck regulator, which is able to operate at a 1.2-V supply, is implemented. A maximum output current of 120 mA and power-conversion efficiency higher than 89% are achieved.