PD SOI nMOSFETs中浮体效应对辐照性能的影响

在SIMOX衬底上制备了H形栅和环形栅PD SOI nMOSFETs,并研究了浮体效应对辐照性能的影响.在106rad(Si)总剂量辐照下,所有器件的亚阈特性未见明显变化.环形栅器件的背栅阈值电压漂移比H型栅器件小33%,其原因是碰撞电离使环形栅器件的体区电位升高,在埋氧化层中形成的电场减小了辐照产生的损伤.浮体效应有利于改进器件的背栅抗辐照能力.     

辐照对SOI NMOS寄生双极晶体管的影响。

在埋氧化层厚度不同的SIMOX衬底上制备了H型栅结构器件。经过总剂量辐照后,器件的正栅亚阈值特性无明显变化,背栅亚阈值特性发生平移,但均未发生漏电,说明其抗辐照性能超过1E6rad(Si)。辐照后器件的寄生双极晶体管增益有所增大,并且与背栅阈值电压的变化趋势相似,可能是由于埋氧化层中的正电荷积累使体区电位升高,提高了发射极的发射效率。     

Direct tunneling-induced floating-body effect in 90-nm pseudo-kink-free PD SOI pMOSFETs with DTMOS-like behavior and low input power consumption

This paper reports the investigation of the direct tunneling-induced floating-body effect in 90-nm H-gate floating body partially depleted (PD) silicon-on-insulator (SOI) pMOSFETs with dynamic-threshold MOS (DTMOS)-like behavior and low input power consumption. Based on this paper, with the decrease of the gate-oxide thickness, the direct-tunneling current will dominate the floating body potential of H-gate PD SOI pMOSFETs, which makes the floating body potential highly gate voltage dependent like DTMOS behavior with a larger drain current. However, the input power consumption is still kept lower. Simultaneously, the highly gate voltage dependent direct-tunneling current will reduce the influence of the impact ionization current on the neutral region with a higher kink onset-voltage. It contributes to the pseudo-kink-free phenomenon in 90-nm H-gate floating body PD SOI pMOSFETs.     

源区浅结SOI MOSFET的辐照效应模拟

研究了源区浅结的不对称SOIMOSFET对浮体效应的改善 ,模拟了总剂量、抗单粒子事件 (SEU)、瞬时辐照效应以及源区深度对抗辐照性能的影响 .这种结构器件的背沟道抗总剂量能力比传统器件有显著提高 ,并且随着源区深度的减小 ,抗总剂量辐照的能力不断加强 .体接触不对称结构的抗SEU和瞬时辐照能力优于无体接触结构和传统结构器件 ,这与体接触对浮体效应的抑制和寄生npn双极晶体管电流增益的下降有关     

边缘注入对H型栅SOI pMOSFETs亚阈值泄漏电流的影响

就不同边缘注入剂量对H型栅SOI pMOSFETs亚阈值泄漏电流的影响进行了研究。实验结果表明不足的边缘注入将会产生边缘背栅寄生晶体管,并且在高的背栅压下会产生明显的泄漏电流。分析表明尽管H型栅结构的器件在源和漏之间没有直接的边缘泄漏通路,但是在有源扩展区部分,由于LOCOS技术引起的硅膜减薄和剂量损失仍就促使了边缘背栅阈值电压的降低。     

PD SOI MOSFET低频噪声研究进展

随着器件尺寸的不断减小,PD SOI器件的低频噪声特性对电路稳定性的影响越来越大.研究了PD SOI器件低频过冲噪声现象,分析了此类器件在发生浮体效应、栅致浮体效应以及前背栅耦合效应时低频过冲噪声的产生机理及影响因素.最后指出,可以通过添加体接触或将PD SOI器件改进为双栅结构,达到有效抑制低频过冲噪声的目的.     

Effects of gate structures on the RF performance in PD SOI MOSFETs

The radio-frequency (RF) performance of PD silicon-on-insulator metal oxide semiconductor field effect transistors with T-gate and H-gate structures has been investigated. Our measurement shows that H-gate devices have larger cutoff frequency and smaller minimum noise figure than T-gate devices. This improved RF performance in H-gate devices can be explained mainly by the enhancement of transconductance resulting from the gate extension induced inversion charges and the low gate resistance. We conclude that the H-gate structure is superior to the T-gate structure for the design of the low-noise amplifier (LNA).     

Gate tunneling leakage current behavior of 40 nm PD SOI NMOS device considering the floating body effect

This paper reports an analysis of floating body effect related gate tunneling leakage current behavior of the 40 nm PD SOI NMOS device using bipolar/MOS equivalent circuit approach. As confirmed by the experimentally measured data, the bipolar/MOS equivalent circuit approach could predict the gate tunneling leakage current behavior, which is strongly affected by the parasitic bipolar device in the floating body as observed from the perpendicular electric field along the path of the U-shaped edges of the polysilicon gate.     

一种抗总剂量辐照的新型PD SOI器件

提出了一种具有叠层埋氧层的新栅型绝缘体上硅(SOI)器件.针对SOI器件的抗总电离剂量(TID)加固方案,对绝缘埋氧层(BOX)采用了叠层埋氧方案,对浅沟槽隔离(STI)层采用了特殊S栅方案.利用Sentaurus TCAD软件,采用Insulator Fixed Charge模型设置固定电荷密度,基于0.18 μm ...     

Status and Trends in Advanced SOI Devices and Materials

A review of recently explored effects in advanced SOI devices and materials is given. The effects of key device parameters on the electrical and thermal floating body effects are shown for various device architectures.Recent advances in the understanding of the sensitivity of electron and hole transport to the tensile or compressive uniaxial and biaxial strains in thin film SOI are presented. The performance and physical mechanisms are also addressed in multi-gate Si, SiGe and Ge MOSFETs. New hot carrier phenomena are discussed. The effects of gate misalignment or underlap,as well as the use of the back gate for charge storage in double-gate nanodevices and of capacitorless DRAM are also outlined.     

Status and Trends in Advanced SOI Devices and Materials

提供了一种用于安德鲁反射测量样品制备新方法. 该方法采用聚焦粒子束刻蚀和磁控溅射,可以获得可控的、干净的、无应力的纳米接触用于自旋极化探测. 所制备的样品中,磁性和非磁性材料样品的反射谱都表现出复杂的峰和谷结构,这些结构可能源于与界面相关的零偏压反常以及与激发态相关的准离子相互作用. 对另一个Co40Fe40B20合金样品采用简单的钕针尖压针方法进行了对比性测量,反射谱中没有观察到谷结构,但谱结构出现较明显的热扩展,这种热扩展可能来源于界面处的非弹性输运. 所有的反射谱目前还不能由现有的理论给出令人满意的解释. 利用点接触反射方法获得可靠的自旋极化信息还有赖于接触界面特征的进一步分析. 而一个更切合实际的、更完善的理论成为迫切的需要.     

PDSOI体源连接环形栅nMOS特性研究

提出了一种基于部分耗尽绝缘体上硅的体源连接环形栅nMOS器件,并讨论了相应的工艺技术和工作机理。采用体源连接环形栅器件结构,有效地抑制了浮体环形栅器件中存在的浮体效应和寄生双极晶体管效应,使器件性能得到很大的提高。消除了浮体环形栅器件的反常亚阈值斜率和Kink效应,DIBL从120.7mV/V降低到3.45mV/V,关态击穿电压从4.8V提高到12.1V。最后指出,体源连接环形栅器件非常适合于抗辐照加固等应用领域。     

PDSOI nMOSFETs关态击穿特性

分别采用不同的背栅沟道注入剂量制成了部分耗尽绝缘体上硅浮体和H型栅体接触n型沟道器件.对这些器件的关态击穿特性进行了研究.当背栅沟道注入剂量从1.0×1013增加到1.3×1013cm-2,浮体n型沟道器件关态击穿电压由5.2升高到6.7V,而H型栅体接触n型沟道器件关态击穿电压从11.9降低到9V.通过测量寄生双极晶体管静态增益和漏体pn结击穿电压,对部分耗尽绝缘体上硅浮体和H型栅体接触n型沟道器件的击穿特性进行了定性解释和分析.     

H型栅SOIMOS作为静电保护器件的维持电压的研究(英文)

对绝缘体上硅工艺来说,静电保护可靠性是一个关键且具有挑战性的问题。着重于研究H型栅SOIMOS的维持电压,通过实验发现此器件的维持电压与栅宽紧密联系。结合TCAD仿真解释了器件的工作机理,通过建立集约模型并由HSPICE仿真,揭示了体电阻与维持电压之间的关系。     

Impacts of gate structure on dynamic threshold SOI nMOSFETs

The effects of different substrate-contact structures (T-gate and H-gate) dynamic threshold voltage silicon-on-insulator (SOI) nMOSFETs (DTMOS) have been investigated. It is found that H-gate structure devices have higher driving current than T-gate under DTMOS-mode operation. This is because H-gate SOI devices have larger body effect factor (/spl gamma/), inducing a lager reduction of threshold voltage. Besides, it is found that drain-induced-barrier-lowering (DIBL) is dramatically reduced for both T-gate and H-gate structure devices when devices are operated under DTMOS-mode.     

Flash存储器浮栅单元的总剂量效应统计性分析

针对核设施机电设备中控制系统存储单元耐辐射可靠性评价的需要,以国产NOR型Flash存储器为研究对象,对器件存储阵列浮栅单元的总剂量损伤阈值开展了实验研究。综合利用SMOTE算法和Bootstrap法建立了一种基于极小子样的器件耐辐照可靠性评价方法,对被测样品校验失效剂量进行了统计分析。实验结果表明,器件浮栅单元的主要失效模式为浮栅电荷损失造成的阈值电压降低,平均校验错误剂量为(631.89±103.64)Gy(Si)。统计分析表明,器件总剂量损伤阈值服从对数正态分布。基于SMOTE-Bootstrap的可靠性评价方法避免了传统Bootstrap再生样本过于集中的问题,可应用于极小子样的可靠性评价。     

Investigation of pillar thickness variation effect on oblique rotating implantation (ORI)-based vertical double gate MOSFET

The rapid scaling of integrated circuit requires further shrinkage of lateral device dimension, which correlates with pillar thickness in vertical structure. This paper investigates the effect of pillar thickness variation on vertical double gate MOSFET (VDGM) fabricated using oblique rotating ion implantation (ORI) method. For this purpose, several scenarios of silicon pillar thickness t_si were evaluated for 20–100 nm channel length. The source region was found to merge at pillar thickness below 75 nm, which results in floating body effect and creates isolated region in the middle of pillar. The vertical devices using ORI method show better performance than those with conventional implantation method for all pillar thickness, due to the elimination of corner effect that degrades the gate control. The presence of isolated depletion region in the middle of pillar at floating body increases parasitic effect for higher drain potential. By further reduction of pillar thickness towards fully depleted feature, the increase in gate-to gate charge coupling improves the performance of ORI-based vertical double gate MOSFET, as evident in near-ideal swing value and lower DIBL, compared to the partially depleted and body-tied device.     

浮栅器件栅耦合系数修正的探讨

提取浮栅器件栅耦合率的方法一般都是针对不可忽略的沟道耦合现象进行修正.对这些方法进行了比较、分析发现,对于短沟道浮栅器件,会由于参考器件存在明显的DIBL/SIBL效应,使提取的源、漏耦合系数偏大产生了很大的误差.提出了一种对亚阈值斜率法提取浮栅器件栅耦合系数的修正方法,结合了DIBL/SIBL效应因子,基于亚阈值斜率之比来较简单地实现更精确的近似,得到的栅耦合系数与设计值吻合较好,误差在2%以内,表明此修正法是合理且精确的.     

一种新的部分耗尽SOI器件BTS结构

提出了一种新的部分耗尽SOI体接触技术,与其它体接触技术相比,该方法可以有效抑制SOI器件的浮体效应。形成多晶硅栅之前在源区进行大剂量P＋杂质注入,然后形成非对称源区浅结结构。然后生长硅化物电极,厚的硅化物穿透源区浅结与下面高浓度的体区形成欧姆接触。二维器件模拟表明该结构可以有效降低强反型区体区电势,从而抑制了浮体效应。     

PDSOI nMOSFETs关态击穿特性

分别采用不同的背栅沟道注入剂量制成了部分耗尽绝缘体上硅浮体和H型栅体接触n型沟道器件.对这些器件的关态击穿特性进行了研究.当背栅沟道注入剂量从1.0×1013增加到1.3×1013cm-2,浮体n型沟道器件关态击穿电压由5.2升高到6.7V,而H型栅体接触n型沟道器件关态击穿电压从11.9降低到9V.通过测量寄生双极晶体管静态增益和漏体pn结击穿电压,对部分耗尽绝缘体上硅浮体和H型栅体接触n型沟道器件的击穿特性进行了定性解释和分析.