Evidence of acceptor-like oxide defects created by hot-carrierinjection in n-MOSFET's: a charge-pumping study

Charge-pumping measurements and simulation of charge-pumping characteristics demonstrate that acceptor-like oxide traps (i.e. negatively charged when occupied by an electron and neutral when occupied by a hole) are created in the gate-drain overlap region of an n-MOSFET subjected to hot-electron and/or hot-hole injections (HEI and/or HHI). These traps are located in the gate-drain overlap region, and it is emphasized that the charge-pumping technique is able to detect them in addition to the damages in the channel     

A study of channel avalanche breakdown in scaled n-MOSFET's

The behavior of channel avalanche breakdown in n-MOSFET's miniaturized by isothermal constant field scaling is examined. Both a first-order analytical estimate and a rigorous two-dimensional numerical simulation of electrically wide devices are used to understand the scaling of channel breakdown. A sublinear dependence of snapback and sustaining voltages on channel length is found and explained. In practical terms, this sublinear dependence means that the relative MOS channel breakdown behavior improves for scaled-down devices. The breakdown behavior was verified against experimental data taken on a 1.3-µm n-channel device. In addition, a model is proposed for channel breakdown on unscaled devices that differ only in channel length.     

A theoretical study of gate/Drain offset in LDD MOSFET's

A semi-quantitative model for the lateral channel electric field in LDD MOSFET's has been developed. This model is derived from a quasi-two-dimensional analysis under the assumption of a uniform doping profile. A field reduction factor, indicating the effectiveness of an LDD design in reducing the peak channel field, is used to compared LDD structures with, without, and with partial gate/drain overlap. Plots showing the trade-off between, and the process-dependencies of, the field reduction factor (FRF) and the series resistance are presented for the three cases. Structures with gate/drain overlap are found to provide greater field reduction than those without the overlap for the same series resistance introduced. This should be considered when comparing the double-diffused and spacer LDD structures. It is shown that gate/drain offset can cause the rise of channel field and substrate current at large gate voltages. Good agreement with simulations is obtained.     

A dispersion compensator using coupled defects in a photoniccrystal

We propose a new type of dispersion compensator that uses the characteristics of light traveling in a coupled defect waveguide (CDW) in a photonic crystal. By using a theoretical computation based on the plane-wave method, we show that the CDW band appears within the bandgap and its characteristics are well reproduced by the tight-binding (TB) model. We calculate the wavelength dispersion of light propagating in the CDW using TB formalism. The calculated result shows an inherently large dispersion of the CDW, which enables the realization of an extremely small dispersion compensator of a few tens of millimeters in size     

A comparative study of gate direct tunneling and drain leakagecurrents in n-MOSFET's with sub-2 nm gate oxides

This work examines different components of leakage current in scaled n-MOSFET's with ultrathin gate oxides (1.4-2.0 nm). Both gate direct tunneling and drain leakage currents are studied by theoretical modeling and experiments, and their effects on the drain current are investigated and compared. It concludes that the source and drain extension to the gate overlap regions have strong effects on device performance in terms of gate tunneling and off-state drain currents     

Application of atomic scale STEM techniques to the study of interfaces and defects in materials

Incoherent imaging and analysis techniques in the scanning transmission electron microscope (STEM) provide the potential to map changes in structure, composition and bonding that occur at materials interfaces and defects on the fundamental atomic scale. Such comprehensive characterization capabilities permit a detailed analysis of the structure-property relationships of interfaces and defects to be performed. In this paper, we discuss the resolution limits of such techniques in the JEOL 2010F STEM/TEM operating both under standard conditions and at elevated temperatures. Examples of the use of such techniques to quantify the atomic scale defect chemistry at interfaces and defects in perovskite oxides, the growth and structure of II-VI and III-V quantum dots and the electronic structure of threading dislocations in GaN will also be presented.     

Comparison of neutral electron trap generation by hot-carrierstress in n-MOSFET's with oxide and oxynitride gate dielectrics

A comparative study of neutral electron-trap generation due to hot-carrier stress in n-MOSFETs with pure oxide, NH₃-nitrided oxide (RTN), and reoxidized nitrided oxide (RTN/RTO) as gate dielectrics is reported. Results show that neutral electron trap generation is considerably suppressed by nitridation and reoxidation. The nature of neutral traps is described based on the kinetics of trap filling by electron injection into the gate dielectrics immediately after channel hot-electron stress (CHES). Improved endurance of the RTN and RTN/RTO oxides is explained using physical models related to interfacial strain relaxation     

A comprehensive study of indium implantation-induced damage in deep submicrometer nMOSFET: device characterization and damage assessment

The impact of indium channel implantation on the current-voltage characteristics, gate oxide breakdown and hot-carrier reliability of deep submicrometer nMOSFETs is studied in detail. A significantly faster oxide wear-out during ramped-voltage testing and a distinctly enhanced drain current degradation during hot-carrier stressing are observed in devices with implant dose ranging from 1-2 /spl times/ 10/sup 13/ cm/sup -2/. An important generation leakage is also measured in the long-channel MOSFET, although such irregularity is normally not detected in short-channel devices owing to predominant subthreshold current. The loss in device reliability may be attributed to the generation of local amorphous regions in the channel when the implant dose exceeds 10/sup 13/ cm/sup -2/. The limited thermal budget of the subsequent gate oxidation step is generally unable to anneal out these defects, which in turn lead to the formation of local weak spots and strained Si-H bonds in the gate oxide, and dislocation loops in the channel region. This finding raises an important concern on the use of indium implantation in retrograde channel engineering, since implant doses on the order of 10/sup 13/ cm/sup -2/ are often needed for effective suppression of short-channel effects. In order to minimize the loss in device reliability, the damaged lattice would need to be restored using a dedicated thermal annealing cycle prior to gate oxidation. A good correlation between the hot-carrier stress data and the DC current-voltage (DCIV) measurement data is also presented. This makes the DCIV technique a precise, nondestructive monitor for implantation-induced damage in deep submicrometer MOSFET, via a direct measurement of the process-residue interface traps.     

A preliminary study of SF6 based inductively coupled plasma etching techniques for beta gallium trioxide thin film

Beta phase Gallium trioxide (β-Ga₂O₃) thin film was grown by metal organic chemical vapor deposition technology. Mixture gases of SF₆ and Ar were used for dry etching of β-Ga₂O₃ thin film by inductively coupled plasma (ICP). The effect of SF₆/Ar (etching gas) ratio on etch rate and film etching damage was studied. The etching rate and surface roughness were measured using F20-UN thin film analyzer and atomic force microscopy showing that the etching rate in the range between 30 nm/min and 35 nm/min with an improved surface roughness was obtained when the reactive mixed gas of SF₆/Ar was used. The analysis of X-ray diffraction and transmission spectra further confirmed the non-destructive crystal quality. This work demonstrates that the properly proportioned mixture gases of SF₆/Ar is suitable for the dry etching of β-Ga₂O₃ thin film by ICP and can serve as a guide for future β-Ga₂O₃ device processing.     

A novel charge-pumping method for extracting the lateraldistributions of interface-trap and effective oxide-trapped chargedensities in MOSFET devices

A novel charge-pumping method using dc source/drain biases and specified gate waveforms is proposed to extract the lateral distributions of interface-trap and effective oxide-trapped charge densities. The surface potential redistribution due to the oxide-trapped charges is treated by an iteration process in order to accurately determine their lateral distributions. The proposed novel method is feasible for accurately extracting the distributions of interface-trap and effective oxide-trapped charge densities generated by the hot-carrier stress and can be further used to predict the device lifetime     

A new substrate and gate current phenomenon in short-channel LDD and minimum overlap devices

A new substrate and gate current phenomenon in short-channel LDD and minimum overlap devices has been observed. This phenomenon is well characterized experimentally by studying devices with different gate oxide thickness, spacer width, and n-region doping. A good physical understanding is obtained by using a two-dimensional device simulation program together with experimental data analysis. This effect can be maximized for use as a potential low-voltage EPROM or avoided for reliability reason by properly designing the n-region doping, gate overlap, and oxide spacer width.     

Investigation of voltage-swing effect and trap generation in high-k gate dielectric of MOS devices by charge-pumping measurement

Charge-pumping (CP) techniques with various rise and fall times and with various voltage swings are used to investigate the energy distribution of interface-trap density and the bulk traps. The charge pumped per cycle (Q_cp) as a function of frequency was applied to detect the spatial profile of border traps near the high-k gate dielectric/Si interface and to observe the phenomena of trap migration in the high-k dielectric bulk during constant voltage stress (CVS) sequence. Combining these two techniques, a novel CP technique, which takes into consideration the carrier tunneling, is developed to measure the energy and depth profiles of the border trap in the high-k bulk of MOS devices.     

用于LDD和SST的SiO2边墙干法腐蚀工艺研究

本文从干法腐蚀角度出发,首先从数学上分析了多晶硅角度,SiO_2边墙的宽度和高度,衬底损失与各工艺参数间的关系,指出边墙的宽度和高度分别取决于多晶硅的角度和过腐蚀量。在Tegal1512e设备上,采用Cl_2、SF_6、N_2混合气体,开发了多晶硅干法腐蚀工艺,讨论了LDD的正胶掩膜及SST的SiO_2掩膜对工艺的不同影响。SEM分析发现了SF_6气体腐蚀的各向同性。在Tegal903e设备上,采用CHF_3、SF_6、He混合气体,开发了SiO_2边墙干法腐蚀工艺,研究了腐蚀的各向异性,辐射损伤,选择比,均匀性及重复性的控制方法。取得的工艺结果为,腐蚀速率(?)_(sio_2)≈400nm/min,均匀性U≤±5％,选择比S_(f8)>10,工序能力指数C_p>1。     

A novel floating-gate method for measurement of ultra-low hole and electron gate currents in MOS transistors

A new method for measurement of ultra-low gate currents in MOS transistors is presented. It is based on a novel coupled floating-gate transistor (CFGT) structure, which enables a clear distinction between threshold voltage shifts due to charge accumulated in the floating gate, and shifts due to device degradation. This advantage gives the new method a demonstrated sensitivity of 10^-19A. In addition, with this structure it becomes possible to measure the relation between device degradation and the actual amount of charge injected to the gate. The method is demonstrated by measurements of hole and electron currents in NMOSFET's.     

A new method for characterizing the spatial distributions ofinterface states and oxide-trapped charges in LDD n-MOSFETs

Previous studies showed that simultaneous determination of the interface states (Nit) and oxide-trapped charges (Q_ox) in the vicinity of the drain side in MOS devices was rather difficult. A new technique which allows a consistent characterization of the spatial distributions of both hot-carrier-induced Nit and Q_ox is presented. Submicron LDD n-MOS devices were tested and charge pumping measurements were performed. The spatial distributions of both Nit and Q _ox have been justified by two-dimensional (2-D) device simulation of the I-V characteristics for devices before and after the stress. Comparison of the drain current characteristics between simulation and experiment shows very good agreement. Moreover, results show that fixed-oxide charge effect is less pronounced to the device degradation for the experimental LDD-type n-MOS devices     

Transport of hot charge carriers in Si,GaAs, InGaAs,and GaN submicrometer semiconductor structures with nanometer-scale clusters of radiation-induced defects

The distributions of the radii of subclusters of radiation-induced defects and of the distances between the cores of these subclusters are calculated for Si, GaAs, and GaN. The features of the transport of hot charge carriers in the above materials upon irradiation with neutrons are discussed. A burst in the velocity of electrons in Si, GaAs, InGaAs, and GaN before and after irradiation is calculated for the first time; also, the extent of manifestation of the above effect in different semiconductor materials is compared.     

A study of void defects in metalorganic molecular-beam epitaxy grown HgCdTe

Void defects that occur under Hg deficient conditions during the metalorganic molecular beam epitaxy (MOMBE) growth of HgCdTe have been characterized using secondary electron microscopy (SEM) and energy dispersion spectrometry (EDS) mapping as well as by EDS quantitative analysis. For a set of HgCdTe samples grown under a range of Hg fluxes, it was found that the surface morphology had a significant dependence on the Hg flux. An optimum growth window defined by a narrow range of Hg fluxes was identified in which there exists a smooth surface with few voids, whereas at either side of the Hg window surfaces were rough. This surface morphology correlated very well with a minimum in the x-ray line widths and maximum hole concentration and mobility values. This correlation is important for the growth of HgCdTe materials and subsequent device fabrication. Several types of void morphologies have been observed with different correlation to Te and Hg. It was found that there is a pronounced Te enrichment and Hg deficiency associated with most of the developed voids, as compared to the composition of the HgCdTe films. It was also found that most of the voids originated within the HgCdTe film. A mechanism for void formation and growth is proposed. In addition, it was found that annealing caused the voids to separate from the HgCdTe film.     

A survey and comparative study of QoS aware broadcasting techniques in VANET

Mobile operators currently encounter numerous challenges caused by the centralized architecture of mobile networks. A single mobility anchor placed at the network core maintains the entire mobility and data traffic forwarding in the existing centralized mobility management (CMM) solutions. The CMM approach confronts several issues in scalability, reliability, signaling overhead, and non-optimal routing due to the increasing number of mobile devices and the volume of data traffic. To overcome these issues, a new architectural paradigm called distributed mobility management (DMM) is proposed to flatten the network architecture by moving mobility anchors closer to users and separating the control and data planes at the network edge. Two DMM solutions are developed: partially distributed mobility management (partial-DMM) in which only the data plane is distributed and fully distributed mobility management (full-DMM) where both control and data planes are distributed, which can be potentially applied for future mobile networks. This paper presents a network-based full-DMM scheme that was developed and implemented using NS2 network simulator by removing any dedicated centralized mobility anchor from the architecture. Extensive simulations were conducted to evaluate and compare the performance of the full-DMM model with that of the traditional CMM model. The simulation results show that the full-DMM provides lower end-to-end delay performance than CMM. However, the full-DMM generates higher handover latency and packet loss than CMM at high MN speeds. Moreover, simulation results clearly show the benefits of dynamic mobility activation in the full-DMM model.     

A unified approach to profiling the lateral distributions of bothoxide charge and interface states in n-MOSFET's under various biasstress conditions

A new and accurate technique that allows the simultaneous determination of the spatial distributions of both interface states (N _it) and oxide charge (Q_ox) will be presented. The gated-diode current measurement in combination with the gate-induced drain leakage (GIDL) current were performed to monitor the generation of both N_it and Q_ox in n-MOSFET's. A special detrapping technique and simple calculations have been developed, from which the spatial distributions of both N_it and Q_ox under various bias stress conditions, such as the hot-electron stress (I_G,max), I_B,max, and hot-hole stresses, can be determined. The calculation of gated-diode current by incorporating the extracted profiles of N_it and Q_ox has been justified from numerical simulation. Results show very good agreement with the experimental results. The extracted interface damages for hot-electron and hot-hole stresses have very important applications for the study of hot-carrier reliability issues, in particular, on the design of flash EPROM, E²PROM cells since the above stress conditions, such as the I_G,max and hot-hole stress, are the major operating conditions for device programming and erasing, respectively     

A study of the transport of charge carriers in coupled quantum regions

Specific features of controlled relocation of charge carriers in nanostructures based on tunnelingcoupled quantum regions formed by GaAs/AlGaAs heterojunctions are considered. The results of numerical simulation of dynamics of controlled tunneling relocation of the maximum in the amplitudes of wave functions of charge carriers are discussed.