基于中间硅片厚度可控的三层阳极键合技术

三层键合Glass-Silicon-Glass(GSG)结构在光MEMS、微惯性器件、微流体芯片、射频MEMS以及低成本圆片级封装技术领域里是一项重要技术.基于MEMS精密研磨抛光工艺和阳极键合,结合新型玻璃通孔的腐蚀工艺,开展了中间硅片厚度可控的三层阳极键合工艺研究,成功制备了带有通孔的GSG微流体器件.总厚度1360μm,中间硅片厚度60μm,通孔直径100μm,孔间距(圆孔的中心距离)200μm,孔内边缘圆滑无侧蚀.三层结构的键合几率为90%,为探索多层键合技术打下坚实基础.     

基于粘附剂键合的圆片级MEMS塑料封装技术

设计了一套采用聚合物粘附剂(Epo-Tek301)键合的圆片级MEMS塑料(polymethyl methac- rylate)封装方法.塑料封装封盖采用热压成型,激光划片形成4寸圆片.封盖和衬底键合工艺的粘附剂优化厚度为12μm,键合过程中不需要加压加温.测试结果显示该工艺的键合强度(1.3～1.6Mpa)可以满足一般封装需要,而所带入的应力也很小.划片采用分开划片:封盖采用激光划片而硅衬底采用机械划片.该方法封装的微流体芯片已经顺利测试和应用.由于工艺简单,成本低廉,该技术除了用于MEMS封装应用,也可作为划片测试保护.     

金-硅共晶键合技术及其应用

采用金属过渡层来实现硅-硅低温键合,首先介绍了选择钛金作为金属过渡层的原因和金硅共晶键合的基本原理,然后探索了不同键合面积和不同金层厚度对金硅共晶键合质量的影响规律,开展了图形化的硅晶圆和硅盖板之间的低温共晶键合实验研究,获取了最优键合面积的阈值和最优金层厚度.最后将该低温金硅共晶键合技术应用到MEMS器件圆片级封装实验中,实验结果表明较好地实现了MEMS惯性器件的封装强度,但是还存在密封性差的缺陷,需进一步进行实验改进.     

Pyrex7740玻璃通孔湿法腐蚀技术研究

本文研究报道了Pyrex7740玻璃湿法腐蚀通孔技术.将四寸硅玻璃键合圆片的玻璃衬底减薄,并在玻璃上分别制备PECVD SiC、W/Au和PECVD多晶硅三种不同掩膜及其开口,最终利用40％ HF腐蚀实现玻璃通孔.整个工艺过程与IC工艺兼容,并可进行圆片级批量加工.观察并研究纵向和横向腐蚀过程和通孔形貌,对比三种不同腐...     

低温非晶硅/金圆片键合技术(英文)

本文研究了低温非晶硅/金圆片键合技术.具有不同金硅比的键合片在400℃键合温度和1 MPa键合压力下维持30 min,其键合成功区域均高于94%,平均剪切强度均大于10.1 MPa.键合强度测试结果表明键合成品率与金硅比大小无关,平均剪切强度在10～20 MPa范围内.微观结构分析表明键合后单晶硅颗粒随机分布在键合层内,而金则充满其他区域,形成了一个无空洞的键合层.无空洞键合层确保不同金硅比非晶硅/金键合片均具有较高的键合强度,可实现非晶硅/金键合技术在圆片键合领域的应用.     

采用精密印刷技术的玻璃浆料圆片级气密封装

采用先进的丝网印刷设备和精密印刷技术,对MEMS器件玻璃浆料气密封装技术,包括丝网印刷、预烧结和键合工艺等进行了深入研究。采用三种不同线宽的丝网板对二次印刷工艺进行了优化,提高了玻璃浆料的平整度和均匀性。经烧结键合后的封装体具有较高的封接强度(剪切力12kg)及良好的气密性(氦气精检合格率100%),可实现高质量的圆片级气密封装。     

MEMS加速度计三维堆叠模块化封装及垂直互连

传感器系统微小型化的发展趋势是将各功能模块进行三维模块化集成.本研究将加速度计芯片及调制解调电路进行三层堆叠模块集成.其中,各层模块的组装采用了FR4基板上的COB工艺,而垂直互连采用了一种新型的垂直定位装置进行定位和回流焊,实现了加速度计和调制解调电路的三维堆叠模块化封装结构.该结构成功把MEMS器件与IC芯片混合集成在同一模块里;采用了一种新的定位销/孔的定位方式,可同时进行3×3个模块的高精度堆叠定位(其对位误差约0.068mm);通过丝网印刷焊膏,一次回流焊接完成堆叠模块的垂直互连,互连强度高(单个焊点平均强度为30～40MPa);封装体积小(整个加速度计调制解调系统封装后的体积为19×19×8mm3).还讨论了垂直互连的影响因素.对模块进行的剪切力测试表明采用印刷焊膏回流实现垂直互连的强度满足相关标准.     

晶圆级集成技术研究进展

随着物联网时代的来临，传统的传感器芯片与存算芯片相分离的架构已难以满足实际场景的需求。3D集成技术能够缩短传感器芯片与存算芯片间的物理距离，实现功能扩展，提升系统能效。晶圆级集成由于对准精度高和互连密度大，一直是学界和产业界的研究热点。文章对晶圆级集成技术中的两种主流工艺，包括硅通孔和混合键合工艺，进行了系统性介绍；并结合国内外多个研究机构的最新进展，对其发展方向进行了展望，以实现适用于感存算一体化芯片的晶圆级集成工艺。     

基于Sn/Bi合金的低温气密性封装工艺研究

研究了采用Sn/Bi合金作为中间层的键合封装技术.通过电镀的方法在基片上形成Cr/Ni/Cu/Sn、芯片上形成Cr/Ni/Cu/Bi多金属层,在513K、150Pa的真空环境中进行共晶键合,键合过程不需使用助焊剂,避免了助焊剂对微器件的污染.实验表明:这种键合工艺具有较好的气密性,键合区合金层分布均匀,无缝隙、气泡等缺陷,键合强度较高,能够满足电子元器件和微机电系统(MEMS)可动部件低温气密性封装的要求.     

硅玻璃阳极键合绝压压阻式压力传感器中的残余应力

硅玻璃阳极键合技术因键合强度高,工艺简单而成为低成本绝压压力传感器的主要封装技术.但由于常规的硅玻璃阳极键合需要在相对较高的温度下进行且材料之间不可避免的热膨胀系数失配将产生较大的残余应力.实验采用有限元方法对硅玻璃阳极键合进行了系统的力学分析以减小残余应力对器件性能的影响.实验中采用硅玻璃阳极键合技术制备了不同压敏膜厚度和尺寸的传感器并测试其曲率与零点以对残余应力进行分析验证.     

玻璃浆料低温气密封装MEMS器件研究

系统地研究了玻璃浆料在低温下气密封装MEMS器件的过程。采用该工艺（预烧结温度400℃,烧结温度500℃,外加压强3kPa）形成的封装结构具有较高的封接强度（剪切力〉15kg）及良好的气密性（气密检测合格率达到85％）,测得的漏率符合相关标准。     

Fabrication of nano-scale Cu bond pads with seal design in 3D integration applications

A method to fabricate nano-scale Cu bond pads for improving bonding quality in 3D integration applications is reported. The effect of Cu bonding quality on inter-level via structural reliability for 3D integration applications is investigated. We developed a Cu nano-scale-height bond pad structure and fabrication process for improved bonding quality by recessing oxides using a combination of SiO2 CMP process and dilute HF wet etching. In addition, in order to achieve improved wafer-level bonding, we introduced a seal design concept that prevents corrosion and provides extra mechanical support. Demonstrations of these concepts and processes provide the feasibility of reliable nano-scale 3D integration applications.     

A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices

We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging.     

阳极键合研究现状及影响因素

为了提高键合质量、优化键合材料,促进阳极键合技术在工业生产中的应用,本文以“硅/玻璃”的阳极键合为例,阐述了阳极键合作为新型连接工艺的键合机理及工艺过程,介绍了现阶段阳极键合在国内外工业生产中的应用实例及相关研究,尤其是在微电子封装领域所展现的杰出应用前景,同时结合阳极键合过程中对键合参数、材料处理等要求,给出了影响键合质量的各种因素,以及在键合过程中常出现的问题及其解决办法.本文立足于键合机理及键合工艺过程,结合不同材料特性,重点阐述了阳极键合这一新型连接工艺的国内外研究现状及影响键合的因素,为进一步提高键合质量、优化键合工艺、开发新的键合材料等提供理论依据.     

Photoelectrochemical etching to fabricate single-crystal SiC MEMS for harsh environments

In this paper, we report on a novel surface micromachining process technology for the fabrication of microelectromechanical systems in SiC. Single-crystal SiC suspended microstructures were fabricated using a dopant-selective photoelectrochemical etching process, which allows for undercutting the p-SiC layer by rapid lateral etching of the underlying n-SiC substrate. The selective etching was achieved by applying a bias which employs the different flat-band potentials of n-SiC and p-SiC in the KOH solution. Single-crystal SiC MEMS developed in this study fully exploits the superior mechanical and biocompatible properties of SiC and has the capability of monolithic integration with electron devices and circuits, and therefore, is promising for sensing and actuating operations in biomedical, high-temperature and harsh environments.     

High-aspect-ratio bulk micromachining of titanium

Recent process developments have permitted the highly anisotropic bulk micromachining of titanium microelectromechanical systems (MEMS). By using the metal anisotropic reactive ion etching with oxidation (MARIO) process, arbitrarily high-aspect-ratio structures with straight sidewalls and micrometre-scale features have been bulk micromachined into titanium substrates of various thicknesses, ranging from 0.5-mm sheet down to 10-microm free-standing titanium foils. Bulk micromachined structures are generally free of residual stresses and are preferred when large, rigid, flat and/or high-force actuators are desired. However, so far there has been a limited ability to select materials on the basis of specific application in bulk micromachining, primarily because of the predominance of MEMS processes dedicated to single-crystal silicon, such as silicon deep reactive ion etching. The MARIO process permits the creation of bulk titanium MEMS, which offers potential for the use of a set of material properties beyond those provided by traditional semiconductor-based MEMS. Consequently, the MARIO process enables the fabrication of novel devices that capitalize on these assets to yield enhanced functionalities that would not be possible with traditional micromechanical material systems.     

Progress in Microelectromechanical Systems

Abstract:  Recent advances in microelectromechanical systems (MEMS) technology have led to the development of a multitude of new devices heretofore impossible. However, applications of these devices are still hampered by challenges posed by their integration and packaging. The current trend in micro/nanosystems is to produce ever smaller, lighter and more capable devices at a lower cost than ever before. In addition, the finished products have to operate at very low power and in very adverse conditions while ensuring durable and reliable performance. Some of the new devices have been developed to function at high operational speeds, and others to make accurate measurements of operating conditions of specific processes. Regardless of their applications, the devices have to be packaged to facilitate their use. MEMS packaging, however, is application-specific and, usually, has to be developed on a case-by-case basis. To facilitate advances of MEMS, educational programmes have been introduced addressing all aspects in their development. This paper addresses progress in MEMS by presenting pertinent aspects in a development of MEMS including, but not limited to, design, analysis, fabrication, characterisation, packaging, and testing. This presentation is illustrated with selected examples.     

用于微电子机械系统封装的体硅键合技术和薄膜密封技术

对静电键合、体硅直接键合和界面层辅助键合等三种体硅键合技术，整片操作、局部操作和选择保护等三种密封技术，以及这些技术用于微电子机械系统的密封作了评述，强调在器件研究开始时应考虑封装问题，具体技术则应在保证器件功能和尽量减少芯片复杂性两者之间权衡决定。     

玻璃与铝在不同层数结构下的阳极键合界面力学性能

运用共阳极法实现不同层数玻璃／铝的阳极键合,采用MARC非线性有限元分析软件,对三层、五层、七层、九层玻璃／铝键合试件的界面力学性能进行比较分析,探讨结合处残余应力随层数增加的变化趋势,分析结果表明,由于多层结构的对称性,最大的等效应力发生在中心处的过渡层。研究结果为MEMS器件在多层封装结构的设计提供了理论依据。     

A systematic study of DRIE process for high aspect ratio microstructuring

Various MEMS devices like Accelerometers, Resonators, RF- Filters, Micropumps, Microvalves, Microdispensers and Microthrusters are produced by removing the bulk of the substrate materials. Fabrications of such Microsystems requires the ability to engineer precise three-dimensional structures in the silicon substrate. Fabrication of MEMS faces multiple technological challenges before it can become a commercially viable technology. One key fabrication process required is the deep silicon etching for forming high aspect ratio structures. There is an increasing interest in the use of dry plasma etching for this application because of its anisotropic etching behavior, high etch speed, good uniformity and profile control, high aspect ratio capabilities without having any undesired secondary effects i.e. RIE lags, Loading, microloading, loosing of anisotropic nature of etching as aspect ratio increases, micro-grass and even etch stalling. Developing a DRIE micro-machining process requires a thorough understanding of all plasma parameters, which can affect a silicon etching process and their use to suppress the secondary effects. In this paper our intention is to investigate the influence of etching gas flow, etching gas pressure, passivation gas pressure, ICP coil power, Platen power and etch and passivation time sequence on etch rate and side wall profile. Parameter ramping is a powerful technique used to achieve the requirements of high aspect ratio microstructures (HARMS) for MEMS applications by having high etch rate with good profile/CD control. The results presented here can be used to rationally vary processing parameters in order to meet the microstructural requirements for a particular application.