The effect of patterns on thermal stress during rapid thermalprocessing of silicon wafers

The presence of patterns can lead to temperature nonuniformity and undesirable levels of thermal stress in silicon wafers during rapid thermal processing (RTP). Plastic deformation of the wafer can lead to production problems such as photolithography overlay errors and degraded device performance. In this work, the transient temperature fields in patterned wafers are simulated using a detailed finite-element-based reactor transport model coupled with a thin film optics model for predicting the effect of patterns on the wafer radiative properties. The temperature distributions are then used to predict the stress fields in the wafer and the onset of plastic deformation. Results show that pattern-induced temperature nonuniformity can cause plastic deformation during RTP, and that the problem is exacerbated by single-side heating, increased processing temperature, and increased ramp rate. Pattern effects can be mitigated by stepping the die pattern out to the edge of the wafer or by altering the thin film stack on the wafer periphery to make the radiative properties across the wafer more uniform     

Wafer temperature measurement in a rapid thermal processor with modulated lamp power

Pyrometry methods utilizing modulated lamp power (“ripple”) were used to improve wafer temperature measurement and control in rapid thermal processing (RTP) for silicon integrated circuit production. Data from a manufacturing line where ripple pyrometers have been tested show significantly reduced wafer to wafer and lot to lot variations in final test electrical measurements and increased yields of good chips per wafer. The pyrometers, an outgrowth of Accufiber’s ripple technique, are used to compensate for ordinary production variations in the emissivities of the backsides of wafers, which face the pyrometers. Power to the heating lamps is modulated with oscillatory functions of time at either the power line frequency or under software control. Fluctuating and quasi-steady components in detected radiation are analyzed to suppress background reflections from the lamps and to correct for effective wafer emissivity. Sheet resistances of annealed wafers with high dose shallow As implants were used to infer temperature measurement capability over a range in backside emissivity. Emissivities are varied when depositing or growing one or more layers of silicon dioxide, silicon nitride, or polycrystalline silicon on the backsides of the wafers.     

Rapid thermal processing of silicon wafers with emissivity patterns

Fabrication of devices and circuits on silicon wafers creates patterns in optical properties, particularly the thermal emissivity and absorptivity, that lead to temperature nonuniformity during rapid thermal processing (RTP) by infrared heating methods. The work reported in this paper compares the effect of emissivity test patterns on wafers heated by two RTP methods: (1) a steadystate furnace or (2) arrays of incandescent lamps. Method I was found to yield reduced temperature variability, attributable to smaller temperature differences between the wafer and heat source. The temperature was determined by monitoring test processes involving either the device side or the reverse side of the wafer. These include electrical activiation of implanted dopants after rapid thermal annealing (RTA) or growth of oxide films by rapid thermal oxidation (RTO). Temperature variation data are compared with a model of radiant heating of patterned wafers in RTP systems.     

The effect of patterned susceptor on the thickness uniformity ofrapid thermal oxides

A temperature compensation concept suitable for rapid thermal processing (RTP) with a nonuniform wafer temperature distribution is proposed in this work. Concentric Si rings with different diameters are placed on planar quartz or Si susceptors and are regarded as patterned susceptors for temperature compensation. We put monitor wafers on the patterned susceptor and see the effect of the patterned susceptor on the oxide thickness uniformity of the monitor wafers. The Si rings work as radiation barriers when placed on the quartz susceptor, but as heat conduction media when placed on the Si susceptor. By properly arranging the Si rings on the planar susceptors, the monitor wafers' oxide thickness uniformity can be improved     

硅片背面软损伤工艺技术研究

硅中的金属离子杂质会明显降低少子寿命,并进一步影响硅器件的性能。因此对硅片背面喷砂工艺进行了系统的研究。通过喷砂工艺,在硅片背面形成软损伤层,使硅片具有了吸杂能力,并从吸杂机理出发,解决了吸杂工艺带来的硅抛光片表面颗粒效应,并对硅抛光片的吸杂效果及表面颗粒度进行了表征,为具有吸杂性能的“开盒即用”硅抛光片的批量化生产提供了有力的技术保证。     

Manufacturability issues related to transient thermal annealing oftitanium silicide films in a rapid thermal processor

Transient thermal annealing of sputtered titanium films in a rapid thermal processor (RTP) is critically evaluated from the viewpoint of manufacturability-related considerations. In particular, the thin-film properties of the resulting titanium silicide on polysilicon and silicon, process uniformity, and unit step wafer yield of high-density scaled device structures are investigated. The experimental results suggest that RTP silicides show good thin-film properties for manufacturability on planar wafer surfaces. Transient thermal gradients in an RTP system are shown to cause substantial variations in the electrical and structural properties of TiSi_x films formed on silicon substrates with varying substrate thicknesses. Closed-loop temperature control in an RTP reactor provided stoichiometrically identical TiSi_x films with negligible substrate thickness dependence. The experimental results also suggest that careful wafer surface temperature control is needed when forming titanium silicide films on nonplanar silicon surfaces, silicon trenches, and process monitor wafers without predetermined wafer thicknesses     

A model for rapid thermal processing: achieving uniformity throughlamp control

A first-principles approach to the modeling of a rapid thermal processing (RTP) system to obtain temperature uniformity is described. RTP systems are single wafer and typically have a bank of heating lamps which can be individually controlled. Temperature uniformity across a wafer is difficult to obtain in RTP systems. A temperature gradient exists outward from the center of the wafer due to cooling for a uniform heat flux density on the surface of the wafer from the lamps. Experiments have shown that the nonuniform temperature of a wafer in an RTP system can be counteracted by adjusting the relative power of the individual lamps, which alters the heat flux density at the wafer. The model is composed of two components. The first predicts a wafer's temperature profile given the individual lamp powers. The second determines the relative lamp power necessary to achieve uniform temperature everywhere but at the outermost edge of the wafer (cooling at the edge is always present). The model has been verified experimentally by rapid thermal chemical vapor deposition of polycrystalline silicon with a prototype LEISK RTP system. The wafer temperature profile is inferred from the poly-Si thickness. Results showed a temperature uniformity of ±1%, an average absolute temperature variation of 5.5°C, and a worst-case absolute temperature variation of 6.5°C for several wafers processed at different temperatures     

Thermal and stress analysis of semiconductor wafers in a rapidthermal processing oven

Results are presented from studies of heat transfer in a rapid thermal processing (RTP)-type oven used for several semiconductor wafer processes. These processes include: (1) rapid thermal annealing; (2) thermal gradient zone melting; and (3) lateral epitaxial growth over oxide. The heat transfer studies include the measurement of convective heat transfer in a similar apparatus, and the development of a numerical model that incorporates radiative and convective heat transfer. Thermal stresses that are induced in silicon wafers are calculated and compared to the yield stress of silicon at the appropriate temperature and strain rate. Some methods for improving the temperature uniformity and reducing thermal stresses in the wafers are discussed     

Effect of surface roughness on the temperature of a silicon wafer heated by incoherent radiation

The effect of surface roughness of a silicon wafer on its temperature on heating by incoherent radiation is studied. The temperature-time diagrams of heating and cooling are obtained experimentally for double-side- and single-side-polished wafers at different arrangements of the rough surface with respect to the radiation source. The steady-state temperatures of such wafers under identical conditions of heating from 100 to 250°C are compared. It is established that the highest steady-state temperatures are common to the wafers presenting their rough side to the radiation source, the lowest steady-state temperatures to the double-side- polished wafers, and the intermediate temperatures to the wafers presenting their polished side to the radiation source. An optical model of the rough surface is suggested. In this model, the rough surface is represented by a negligibly thin damaged layer characterized by its own optical parameters. In the model, an optical parameter is introduced to characterize the degree of roughness of the illuminated surface. The dependence of the absorptivity of the wafer on this parameter and on the arrangement of the rough surface with respect to the radiation source is treated theoretically. The model provides a qualitative interpretation of the experimental data.     

Fracture strength characterization and failure analysis of silicon dies

This paper characterizes fracture strength of a silicon die as a first step to predict and prevent die cracking during package assembly, reliability tests, and operation life. Die strength is measured via the three-point bend test conducted using a micro-force tester. Strength reduction due to surface defects, such as tiny notches or micro-cracks that are introduced through wafer backside grinding is evaluated. It is observed that die strength strongly depends on the grinding patterns, i.e. minimum die strength in a wafer is found if the grinding mark is in parallel with the loading axis. Furthermore, fracture strength of dies with different wafer surface conditions like polishing and no treatment (grinding) are also examined. Polished wafers possess the highest silicon strength owing to its minimum surface flaws. On the other hand, untreated wafers contain the most severe surface defects; hence exhibit the lowest die strength. Geometrical factors (square vs. rectangular) and die thickness (4 vs. 6 mils) are probed as well, however these factors do not contribute to die strength degradation. Surface morphology and roughness studies of silicon dies via scanning electron microscope and atomic force microscope also confirmed that die strength degradation is mainly controlled by surface defect (roughness) levels. Observed fracture modes also correlate well with measured die strength.     

Full Field Temperature Measurement of Specular Wafers During Rapid Thermal Processing

Many of the processes involved in the creation of semiconductor devices involve high-temperature processing of silicon wafers. The benefits of reduced thermal budget and faster cycle time make rapid thermal processing (RTP) a possible key technology for semiconductor manufacturing. However, the problem of nonuniform wafer temperature has prevented it from further spread among the industry. The first step in developing controls to maintain a uniform wafer temperature is accurate temperature measurement during processing. In this paper, a system was developed to exploit the specular reflectivity of silicon wafers and obtain a measurement of the wafer temperature profile. The spectral reflectivity is determined by measuring the intensity of an incident beam and the beam reflected from the wafer surface. With this measured reflectivity value the spectral-directional wafer emissivity was determined using Kirchhoff's law. The obtained emissivity then was used to calculate the wafer temperature profile from an image obtained with an infrared camera. An experimental study of the transmittance of an undoped silicon calibration wafer at an elevated temperature is also discussed     

Semi-Empirical Model-Based Multivariable Iterative Learning Control of an RTP System

Comprehensive study on control system design for a rapid thermal processing (RTP) equipment has been conducted with the purpose to obtain maximum temperature uniformity across the wafer surface, while precisely tracking a given reference trajectory. The study covers from model development, identification, optimum multivariable iterative learning control (ILC), to reduced-order controller design. The highlight of the study is the ILC technique on the basis of a semi-empirical dynamic radiation model named as$T^4$-model. It was shown that the$T^4$-model-based ILC technique can remarkably improve the performance of RTP control compared with the ordinary linear model-based ILC. In addition, reduced-order control methods and the associated optimum sensor location have been addressed. The proposed techniques have been evaluated in an RTP equipment fabricating 8-in wafers.     

Photoresist deposition without spinning

A technique for resist deposition using a novel fluid ejection method is presented in this paper. An ejector has been developed to deposit photoresist on silicon wafers without spinning. Drop-on-demand coating of the wafer reduces waste and the cost of coating wafers. Shipley 1400-21, 1400-27, 1805, and 1813 resists were used to coat sample 3- and 4-in wafers. Later, these wafers were exposed and developed. The deposited resist film was 3.5 /spl mu/m thick and had a surface roughness of about 0.2 /spl mu/m. The ultimate goal is to deposit resist films with a thickness of the order of 0.5 /spl mu/m and a surface roughness of the order of 30 /spl Aring/, which is currently achieved for 200-mm silicon wafers by using a spinning method. Such goals can be attained by using micromachined multiple ejectors or with better control over the deposition environment. In the micromachined configuration, thousands of ejectors are made into a silicon die, as presented by Percin et al. (2002), and thus allow for a full coating of a wafer in a few seconds. Coating in a clean environment will allow the lithography of circuits for microelectronic applications. Other potential applications for the technology in the semiconductor manufacturing are in deposition of low-k materials, wafer cleaning, manufacturing of organic LEDs and organic FETs, direct lithography, nanolithography, and coating for hard-disk drives.     

InSb晶片清洗研究

随着红外探测器件制备工艺的不断发展,人们对InSb晶片表面质量的要求也越来越高,但是晶片在生产过程中不可避免地会引进各种杂质。研究了一种利用兆声超声并结合药液去离子水清洗InSb晶片的方法,并对清洗后的InSb晶片进行了表面颗粒度、表面有机物和表面粗糙度等方面的测量。实验结果表明,该方法能够有效去除InSb晶片表面的颗粒、有机物和金属离子杂质,但是也会略微增大晶片表面的粗糙度。     

Transient thermal behavior in a new RTP chamber

The transient thermal behavior of 200 and 300 mm wafers in a new rapid thermal processing (RTP) chamber is investigated. The AST3000 is a new RTP tool to meet the process requirements for both wafer sizes in 0.18 μm technologies and beyond. In this paper, experimental results obtained on both 200 and 300 mm wafers for varying processing conditions are shown: spike anneal experiments with fast ramp rates up to 200°C/s were performed. For standard anneal recipes, the steady state time is varied in a broad range and also the inherent temperature uniformity is investigated.     

清洗工艺对锗外延片表面点状缺陷的影响

锗外延片表面的雾、水印及点状缺陷等会影响太阳电池的性能和成品率,其中点状缺陷出现的比例最高。研究了锗抛光片清洗工艺对外延片表面点状缺陷的影响,获得了无点状缺陷、低粗糙度及高表面质量的锗单晶片。采用厚度为175μm p型<100>锗单面抛光片进行清洗试验,研究了SC-1溶液的不同清洗时间、清洗温度和去离子水冲洗温度对锗抛光片外延后点状缺陷的影响,分析了表面SiO_2残留和锗片表面粗糙度对外延片表面点状缺陷的影响。结果表明点状缺陷主要是由于锗单晶抛光片表面沾污没有彻底清洗干净以及清洗过程中产生新的缺陷造成的。采用氢氟酸溶液浸泡、SC-1溶液低温短时间清洗结合低温去离子水冲洗后的锗抛光片进行外延,用其制备的太阳电池光电转换效率由原来的25%提高到31%。     

InSb晶片化学抛光研究

机械抛光会给InSb晶片表面造成一定程度的机械损伤,增加表面的粗糙度,从而影响器件的性能.化学抛光可以有效地去除表面划痕,改善晶片的表面形貌,降低粗糙度.用低浓度的澳一甲醇溶液对机械抛光后的InSb晶片进行了化学抛光,并对化学抛光前后的InSb晶片进行了表面形貌、总厚度偏差(TTV),粗糙度、表面组分和杂质对比分析.实验结果表明,用低浓度的溴-甲醇溶液对InSb晶片进行化学抛光,腐蚀速率平稳且容易控制,能有效去除表面划痕,从而得到光滑、平坦的表面.晶片表面的粗糙度为6.443nm,TTV为3.4μm,In/Sb原子比接近1.与传统的腐蚀液CP4-A,CP4-B相比,用低浓度的溴-甲醇溶液对InSb晶片进行化学抛光,可以获得更低的表面粗糙度和TTV,且In/Sb的原子比更接近于1.     

Thinned wafer multi-stack 3DI technology

Wafer scale 3DI technology, so-called wafer-on-a-wafer (WOW), characterized by thinned-wafer stacking and Cu multi-level interconnects, has been developed, and revealed that seven-level multi-wafer stacking is possible. The WOW process differs from the chip-on-a-chip and chip-on-a-wafer processes and can be used for wafer-scale bulk processes, enabling manufacturing from transistor to 3D stacking using wafers. Wafers are thinned down to 20-μm and bonded to the base wafer following back-to-face stacking. Through-silicon-via (TSV) holes with a diameter of 30 μm are formed and etched-off until the lower electrode of Au which is patterned on the underneath wafer. Titanium (Ti) and titanium-nitride (TiN) are formed on a TSV hole as a barrier metal and electrode for the electrochemically plated Cu (ECP-Cu). After ECP-Cu deposition, surface planarization is performed using Surface Planer™. Those wafers are used as a base wafer and multi-stacking is carried out repeatedly. The vertical connection between Cu of TSV and Au is therefore connected with a self-aligned contact and without a bump electrode. The electrical properties of the 242-chain contacts within the wafer were measured and no open failure was found. Adopting the thinned substrates eliminates deep silicon etching, and TSV filling which take a long process time, and reduces the residual stress on the Cu plug. Wafers can be stacked as much as possible in accordance with the degree of integration, and this is expected to be a low-cost and high-integration technology for post-scaling.     

Temperature uniformity in RTP furnaces

The heat transfer to a wafer in a rapid thermal processing (RTP) furnace is simulated by an analytical/numerical model. The model includes radiation heat transfer to the wafer from the lamps, heat conduction within the wafer, and emission of radiation from the wafer. Geometric optics are used to predict the radiant heat flux distribution over the wafer. The predicted wafer surface temperature distribution is compared to measurements made in an RTP furnace for two different reflector geometries. Lamp configurations and the resulting irradiance required to produce a uniform wafer temperature are defined