High reliability in PHEMT MMICs with dual-etch-stop AlAs layers for high-speed RF switch applications

We have conducted a thorough investigation on the long-term process reliability for our recently developed dual-etch-stop (DES) pseudomorphic high electron mobility transistor (PHEMT) process using the on-wafer-level accelerated DC and RF biased step stress test up to 320 °C channel temperature as well as package-level three-temperature constant stress lifetest. Devices studied are 0.9-μm-gate InGaAs PHEMTs with two silicon-doped AlAs layers as gate and channel etch-stop materials. High-temperature-operating-life (HTOL) test on our single-pole-double-throw (SPDT) switch products using this DES PHEMT process has also been performed. This article describes the detailed reliability experiments and compares the reliability results of this new DES PHEMT process against the standard non-etch-stop (NES) PHEMT baseline material. Extensive statistical analyses on the DES PHEMT devices derived an activation energy E_a=1.4 eV and a mean-time-to-failure (MTTF) > 10⁷ h at 125 °C, an order of magnitude better than our baseline NES PHEMTs. This study demonstrates and discusses the excellent reliability in the DES PHEMT process for wireless communications applications.     

High temperature transport kinetics in heteroepitaxial LaFeO3 thin films

Heteroepitaxial LaFeO₃(1 1 0) thin films with a thickness of 150 nm were grown on LaAlO₃(0 0 1) by reactive sputtering in an inverted cylindrical magnetron geometry. Equilibrium conductivity was measured as a function of partial pressure of oxygen at T=1000 °C, and logσ plotted vs. logP(O₂) showed a minimum in conductivity for P(O₂)=10⁻¹¹ atm and a linear response between 10⁻¹⁰ and 1 atm. This linear response makes thin films of LaFeO₃ a promising material for oxygen sensor applications. We have also measured the time response of the film conductivity upon an abrupt change in the partial pressure of ambient oxygen from 10⁻² to 10⁻³ atm, which was determined at 60 s for T=700 °C and <3.5 s at T=1000 °C.     

Effects of bonding temperature on the properties and reliabilities of anisotropic conductive films (ACFs) for flip chip on organic substrate application

The effects of bonding temperatures on the composite properties and reliability performances of anisotropic conductive films (ACFs) for flip chip on organic substrates assemblies were studied. As the bonding temperature decreased, the composite properties of ACF, such as water absorption, glass transition temperature (T_g), elastic modulus (E′) and coefficient of thermal expansion (α), were improved. These results were due to the difference in network structures of cured ACFs which were fully cured at different temperatures. From small angle X-ray scattering (SAXS) test result, ACFs cured at lower temperature, had denser network structures. The reliability performances of flip chip on organic substrate assemblies using ACFs were also investigated as a function of bonding temperatures. The results in thermal cycling test (−55 °C/+150 °C, 1000 cycles) and PCT (121 °C, 100% RH, 96 h) showed that the lower bonding temperature resulted in better reliability of the flip chip interconnects using ACFs. Therefore, the composite properties of cured ACF and reliability of flip chip on organic substrate assemblies using ACFs were strongly affected by the bonding temperature.     

A quantitative method of reliability estimation for surface mount solder joints based on heating factor Qη

A novel method of reliability analysis on thermal fatigue failure for surface mount solder joints, based on the heating factor Q_η, is presented, by which quantitative reliability estimation and prediction of solder joints suffering from cyclic thermal stress can be done. Based on the typical lifetime data of thermal cycling test, the relationship of the mean time to failure (MTTF) as well as the reliability of solder joints as an explicit function of Q_η is deduced and presented in a unified mathematic form. Numerical calculations are performed, and the result shows that the MTTF decreases quickly with the increases in heating factor and then slowly approximates to a constant value when Q_η  1500 s °C. The solder joint reliability in terms of thermal cycle degrades in an analogical fashion for different heating factors. For any given thermal cycle, calculation suggests that to obtain a higher reliability, a lower heating factor should be controlled during soldering. The presented method gives an applicable solution and can be used for online reflow control in industry. On the one hand, an ideal reflow profile can be achieved by properly controlling heating factor during soldering to meet the given reliability goal. On the other hand, the life expectancy of solder joints can be approximately estimated and predicted from a known reflow profile with a specified heating factor. Finally, for a specified reliability goal, how to properly choose and control heating factor during soldering to achieve reliable solder joints is discussed.     

Processability and reliability of epoxy adhesive used in microelectronic devices linked to effects of degree of cure and damp heat aging

In an effort to explicate the effects of degree of cure (conversion) and damp heat aging at 85 °C/85% RH on physical properties of the cured epoxy system consisting of diglycidyl ether of bisphenol F (DGBF) and imidazole as a curing agent, an experimental approach was systematically performed using a dynamic mechanical analyzer (DMA) and thermomechanical analyzer (TMA). Of interesting physical properties are the storage modulus, loss modulus, tan δ, glass transition temperature (T_g), and coefficient of thermal expansion (CTE). The die shear test was performed to evaluate changes in adhesion strength of the cured epoxy with and without an epoxy silane before and after the damp heat aging. We have found that the magnitude of storage modulus in a glass transition region and the onset temperature for degradation of storage modulus, DMA T_g, increase as the conversion of cure increases. Even though such benefits observed at ambient are lessened after extended exposure to the damp heat aging, higher conversion has less degradation than lower conversion. It is observed that T_g taken from DMA and TMA decreases approximately from 132 °C to 81 °C after 500 h of damp heat aging. Such large diminution is attributed to high moisture diffusivity of 2.0 × 10⁻⁸/cm²/s at 85 °C/85% RH and can cause large dimensional instability at the critical interface supported by the epoxy adhesive. We have also found that a 3-parameter exponential function is useful to predict the degradation of T_g under the given aging condition. Although the effect of an epoxy silane is negligible at ambient, it provides better adhesion strength after the damp heat aging. Finally, we intend to give process guidelines for the usage of DGBF/imidazole epoxy system to ensure stringent reliability in electronic device applications.     

Temperature profile effects in accelerated thermal cycling of SnPb and Pb-free solder joints

Accelerated thermal cycling (ATC) has been widely used in the microelectronics industry for reliability assessment. ATC testing decreases life cycle test time by one or more of the following means: increasing the heating and cooling rate, decreasing the hold time, or increasing the range of the applied temperature. The relative effect of each of these cycle parameters and the failure mechanisms they induce has been the subject of many studies; however uncertainty remains, particularly regarding the role of the heating and cooling rate. In this research, three conditions with two ramp rates (14 °C/min and 95 °C/min) and two temperature ranges (ΔT = 0–100 °C and −40 to 125 °C) were applied to resistor 2512 and PBGA 256 test vehicles assembled with SnPb and Pb-free solders. The test results showed that the higher ramp rate reduced the testing time while retaining the same failure modes, and that the damage per cycle increased with the temperature difference. For the resistors, the Pb-free solder joints lasted longer than the SnPb joints at the smaller ΔT, but were inferior at the larger ΔT. In contrast, the Pb-free solder joints in the PBGA test vehicles lasted longer than the SnPb solder under both conditions.     

Reliability results of HBTs with an InGaP emitter

Accelerated lifetest results are presented on HBTs with InGaP emitters. An Arrhenius plot indicates the existence of a temperature dependent activation energy, E_a. A low E_a mechanism dominates above T_j 380 °C and a high E_a mechanism dominates at lower temperature. The critical transition temperature between regimes is determined using the method of maximum likelihood. The difference in E_a’s between low and high temperature regimes is statistically significant.A comparison is made between lifetimes determined from at temperature vs. 40 °C data. No significant difference is observed indicating that beta degradation can be monitored at temperature only and cooling to low temperature is not necessary. Other comparisons indicate that junction temperatures up to 367 °C can still provide good estimates of lower temperature behavior.By the method of maximum likelihood, the predicted MTTF at T_j = 125 °C is 7.6 × 10⁹ h with 95% CBs of [6.4 × 10⁸, 8.9 × 10¹⁰]. Given the typical industry standard of 1 × 10⁶ h, the reliability requirements are easily met.It is suggested that the standard of 1 × 10⁶ h does not adequately capture failure time variation and that a better specification is in terms of fails in time (FITs). The 10 year average FIT rate at 125 °C is found to be negligible. Assuming a much higher junction temperature of 210 °C, the average failure rate climbs to 5 FITs with an upper 95% confidence bound of 40 FITs.     

Accelerated active ageing test on SiC JFETs power module with silver joining technology for high temperature application

This paper presents the accelerated active power cycling test (APCT) results on SiC JFETs power module dedicated to operate at high temperature. This study partly focuses on the new chip joining technology (LTJT), which permit to use SiC JFETs transistors at higher temperatures. We present the different die attachments tested with high temperature lead solder and silver sintering joining technologies. Active power cycling results for high junction temperature T_jmax = 175 °C with ΔT_j = 80 K to perform an evaluation of main damages during active test are carried out and a comparison between lead and silver chip joining technologies is presented.     

Optimal redundancies for reliability and availability of series systems

Five different series system configurations with standby units are compared based on their overall reliability and availability. The time-to-failure of a component and its repair time are assumed to have the negative exponential distribution. The mean time-to-failure, MTTF, and the steady-state availability, A_T(∞), are obtained for the first three simple configurations and comparisons are performed. For all five configurations, comparisons are made based on assumed numerical values given to the distribution parameters, as well as to the cost of the components. The configurations are ranked based on: MTTF, A_T(∞), cost and cost-benefit where benefit is either MTTF or A_T(∞).     

New approach for forming bulk-heterojunction solar cells comprising a π-conjugated polymer and C60

A new approach for high-efficiency polymer solar cells utilizing a BHJ active layer consisting of poly(3-hexylthiophene) (P3HT) as a donor and buckminsterfullerene, C₆₀ as an acceptor was demonstrated. P3HT/C₆₀ BHJ films were made possible by in situ formation of C₆₀ from solubilized addends, C₆₀–CpCO₂R (R = Hex, Oct, and EHex) by retro Diels–Alder reaction at, or above, 100 °C. These cells exhibit enhanced performances compared to as-prepared P3HT/C₆₀ BHJ films, showing better morphology.     

Aging of the over-voltage protection elements caused by over-voltages

The aim of this work is examining the influence of the number of the activation––over-voltage pulses to the aging of over-voltage protection elements. Both non-linear (gas-filled surge arresters (GFSA), varistors, over-voltage diodes) and linear (capacitors––constituents of filters) over-voltage protection elements were tested. The instruments employed allow reliable measurements, 1000 consecutive activation were tested. The double-exponential current pulse (amplitude I₁^max=13 A, I₂^max=16 A, rise time T₁=8 μs, fall time T₂=20 μs) for non-linear elements and a double-exponential over-voltage pulse (rise time T₁=1.2 μs, fall time T₂=50 μs) of the amplitude U₁^max=320 V, U₂^max=480 V and U₃^max=640 V for capacitors were used. The experimental results show that the over-voltage diodes are the most reliable elements in view of characteristic modifications that are consequence of aging. However, it was observed that varistors, GFSA and capacitors undergo noticeable changes in characteristics.     

Effects of the electrical stress on the conduction characteristics of metal gate/MgO/InP stacks

The degradation dynamics and post-breakdown current–voltage (I–V) characteristics of magnesium oxide (MgO) layers grown on n and p-type indium phosphide (InP) substrates subjected to electrical stress were investigated. We show that the current–time (I–t) characteristics during degradation can be described by a power-law model I(t) = I₀t^−α, where I₀ and α are constants. It is reported that the leakage current associated with the soft breakdown (SBD) failure mode follows the typical voltage dependence I = aV^b, where a and b are constants, for both injection polarities but in a wider voltage range compared with the SiO₂/Si system. It is also shown that the hard breakdown (HBD) current is remarkably high, involving large ON–OFF fluctuations that resemble the phenomenon of resistive switching previously observed in a wide variety of metal oxides.     

A 1.8-V 0.7 ppm/°C high order temperature-compensated CMOS current reference

A high order curvature compensation technique for current reference generator which exploits the I–V characteristic of MOS to achieve I _SC (T ^m ) (m ≥ 2) is described. I _SC (T ^m ) is a self-compensated current which corrects its negative three-order TC (Temperature Coefficient) and linear TC by itself. Then, I (T ²) is achieved also by exploiting the I–V characteristic of MOS, for correcting the other negative high order parts of I _SC (T ^m ). This circuit operates on a 1.8 V power supply and is compatible with a standard n-well 0.5-μm digital CMOS process. The circuit realizes a temperature coefficient of 0.7 ppm/°C, a deviation of the simulated output current of 0.011% from −20°C to + 150°C and 97.5 dB PSRR through HSPICE simulation.     

Low and high temperature device reliability investigations of buried p-channel MOSFETs of a 0.17 μm technology

The hot carrier degradation of buried p-channel MOSFETs of a 0.17 μm technology is assessed in the temperature range between −40°C and 125°C. Within this temperature range, the degradation of the electrical parameter is investigated for different drain voltages and channel lengths (0.2–0.3 μm) in the gate voltage range between V_GS=0 V and V_GS=V_DS. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are discussed by reviewing previous works. Based on hot carrier modelling and lifetime extrapolation to operating conditions the stressing voltage conditions are analysed. For the experimentally investigated temperature range the worst case stress condition is identified at low temperatures for gate voltage at the maximum of the gate current (I_Gmax). In the case of V_GS corresponding to I_Gmax two activation energies are determined for low and high temperatures. For temperatures above 125°C the worst case bias condition changes from V_GS=V_GS@I_Gmax to V_GS=V_DS.     

Microstructure evolution of the Sn–Ag–y%Cu interconnect

The lead free Sn–Ag–y%Cu (y = 0.0, 0.5, 1.0 and 2.0) interconnect interfacial microstructures and the microstructure evolution under thermal treatment (isothermal aging, 150 °C/1000 h) were studied in detail by using surface microetching microscopy and cross section microscopy. The corresponding mechanical and reliability behaviors were evaluated by performing shear test and fracture mode analysis before and after the thermal treatment. The results indicate: (i) The interconnects could have different microstructures and intermetallic compound (IMC), depending on the Cu content. The Cu–Sn IMC could have microstructures that were clusters or protrusion-like, Augustine grass leaf-like, scissor-like, tweezers-like, etc. (ii) Ag₃Sn IMCs were not observed at time zero for any interconnect groups, but they occurred after the aging for all groups. The Ag₃Sn IMC could have different microstructures, again depending on Cu content. For low Cu content, the Ag₃Sn IMCs were granules or nodules; for higher Cu content, Ag₃Sn IMCs were plate-like. (iii) The growth of Ag₃Sn plates was promoted by the growth of Cu–Sn IMCs, but indirectly linked to the Cu content. (iv) High Cu content (1.0 wt% and higher) could degrade the mechanical and reliability performances of the LF interconnect by providing a brittle joint, which was mainly achieved through the substantial growth of Cu–Sn IMCs and Ag₃Sn plates.     

An investigation of surface state capture cross-sections for metal–oxide–semiconductor field-effect transistors using HfO2 gate dielectrics

MOSFETs and MOSCs incorporating HfO₂ gate dielectrics were fabricated. The I_DS–V_DS, I_DS–V_GS, gated-diode and C–V characteristics were investigated. The subthreshold swing and the interface trap density were obtained. The surface recombination velocity and the minority carrier lifetime in the field-induced depletion region measured from the gated diodes were about 2.73 × 10³ cm/s and 1.63 × 10⁻⁶ s, respectively. The effective capture cross section of surface state was determined to be 1.6 × 10⁻¹⁵ cm² using the gated-diode technique in comparison with the subthreshold swing measurement. A comparison with conventional MOSFETs using SiO₂ gate oxide was also made.     

High-temperature reliability of Flip Chip assemblies

Flip Chip technology has been widely accepted within microelectronics as a technology for maximum miniaturization. Typical applications today are mobile products such as cellular phones or GPS devices. For both widening Flip Chip technology’s application range and for addressing the automotive electronics’ volume market, developing assemblies capable of withstanding high temperatures is crucial. A typical scenario for integrating electronics into a car is a control unit within the engine compartment, where ambient temperatures are around 150 °C, package junction temperatures may range from 175 °C to 200 °C and peak temperatures may exceed these values.If Flip Chip technology is used under harsh environment conditions, it is clear that especially the polymeric materials, i.e., underfiller, solder mask or the organic substrate base material, are challenged. Generally, the developmental goal for encapsulants compatible with high-temperature applications are materials with high T_g and low degradation even at temperatures >200 °C.According to these demands, a test group of advanced underfill encapsulants has been used for assembling Flip Chip devices. These test vehicles were built using lead-free and lead-containing solders such as SnAgCu and eutectic PbSn and standard FR4 substrates, for evaluating the reliability potential of state-of-the-art underfillers. Material analysis is performed for studying both material degradation as well as temperature-dependent thermo-mechanical and adhesive properties. For assessing reliability, temperature cycling is performed with different maximum test temperatures ranging from 150 °C to 175 °C. The device status is intermediately analyzed by using electrical measurement for detecting bond integrity and acoustomicroscopy for determining the occurrence and growth of delaminations. Extensive failure analysis is added to investigate device failure mechanisms, especially related to the respective test temperature.In summary, an empirical status of the high-temperature potential of state-of-the-art underfillers and material combinations is attained and an outlook on future demands and developments is provided.     

Electromigration of Sn–37Pb and Sn–3Ag–1.5Cu/Sn–3Ag–0.5Cu composite flip–chip solder bumps with Ti/Ni(V)/Cu under bump metallurgy

We examine electromigration fatigue reliability and morphological patterns of Sn–37Pb and Sn–3Ag–1.5Cu/Sn–3Ag–0.5Cu composite solder bumps in a flip–chip package assembly with Ti/Ni(V)/Cu UBM. The flip–chip test vehicle was subjected to test conditions of five combinations of applied electric currents and ambient temperatures, namely, 0.4 A/150 °C, 0.5 A/150 °C, 0.6 A/125 °C, 0.6 A/135 °C, and 0.6 A/150 °C. The electrothermal coupling analysis was employed to investigate the current crowding effect and maximum temperature in the solder bump in order to correlate with the experimental electromigration reliability using the Black’s equation as a reliability model. From available electromigration reliability models, we also present a comparison between fatigue lives of Sn–37Pb solder bumps with Ti/Ni(V)/Cu and those with Al/Ni(V)/Cu UBM under different current stressing conditions.     

Numerical analysis of a SWEAT structure with an improved one dimensional nonlinear model

An improved one dimensional (1 − D) nonlinear model of the thermal response of the Standard Wafer-level Electromigration Accelerated Test (SWEAT) structure is described. The major improvement in this model are accurate predictions of the critical current density j_o; according to older models j_o is inversely proportional to the “power” I²R/R(T_s), while our model shows a different (increasing) trend and is confirmed by measurements. The ratio of the maximum temperature increase to the average temperature increase (γ) for the investigated structure depends on the relative change of the resistance and normalized current , and can be calculated within 1% from basic material and structure parameters. The model includes the edge correction factor α depending on the geometry of the structure (W_n/t_i), material parameters and stress current I. Using the corrected values for the edge correction factor, the maximum temperature increase in the SWEAT test structure can be calculated within less than 5°C.     

Heat Capacity Study on Anharmonicity in Ae<Subscript>8</Subscript>Ga<Subscript>16</Subscript>Ge<Subscript>30</Subscript> (Ae = Sr and Ba)

The heat capacity of single-crystalline samples of Sr₈Ga₁₆Ge₃₀ (SGG) and Ba₈Ga₁₆Ge₃₀ (BGG) clathrates was measured to investigate the anharmonicity of the encapsulated atoms. At low temperatures, BGG can be well described by a standard Debye model, and the C _p/T ³ versus T plot can be fitted with two Einstein temperatures: θ _E1 = 42 K and θ _E2 = 74 K. On the other hand, SGG shows deviation from the Debye model. Moreover, neither the Einstein model nor the soft potential model (SPM) alone can fit the peak in the C _p/T ³ versus T plot, and the peak should be fitted by employing both models. Our results indicate that the effective electron mass is enhanced by the anharmonic phonons.