Profiling Voids Embedded in a Slab by a Non-Linear Model

In this paper, by applying a non linear model for the electromagnetic inverse scattering, a technique for the dielectric profiling of a planarly layered medium is investigated and applied to void localization and diagnostics inside a homogeneous lossless slab (one-dimensional geometry). Data are collected under plane wave multifrequency normal incidence. Suitable finite dimensional representations for the unknown functions are introduced and their influence on the model is discussed. The resulting functional equation is solved by the method of weighted residuals and the solution algorithm amounts to minimizing a non quadratic function, where particular attention is devoted to reduce the occurrence of local minima. Finally, the inversion algorithm is validated by applications to both simulated and experimental data.     

Modelling of 2-D Real Rational Reactance Functions. A Parameter-Based Approach

Lossless (reactive) one-ports are of great importance in the field of linear network theory. This statement also applies for the two-dimensional (2-D) case, where the design of corresponding impedance or admittance functions is a much more challenging task. In this paper a model for 2-D real rational reactance functions is introduced which is a rational function in p₁ and p₂ where the coefficients are functions of parameters. The following features make it best suited for the computer based design of lossless one-ports, namely no dependencies between the real valued parameters, coverage of the whole class of 2-D real rational reactance functions, and the coefficients are polynomials in the parameters. The synthesis of 2-D lossless networks and skew symmetric matrices form the basis of our considerations.     

Low-Voltage Continuous-Time Filter Based on a CMOS Transconductor with Enhanced Linearity

The proposed design of a low-voltage continuous time filter is based on a CMOS transconductor with enhanced linearity. The compensation principle is used for the reduction of transconductor non-linear distortions. The discussed transconductor consists of two transconductors connected in parallel. The input transistors of the first transconductor are working in the triode region, while the input transistors of the further one are in the saturation. A fifth-order 1 MHz low-pass Bessel filter is synthesized and simulated using transconductors. The supply voltage is equal to +2.5 V. A tuning system of the filter is also simulated and discussed. A comparison shows that the discussed filter provides a higher linearity (from 4 to 9 dB) than the known circuits with the exception of filters based on the amplifier with degeneration. But it is noted that the last approach is difficult to use for the low-voltage application, because the voltage drop on the degeneration resistors limits the possible decrease of the voltage supply.     

A depletion load self-aligned technology

Based on an accurate large signal MOSFET model, a computer aided design of the elementary NOR gate using a P channel depletion enhancement self-aligned technology has been done so as to minimize power-speed product. Threshold adjustment and gate self-registration are achieved by ion implantation. Measurements of main electrical and technological parameters are given. Computer aided design results are compared with measured performances on a 99 gates ring oscillator. For a 5 V supply voltage power-speed products as low as 1 pJ are obtained.     

An Immitance Based Tool for Modelling Passive One-Port Devices by Means of Darlington Equivalents

An immitance-based method is presented to model measured orcomputed data, obtained from a “passive one-port physical device” by means of its Darlington equivalent. In other words, the given data ismodelled as a lossless two port terminated in a unit resistor. The basis of the new modelling tool rests on the numerical decomposition of the given immitance data into its Foster and minimum parts. Therefore, the proposed technique does not require any choice for the circuit topology to build the model. Rather, the optimum circuit topology that characterises thegiven data is the natural consequence of the modelling process proposed in this paper. A main algorithm is presented to construct the model from the given data. It is expected that the proposed modelling tool will findpractical applications in the behaviour characterisation, simulation, and design of high speed/high frequency analog/digital mobile communication sub-systems manufactured on VLSI chips. An antenna-modelling example is included to systematically exhibit the implementation of the modelling technique.     

Recursive Halfband-Filters

The paper describes the properties and the design of recursive halfband-filters.The two possibilities of being complementary are introduced. The lowpass with the transfer function H_Lp(z)and the corresponding highpass, described by H_Hp(z) = H_Lp(-z)can either be strictly complementary or power complementary. According to the respective symmetry, the impulse responses, transfer functions and frequency responses possess certain characteristic properties, which are described in section 2. It turns out that these resulting symmetries of the frequency response reduce the number of the choosable design parameters. We can only prescribe the cutoff frequency and the tolerated deviation either for the passband or the stopband.

In the third section we treat the design of halfband-filters with approximately linear phase. By coupling an appropriately designed allpass of even degree n_A with a delay of order m=n_A±1 we obtain the desired solution by solving a corresponding approximation problem for the phase of the allpass. The resulting lowpass and highpass are strictly as well as power complementary!The kind of approximation will be done in the sense of maximal flatness, where a closed form solution exists [8], or in the sense of Chebychev, where the solution is obtained iteratively [13]. The design of systems with minimum phase is presented in section 4. The resulting lowpass and highpass are power complementary. Closed form solutions yield Butterworthand Cauer filters, if a maximal flat or a Chebychev approximation is desired. In all cases a fixed relation exists between the passband frequency Ω_P and the tolerated deviation δ_P in the passband when the degree n has been chosen.     

Hierarchical interconnection structures for field programmable gatearrays

Field programmable gate arrays (FPGA's) suffer from lower density and lower performance than conventional gate arrays. Hierarchical interconnection structures for field programmable gate arrays are proposed. They help overcome these problems. Logic blocks in a field programmable gate array are grouped into clusters. Clusters are then recursively grouped together. To obtain the optimal hierarchical structure with high performance and high density, various hierarchical structures with the same routability are discussed. The field programmable gate arrays with new architecture can be efficiently configured with existing computer aided design algorithms. The k-way min-cut algorithm is applicable to the placement step in the implementation. Global routing paths in a field programmable gate array can be obtained easily. The placement and global routing steps can be performed simultaneously. Experiments on benchmark circuits show that density and performance are significantly improved     

Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load

This paper deals with the problem of estimating the performance of a CMOS gate driving RLC interconnect load. The widely accepted model for CMOS gate and interconnect line is used for the representation. The CMOS gate is modeled by an Alpha Power law model, whereas the distributed RLC interconnect is represented by an equivalent π-model. The output waveform and the propagation delay of the inverter are analytically calculated and compared with SPICE simulations. The analytical driver-interconnect load model gives sufficiently close results to SPICE simulations for two different cases of slow and fast input ramps. For each case of stimulation, the model gives an insight to four regions of operation of the CMOS gate. The voltage waveform at the end of an interconnect line is obtained for each region of operation. The SPICE and analytical results for the output voltage waveform and propagation delay match very closely.     

Two-dimensional pixel image lag simulation and optimization in a 4-T CMOS image sensor

Pixel image lag in a 4-T CMOS image sensor is analyzed and simulated in a two-dimensional model.Strategies of reducing image lag are discussed from transfer gate channel threshold voltage doping adjustment,PPD N-type doping dose/implant tilt adjustment and transfer gate operation voltage adjustment for signal electron transfer.With the computer analysis tool ISE-TCAD,simulation results show that minimum image lag can be obtained at a pinned photodiode n-type doping dose of 7.0×10~(12) cm~(-2),an implant ...     

Analysis of the Collocation Method for Simulating the Propagation of Optical Pulse Sequences

In analogy to the standard Split-Step Fourier algorithm for calculating the signal transmission through optical fibers, a Split-Step collocation algorithm is applied and analyzed in terms of its capability to calculate the propagation of pulse sequences in optical fibers. The method uses a point matching technique for the representation of short optical pulse sequences with Hermite-Gauss functions as basis. This special basis renders time consuming Fast Fourier Transformations (FFT) within the calculation unnecessary. The method is analyzed using realistic NRZ pulse sequences in the simulations. Accuracy and computational effort are evaluated in comparison to the Split-Step Fourier method.     

Flexible Digital Receiver Architecture with Optimized Components

Future wireless communication systems require increased flexibility, lower power consumption, smaller size and decreasing costs for the terminals and therewith for the components. By replacing analogue by digital signal processing the degree of integration and the flexibility of a terminal with respect to multi-mode capability can be improved.In a highly integrated implementation the most critical components are the A/D-converter and the digital filter stages due to high speed and low power requirements. In this contribution a novel concept for a flexible, digital receiver with highly optimized components will be presented. The concept is based on down-conversion of the broadband receive signal to a low intermediate frequency. The main modules of the receiver are a properly designed ΔΣ-modulator for A/D-conversion, and novel digital filtering stages. It will be demonstrated, that the use of cascaded low-order wave digital lattice filters results in a number of advantages and makes a very efficient realization in VLSI-technology feasible.     

A New Waveguide Filter Design and Optimization Approach Using Shadow Specifications

This work uses an optimization technique for the frequency response of waveguide filters which is more advantageous than conventional waveguide filter optimization techniques. The method uses only three variables in the penalty function, irrespective of the filter order. It drastically reduces the chance of convergence to a local minimum, computer storage requirements and computation time. Several examples are presented to support the validity of the approach. The approach will be valuable in waveguide multiplexer design and in many other areas of engineering science.     

SET-based nano-circuit simulation and design method using HSPICE

This paper presents a simulation and design method for complementary SET-based nano-circuits from a practical circuit design point of view. HSPICE behavioral implementation of modified Lientschnig's SET model based on the orthodox theory and the Birth-Death Markov chain is demonstrated and verified with Coulomb characteristics. It shows reduced CPU time, improvement of accuracy, and more compatibility with other SPICE softwares on both Windows and Unix platforms. The proposed design methodology presents how to build static CMOS-like SET circuits, and demonstrates that conventional CMOS circuit design methodologies are all applicable to SET circuit designs based on the methodology. HSPICE simulation results show that, for 1 MΩ junction resistance, the power consumption of a SET NAND2 gate is less than 0.3 pW, and the propagation delay for a SET XOR2 gate is 29.8 ns while driving a 10 aF load.     

20万门CMOS门阵列设计技术

本文主要介绍0.8umCMOS门阵列的设计技术,包括建库技术,可测性设计技术、时钟设计技术、电源、地设计技术、电路结构优化、余量设计技术等,最后介绍了20万门母片及电路的主要参数。     

CMOS电路混合整数最优化及设计方法

本文给出了一类CMOS门电路的最优设计问题,并给出了在一定约束条件下最大倒相链级数优化的混合整数优化模型。根据一种连续整数规划求解方法,本文提出了对CMOS电路混合整数优化的设计方法和步骤。最后,本文给出了一个实际的设计结果。     

On the Reduction of the Complexity of Realistic Large Scale Network Simulations

Current computer systems allow a realistic simulation with more than 100,000 HTTP/TCP clients, as shown in this paper. However, the complexity of such simulations is high: the required memory and the simulation duration touches reasonable limits. Reducing the complexity by using a smaller number of clients as compared to reality is evaluated in this study. The reduction is performed with increasing the activity of each client keeping the load approx. constant. Further, it is shown that the average number of active clients remains approx. constant. The reduction has two targets: (i) the optimisation of the considered simulation scenario and (ii) to allow for simulations with larger simulation scenarios.

It is evaluated how the reduction affects the following parameters: average traffic load, coefficient of variation, Hurst parameter, end-to-end delay and loss probability. It is shown that only the loss probability is affected by the reduction. The simulation results show that the required memory can be reduced by a factor of 4–8, depending on the error bound, and the simulation speed increased by up to 33%. The gain allows to simulate an equivalent of 1,200,000 instead of 150,000 clients.     

A Non-Linear Multiuser Detector for UMTS

The family of international standards for mobile communications IMT-2000 includes amongst others the UMTS Terrestrial Radio Access (UTRA) proposal, which consists of two modes: Frequency Division Duplex (FDD) and Time Division Duplex (TDD). Both are wideband CDMA systems. CDMA systems are Multiple Access Interference (MAI) limited. Conventional detectors like the RAKE receiver do not decrease the MAI, this leads to a limited Bit Error Rate (BER) performance. For further improvement of system capacity Multiuser Detectors (MUD) should be applied. In this paper a non-linear approach employing Radial Basis Functions (RBF) is shown. The adaption of this algorithm to UTRA, its complexity and the BER-performance is discussed.     

Simulation of characteristics and optimization of the constructive and technological parameters of integrated magnetosensitive elements in micro and nanosystems

The features of the technology computer aided design of integrated magnetosensitive elements in micro and nanosystems are considered. The results of the simulation and optimization of the constructive and technological parameters for magnetosensitive transistors, integrated Hall elements based on the standard CMOS technology, the Hall field sensor based on SOI-structures, and the characteristics of magnetic field concentrators are presented.