Co-Implantation and autocompensation in close contact rapid thermal annealing of Si-implanted GaAs:Cr

Close contact rapid thermal annealing of semi-insulating GaAs:Cr implanted with Si, Si + Al, and Si + P has been studied using variable temperature Hall effect measurements and low temperature (4.2K) photoluminescence (PL) spectroscopy. Isochronal (10 sec) and isothermal (1000° C) anneals indicate that As is lost from the surface during close contact annealing at high anneal temperatures and long anneal times. Samples which were implanted with Si alone show maximum activation at an annealing temperature of 900° C, above which activation efficiency decreases. Low temperature Hall and PL measurements indicate that this reduced activation is due to increasing auto-compensation of Si donors by Si acceptors at higher anneal temperatures. However, co-implantation of column V elements can increase the activation of Si implants by reducing Si occupancy of As sites and increasing Si occupancy of Ga sites, and therebyoffset the effects of As loss from the surface. For samples implanted with Si + P, activation increases continuously up to a maximum at an anneal temperature of 1050° C, and both low temperature Hall and PL measurements indicate that autocompensation does not increase in this case as the anneal temperature increases. In contrast, samples implanted with Si + Al show very low activation and very high compensation at all anneal temperatures, as expected. The use of column V co-implants in conjunction with close contact RTA can produce excellent donor activation of Si implanted GaAs.     

Ion implantation damage in GaAs: A TEM study of the variation with ion species and stoichiometry

GaAs samples have been implanted with a dose of 2 × 10¹⁴ cm^?2 of each ion in the following combinations: Ga, As, Ga + As, Se, Ga + Se and As + Se. Implantation was at 200°C, and post implantation annealing at 700°C. Subsequent examination by transmission electron microscopy (TEM) showed clear and reproducible differences in the dislocation loop size and density, depending on the ion species implanted. The simplest results were obtained with the single implants, particularly Ga and As. These observed variations could be explained in terms of point defect populations, and hence rates of annealing at a given anneal temperature, being affected significantly by the stoichiometric effect of the implant. These simpler aspects were also seen to be incorporated in the more complex “dual” implants.     

Reduction of boron diffusion in silicon-germanium by fluorine implantation

This letter investigates the effect of a 185 keV, 2.3 /spl times/ 10/sup 15/ cm/sup -2/ F/sup +/ implant on boron transient enhanced diffusion (TED) and boron thermal diffusion in SiGe by characterizing the diffusion of a boron marker layer in samples with and without a 288 keV, 6 /spl times/ 10/sup 13/ cm/sup -2/ P/sup +/ implant. In samples implanted with F/sup +/ only, the fluorine suppresses boron thermal diffusion by 58%. In samples given both P/sup +/ and F/sup +/ implants, the fluorine completely eliminates boron transient enhanced diffusion caused by the P/sup +/ implant and also significantly reduces boron thermal diffusion. SIMS profiles after anneal show a fluorine concentration in the SiGe layer that is approximately 8 /spl times/ higher than after implant, indicating that fluorine accumulates in the SiGe layer during anneal. A comparison with fluorine profiles in comparable silicon samples also shows that the fluorine concentration after anneal is dramatically higher in SiGe samples than in Si samples. This accumulation of fluorine in the SiGe layer during anneal will have major benefits for boron diffusion suppression in devices like SiGe HBTs, where boron must be kept within the SiGe layer.     

Laser Annealed and Thermal Annealed Refractory Ohmic Contacts to GaAs

Ohmic contacts to n-type GaAs have been developed for high-temperature device applications up to 300°C. Refractory metallizations were used with epitaxial Ge layers to form the contacts TiW/Ge/GaAs, Ta/Ge/GaAs, Mo/Ge/GaAs, and Ni/Ge/GaAs. Contacts with high dose Si or Se ion implantation (1012 to 1014/cm2) of the Ge/GaAs interface were also investigated. The purpose of this work was to develop refractory ohmic contacts with low specific-contact resistance (~10-6 ?cm2 on 1 x 1017cm-3GaAs) which are free of imperfections, resulting in a uniform n+ doping layer. The contacts were fabricated on epitaxial GaAs layers (n = 2 x 1016 to 2 x 1017 cm-3) grown on n+ ( 2 x 1018 cm-3) or semi-insulating GaAs (at strates. Ohmic contact was formed by both thermal annealing ( at temperatures up to 700°C) and laser annealing (pulsed Ruby). Examination of the Ge/GaAs interface revealed Ge migration into GaAs to form an n+layer. Under optimum laser anneal conditions, the specific contact resistance was in the range 1-5 x 10-6 ?-cm2 (on 2 x 1017cm-3GaAs). Thermally annealed TiW/Ge had a contact resitivity of 1 x 10-6 ? cm2 on 1 x 1017 cm-3 GaAs under optimum anneal conditions. The contacts also showed improved thermal stability over conventional Ni/AuGe contacts at temperatures above 300°C.     

Growth of strained-Si material using low-temperature Si combined with ion implantation technology

In order to fabricate strained-Si MOSFETs, we present a method to prepare strained-Si material with high-quality surface and ultra-thin SiGe virtual substrate. By sandwiching a low-temperature Si (LT-Si) layer between a Si buffer and a pseudomorphic Si0.08Ge0.2 layer, the surface roughness root mean square (RMS) is 1.02 nm and the defect density is 106 cm-2 owing to the misfit dislocations restricted to the LT-Si layer and the threading dislocations suppressed from penetrating into the Si0.08Ge0.2 layer. By employing P+ implantation and rapid thermal annealing,the strain relaxation degree of the Si0.08Ge0.2 layer increases from 85.09% to 96.41% and relaxation is more uniform. Meanwhile, the RMS (1.1 nm) varies a little and the defect density varies little. According to the results, the method of combining an LT-Si layer with ion implantation can prepare high-quality strained-Si material with a high relaxation degree and ultra-thin SiGe virtual substrate to meet the requirements of device applications.     

0.2-μm p+-n junction characteristics dependent onimplantation and annealing processes

Junction depth, sheet resistance, dopant activation, and diode leakage current characteristics were measured to find out the optimal processing conditions for the formation of 0.2-μm p⁺-n junctions. Among the 2×10¹⁵ cm^-2 BF₂ implanted crystalline, As or Ge preamorphized silicon, the crystalline and Ge preamorphized samples exhibit excellent characteristics. The thermal cycle of furnace anneal (FA) followed by rapid thermal anneal (RTA) shows better characteristics than furnace anneal, rapid thermal anneal, or rapid thermal anneal prior to furnace anneal     

Rapid thermal annealing of dual Si and P implants in InP

In this study we evaluate the effects of dual implantation with different doses of Si and P on dopant activation efficiency and carrier mobility in InP:Fe. The implants were activated by a rapid thermal annealing step carried out in an optimized phosphoruscontaining ambient. For high dose implants (10¹⁴–10¹⁵ cm⁻²), which are typically employed for source/drain regions in FETs, dual implantation of equal doses of Si and P results in a higher sheet carrier concentration and lower sheet resistance. For 10¹⁴ cm⁻² Si implants at 150 keV, the optimal P co-implant dose is equal to the Si dose for most anneal temperatures. We obtain an activation efficiency of ∼70% for dual implanted samples annealed at 850° C for 10 sec. The high activation efficiencies and low sheet resistances obtained in this study emphasize the importance of stoichiometry control through the use of P co-implants and a phosphorus-containing ambient during the thermal processing of InP.     

Growth and characterization of GaAs films deposited on Ge/Si composite substrates by metalorganic chemical vapor deposition

We report the results of studies which have been made on heteroepitaxial layers of GaAs and AlGaAs grown by metalorganic chemical vapor deposition on composite substrates that consist of four different types of heteroepitaxial layered structures of Ge and Ge-Si grown by molecular beam epitaxy on (100)-oriented Si substrates. It is found that of the four structures studied, the preferred composite substrate is a single layer of Ge ∼1 μm thick grown directly on a Si buffer layer. The double-crystal X-ray rocking curves of 2 μm thick GaAs films grown on such substrates have FWHM values as small as 168 arc sec. Transmission electron micrographs of these Ge/Si composite substrates has shown that the number of dislocations in the Ge heteroepitaxial layer can be greatly reduced by an anneal at about 750° C for 30 min which is simultaneously carried out during the growth of the GaAs layer. The quality of the GaAs layers grown on these composite substrates can be greatly improved by the use of a five-period GaAs-GaAsP strained-layer superlattice (SLS). Using the results of these studies, low-threshold optically pumped AlGaAs-GaAs DH laser structures have been grown by MOCVD on MBE Ge/Si composite substrates.     

Shallow boron implantations in Ge and the role of the pre-amorphization depth

The impact of the Ge pre-amorphization conditions on shallow B profiles, resulting from a 1 keV implantation in n-type Ge and a 500 °C 1 min rapid thermal anneal, is investigated. In general, an increase of the sheet resistance with lower Ge energy is observed. There is some evidence for tail diffusion, enhancing slightly the junction depth and reducing its steepness. This could point to end-of-range-mediated transient-enhanced diffusion (TED) of B in Ge. It is clear that for this to happen, a pre-amorphization is required which contains completely the B profile.     

LEC不掺杂半绝缘GaAs的热处理特性

本文对LEC不掺杂SI-GaAs的热处理特性进行了实验研究和分析。结果表明,As、Ga原子从表面挥发及缺陷的内扩散引起表面热蚀和热致导电层的形成。文章讨论了它们对注入层激活行为的影响。指出,采用本文设计的高温快速热处理结合压盖、InAs作过砷压源技术,可以获得满足注硅材料退火要求的SI-GaAs热处理特性。     

A study of the oxidation behavior and the postannealing effect in a graded SiGe/Si heterostructure

A study on the dry thermal oxidation of a graded SiGe layer was performed. To reduce the Ge pileup effect during the thermal oxidation, the SiGe layer was deposited with much lower Ge content near the free surface than near the SiGe/Si heterointerface. After dry thermal oxidation at 900°C, the Ge composition in the pileup layer was significantly reduced and strain relaxation by defect formation was prevented due to the graded Ge distribution. To homogenize the Ge distribution between the pileup layer and remaining SiGe layer, the oxidized layers were postannealed. The homogenization is significantly enhanced by strain-induced diffusion, and it was confirmed by uphill diffusion of Ge. This result can propose an alternative oxidation method of strained SiGe/Si heterostructures.     

The electrical properties of HfO/sub 2/ dielectric on germanium and the substrate doping effect

MOS devices built on various germanium substrates, with chemical vapor deposited (CVD) or physical vapor deposited (PVD) HfO/sub 2/ high-/spl kappa/ dielectric and TaN gate electrode, were fabricated. The electrical properties of these devices, including the capacitance equivalent thickness (CET), gate leakage current density (J/sub g/), slow trap density (D/sub st/), breakdown voltage (V/sub bd/), capacitance-voltage (C-V) frequency dispersion, and thermal stability, are investigated. The process conditions such as surface nitridation treatment, O/sub 2/ introduction in CVD process and postdeposition anneal temperature in PVD process, exhibit significant impacts on the devices' electrical properties. The devices built on germanium substrates with different dopant types and doping concentrations show remarkable variations in electrical characteristics, revealing the role of the substrate doping in the reactions occurring at the dielectric/Ge interface, which can significantly affect the interfacial layer formation and Ge updiffusion. A possible mechanism is suggested that two competing processes (oxide growth and desorption) take place at the interface, which govern the formation of the interfacial layer. Doped p-type (Ga) and n-type (Sb) impurities may enhance the different process at the interface and cause the variations in the interfacial layer formation and so on in electrical properties. The high diffusivities of impurities and Ge atoms in Ge and the induced structural defects near the substrate surface could be one possible cause for this doping effect. As another behavior of the substrate doping effect, Ge n-MOS and p-MOS stacks show quite different C-V characteristics after high temperature postmetallization anneal treatments, which can be explained by the same mechanism.     

Shallow-junction diode formation by implantation of arsenic andboron through titanium-silicide films and rapid thermal annealing

The performance of diodes fabricated on n-type and p-type Si substrates by implanting As or B through a low-resistivity titanium-silicide layer is discussed. The effects of varying the implant dose, energy, and postimplant thermal treatment were investigated. After implantation, a rapid thermal anneal was found to remove most of the implant damage and activate the dopants, which resulted in n⁺-p and p⁺-n junctions under a low-resistivity silicide layer. The n⁺-p junctions were as shallow as 1000 Å with reverse leakage currents as low as 5.5 μA/cm². A conventional furnace anneal resulted in a further reduction of this leakage. Shallow p⁺-n junctions could not be formed with boron implantation because of the large projected range of boron ions at the lowest available energy. Ti silicide films thinner than 600 Å exhibited a sharp rise in sheet resistivity after a furnace anneal, whereas thicker films exhibited more stable behavior. This is attributed to coalescence of the films. High-temperature furnace annealing diffused some of the dopants into the silicide film, reducing the surface concentrations at the TiSi₂ -Si interface     

Low-thermal-budget process modeling with the PREDICT computerprogram

Low-thermal-budget processing models have been developed that are applicable to a broad range of ion-implantation and annealing conditions. The cases discussed here include low-temperature furnace annealing of B implants, preamorphization or postamorphization using Si ⁺ or Ge⁺ implants, and rapid thermal annealing of low-dose and high-dose implants. Annihilation of implant damage is accounted for through activated annealing models. Damage type and location in depth are important in understanding enhanced or retarded diffusion of dopants. Damage and diffusion models have been incorporated in the PREDICT program, and example calculations are compared with measurements     

Optimization of implant anneals to improve transistor performancein a 0.15 μm CMOS technology

The impact of including a rapid thermal anneal step after the extension implants is examined for a 0.15 μm CMOS process. SIMS data will verify that shallower junctions can be obtained with only a single anneal cycle after the source-drain implants, implying that transient enhanced diffusion is minimal for this technology. Further, transistor data indicates that improved CMOS device performance can be obtained without the extension anneal cycle     

Role of a Si0.95Ge0.05 epilayer cap on boron diffusion in silicon under inert and dry oxidizing ambient annealing

Silicon (Si) and Si with a 60 nm Si_0.95Ge_0.05 epilayer cap (Si_0.95Ge_0.05/Si) were implanted with 60 keV, 1×10¹³ cm⁻² boron (B) followed by annealing in nitrogen (N₂) or dry oxygen (O₂) in two different anneal conditions. B⁺implantation energy and dose were set such that the B peak is placed inside Si in Si_0.95Ge_0.05/Si samples and concentration independent B diffusion is achieved upon annealing. For samples annealed above 1075 °C, Ge diffusing from the Si_0.95Ge_0.05 epilayer cap in Si_0.95Ge_0.05/Si samples reached the B layer inside Si and resulted in retarded B diffusion compared to the Si samples. For annealing done at lower temperatures, diffusion of Ge from Si_0.95Ge_0.05 epilayer cap does not reach the B layer inside Si. Thus B diffusion profiles in the Si and Si_0.95Ge_0.05/Si samples appear to be similar. B diffusion in dry oxidizing ambient annealing of Si_0.95Ge_0.05/Si samples further depends on the nature of Si_0.95Ge_0.05 oxidation which is set by the duration and the thermal budget of the oxidizing anneal.     

Growth conditions to achieve mobility enhancement in AlxGa1?xAs-GaAs heterojunctions by m.b.e.

Modulation doped Al0.25Ga0.75As-GaAs heterojunctions have been prepared by molecular beam epitaxy (m.b.e.). Al0.25Ga0.75As layers were doped with Si to a level of ~ 3 × 1017 cm?3, whereas the GaAs layers were either unintentionally doped, doped lightly n-type with Sn, or doped lightly p-type with Be. Heterojunction structures having single and multiple periods have shown enhanced mobility only with the AlxGa1?xAs layer at the surface and the GaAs layer underlying. These results represent the first report that electrons spill over only into the underlying GaAs layer from the top AlxGa1?xAs layer.     

Implant temperature dependence of transient-enhanced diffusion in silicon (1 0 0) implanted with low-energy arsenic ions

The diffusion of arsenic implanted into silicon at low ion energies (2.5 keV) has been studied with medium-energy ion scattering, secondary ion mass spectrometry and four-point probe measurements. The dopant redistribution together with the corresponding damage recovery and electrical activation produced by high-temperature (550–975°C) rapid thermal anneals has been investigated for a range of substrate temperatures (+25, +300 and −120°C) during implant. Initial results show an implant temperature dependence of the damage structure and arsenic lattice position prior to anneal. Solid-phase epitaxial regrowth was observed following 550°C, 10 s anneals for all implant temperatures and resulted in approximately 60% of the implanted arsenic moving to substitutional positions. Annealing at 875°C resulted in similar arsenic redistribution for all implant temperatures. Following annealing at 925°C, transient-enhanced diffusion was observed in all samples with more rapid diffusion in the +25°C samples than either the −120 or +300°C implants, which had similar dopant profiles. In the 975°C anneal range, similar rates of implant redistribution were observed for the +300 and +25°C implants, while diffusion in the −120°C sample was reduced. These observations are discussed qualitatively in terms of the nature and density of the complex defects existing in the as-implanted samples.     

Anti-phase domain-free growth of GaAs on offcut (001) Ge wafers by molecular beam epitaxy with suppressed Ge outdiffusion

The nucleation and growth of GaAs films on offcut (001) Ge wafers by solid source molecular beam epitaxy (MBE) is investigated, with the objective of establishing nucleation conditions which reproducibly yield GaAs films which are free of antiphase domains (APDs) and which have suppressed Ge outdiffusion into the GaAs layer. The nucleation process is monitored by in-situ reflection high energy electron diffraction and Auger electron spectroscopy. Several nucleation variables are studied, including the state of the initial Ge surface (single-domain 2×1 or mixed-domain 2×1:1×2), the initial prelayer (As, Ga, or mixed), and the initial GaAs growth temperature (350 or 500°C). Conditions are identified which simultaneously produce APD-free GaAs layers several microns in thickness on Ge wafers with undetectable Ge outdiffusion and with surface roughness equivalent to that of GaAs/GaAs homoepitaxy. APD-free material is obtained using either As or Ga nucleation layers, with the GaAs domain dependent upon the initial exposure chemical species. Key growth steps for APD-free GaAs/Ge growth by solid source MBE include an epitaxial Ge buffer deposited in the MBE chamber to bury carbon contamination from the underlying Ge wafer, an anneal of the Ge buffer at 640°C to generate a predominantly double atomic-height stepped surface, and nucleation of GaAs growth by a ten monolayer migration enhanced epitaxy step initiated with either pure As or Ga. We identify this last step as being responsible for blocking Ge outdiffusion to below 10¹⁵ cm⁻³ within 0.5 microns of the GaAs/Ge interface.     

High quality GaAs qrowth by MBE on Si using GeSi buffers and prospects for space photovoltaics

III–V solar cells on Si substrates are of interest for space photovoltaics since this would combine high performance space cells with a strong, lightweight and inexpensive substrate. However, the primary obstacles blocking III–V/Si cells from achieving high performance to date have been fundamental material incompatibilities, namely the 4% lattice mismatch between GaAs and Si, and the large mismatch in thermal expansion coefficient. In this paper, we report on the molecular beam epitaxial (MBE) growth and properties of GaAs layers and single junction GaAs cells on Si wafers which utilize compositionally graded GeSi intermediate buffers grown by ultra‐high vacuum chemical vapor deposition (UHVCVD) to mitigate the large lattice mismatch between GaAs and Si. GaAs cell structures were found to incorporate a threading dislocation density of 0.9–1.5×10 cm⁻², identical to the underlying relaxed Ge cap of the graded buffer, via a combination of transmission electron microscopy, electron beam induced current, and etch pit density measurements. AlGaAs/GaAs double heterostructures were grown on the GeSi/Si substrates for time‐resolved photoluminescence measurements, which revealed a bulk GaAs minority carrier lifetime in excess of 10 ns, the highest lifetime ever reported for GaAs on Si. A series of growths were performed to assess the impact of a GaAs buffer layer that is typically grown on the Ge surface prior to growth of active device layers. We found that both the high lifetimes and low interface recombination velocities are maintained even after reducing the GaAs buffer to a thickness of only 0.1 μm. Secondary ion mass spectroscopy studies revealed that there is negligible cross diffusion of Ga, As and Ge at the III–V/Ge interface, identical to our earlier findings for GaAs grown on Ge wafers using MBE. This indicates that there is no need for a buffer to ‘bury’ regions of high autodoping, and that either pn or np configuration cells are easily accommodated by these substrates. Preliminary diodes and single junction AlGaAs heteroface cells were grown and fabricated on the Ge/GeSi/Si substrates for the first time. Diodes fabricated on GaAs, Ge and Ge/GeSi/Si substrates show nearly identical I–V characteristics in both forward and reverse bias regions. External quantum efficiencies of AlGaAs/GaAs cell structures grown on Ge/GeSi/Si and Ge substrates demonstrated nearly identical photoresponse, which indicates that high lifetimes, diffusion lengths and efficient minority carrier collection is maintained after complete cell processing. Copyright © 2000 John Wiley & Sons, Ltd.