A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis

This paper presents a partitioned and embedded BIST technique for data path like circuits. The BIST scheme is defined at behavioral level for full optimization of both system and BIST modes during High Level Synthesis. Test time, area overhead and fault coverage are under the scope of the method. User-given constraints on fault coverage to achieve on data path operators and on test time are used to guide the BIST insertion technique towards the lowest area overhead solution.     

An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths

In this paper an effective Built-In Self-Test (BIST) scheme for the shifter-accumulator pair (accumulation performed either by an adder or an ALU) which appears very often in embedded processor, microprocessor or DSP datapaths is introduced. The BIST scheme provides very high fault coverage (>99%) with respect to the stuck-at fault model for any datapath width with a regular, very small and counter-generated deterministic test set, as it is verified by a comprehensive set of experiments.     

Combining Scan Test and Built-in Self Test

For digital chips containing functional logic and embedded memories, these are usually tested separately: Scan test is used for testing functional logic; Memory Built-in Self Test (MBIST) is run for embedded memories. A new approach is proposed to exercise scan test and MBIST in parallel in order to reduce production test time and improve stress tests. It requires only small additional logic and allows to simultaneously run both test modes. In general, the approach can be used to control simultaneously scan test and any Built-in Self Test (BIST) providing a simple pass/fail result.     

Reusing Scan Chains for Test Pattern Decompression

The paper presents a method for testing a system-on-a-chip by using a compressed representation of the patterns on an external tester. The patterns for a certain core under test are decompressed by reusing scan chains of cores idle during that time. The method only requires a few additional gates in the wrapper, while the mission logic is untouched. Storage and bandwidth requirements for the ATE are reduced significantly.     

一种有效的八位MCU桶形移位器 BIST 电路

针对8位微控制器（MCU）数据通道中桶形移位器的可测试性问题，提出了一种新颖的确定性内置自测试（BIST）电路设计方案，并对其进行了验证。该方案采用5个D触发器，在16个测试时钟周期内产生16个测试矢量，可完成对8位桶形移位器100％故障覆盖率测试。本论文的电路设计方案也可应用于一般2^N位（N≥4）桶形移位器的可测试设计。     

异构系统下的双向签密方案

在过去的研究中,人们通常假设通信双方都处在同一个公钥密码体制环境中,但随着科技的发展和网络的普及,不同的地区可能采用不同的公钥密码体制。为了解决异构系统之间的通信安全问题,该文提出两种在公共密钥基础设施(PKI)和无证书公钥密码体制(CLC)下安全通信的异构签密方案。同时在双线性Diffie-Hellman问题(BDHP)和计算性Diffie-Hellman问题(CDHP)的难解性下,所提方案在随机预言模型中具有自适应选择密文攻击下的不可区分性(IND-CCA2)和自适应选择消息攻击下的不可伪造性(EUF-CMA)。     

Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST

In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional compression scheme, which combines the advantages of known vertical and horizontal compression techniques. To reduce both the number of patterns to be stored and the number of bits to be stored for each pattern, deterministic test cubes are encoded as seeds of an LFSR (horizontal compression), and the seeds are again compressed into seeds of a folding counter sequence (vertical compression). The proposed BIST architecture is fully compatible with standard scan design, simple and flexible, so that sharing between several logic cores is possible. Experimental results show that the proposed scheme requires less test data storage than previously published approaches providing the same flexibility and scan compatibility.     

一种有效的双矢量测试BIST实现方案

文章提出了一种简单有效的双矢量测试BIST。实现方案．其硬件主要由反馈网络可编程且种子可重置的LF—SR和映射逻辑两部分构成。给出了一种全新的LPSR最优种子及其反馈多项式组合求取算法，该算法具有计算简单且容易实现的特点。最后。使用这种BIST、方案实现了SoC中互联总线间串扰故障的激励检测，证明了该方案在计算量和硬件开销方面的优越性。     

SoC中混合信号的测试

随着经济社会的发展,人们对消费类电子的多媒体功能要求越来越高;这极大促进了SoC中混合信号工艺的运用,但是随之而来的是SoC在测试上遇到了前所未有的难题,因为混合信号电路的集成使他不同于纯数字电路IC的测试。SoC中混合信号的测试是SoC进一步发展的瓶颈,这对研究提出了紧迫的要求。介绍SoC中混合信号测试面临的主要问题,着重讨论了混合信号边界扫描测试,内置自测试方法(BIST)等测试手段及各自的特点。展望了SoC混合信号测试的研究方向。     

Behavioral Testability Insertion for Datapath/Controller Circuits

A method for test synthesis in the behavioral domain is described.The approach is based on the notion of adding a test behavior to the normal-mode design behavior. This testbehavior describes the behavior of the design in test mode. Thenormal-mode design behavior and test-mode test behavior are combinedand then synthesized by any general-purpose synthesis system toproduce a testable design with inserted BIST structures. The testbehavior is derived from the design behavior using testabilityanalysis based on metrics that quantify the testability of signalsand variables embedded within behaviors. The insertion method iscombined with a behavioral test scheme thatintegrates a) the design controller and test controller, b) testingof the entire datapath and controller. Examples show that when thetestability insertion procedure is used to modify a behavior beforesynthesis, the resulting synthesized physical implementation isindeed more easily tested than an implementation synthesized directlyfrom the original behavior.     

逻辑簇边界扫描测试相关问题及解决方案

逻辑簇的边界扫描测试存在一些不可忽视的重要问题.分析了这些问题的影响,提出了相应措施,并介绍了结合BIST技术进行逻辑簇测试的方法.     

On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level

Test power requirements for complex components are becoming stringent. The purpose of this paper is to reuse a recently proposed RT (Register Transfer) Level test preparation methodology to drive innovative Low-Energy (LE)/Low-Power (LP) BIST solutions for digital SoC (System on a Chip) embedded cores. RTL test generation is carried out through the definition of a reduced set of partially specified input vectors (masks), leading to a high correlation between multiple detection of RTL faults and single detection of likely physical defects. The methodology is referred as masked-based BIST, or m-BIST. BIST quality is evaluated considering three attributes: test effectiveness (TE), test length (TL) and test power (TP). LE BIST sessions are defined as short test sequences leading to high values of RT-level IFMB metrics and low-level Defects Coverage (DC). The energy and power of the BIST sessions, with and without mask forcing, is computed. It is shown that, by forcing vectors with the RTL masks, short BIST sessions, with low energy and with a comparable (or smaller) average power consumption, as compared to pseudo-random test, are derived. The usefulness of the methodology is ascertained using the VeriDOS simulation environment and modules of the CMUDSP and TORCH ITC'99 benchmark circuits.     

New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters

Two alternative BIST schemes are proposed for structural testing of pipelined Analog-to-Digital Converters (ADC). They are oriented to fault detection in the converter stages rather than to measure the whole ADC electrical performance parameters. The operational principle of both strategies relies on testing every ADC stage reconfigured as an A/D-D/A block and applying as input a simple DC stimuli set which is easily obtained, without strong precision requirements, by a resistive network. The main differences between both strategies relate to the way the output response is evaluated. In the BIST#1 scheme, analog and digital outputs are compared with reference levels generated with a reference D/A converter and a counter. In the BIST#2 strategy, only digital outputs are available and they are compared with fault-free values previously stored in an on-chip register. The new techniques are intended to be used in pipelined converters of an arbitrary number of conversion stages and with a digital self-correction mechanism.     

PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators

The PICO-NPA system automatically synthesizes nonprogrammable accelerators (NPAs) to be used as co-processors for functions expressed as loop nests in C. The NPAs it generates consist of a synchronous array of one or more customized processor datapaths, their controller, local memory, and interfaces. The user, or a design space exploration tool that is a part of the full PICO system, identifies within the application a loop nest to be implemented as an NPA, and indicates the performance required of the NPA by specifying the number of processors and the number of machine cycles that each processor uses per iteration of the inner loop. PICO-NPA emits synthesizable HDL that defines the accelerator at the register transfer level (RTL). The system also modifies the user's application software to make use of the generated accelerator.The main objective of PICO-NPA is to reduce design cost and time, without significantly reducing design quality. Design of an NPA and its support software typically requires one or two weeks using PICO-NPA, which is a many-fold improvement over the industry norm. In addition, PICO-NPA can readily generate a wide-range of implementations with scalable performance from a single specification. In experimental comparison of NPAs of equivalent throughput, PICO-NPA designs are slightly more costly than hand-designed accelerators.Logic synthesis and place-and-route have been performed successfully on PICO-NPA designs, which have achieved high clock rates.     

高速串行数据接收器专用集成电路的可测性设计

本文为了解决高速串行数据接收器专用集成电路的测试难题．提出了针对该高速工作的集成电路的测试方案．并设计了可行的测试电路．通过添加测试引脚、设计专用测试模式．内建自测试等方法有效的群决了该芯片电路的功能测试和电气性能测试．     

A Unified DFT Approach for BIST and External Test

This paper presents a partial reset technique for testability improvement of non-scan sequential circuits. Both pseudo-random BIST and deterministic External Test are in the scope of this paper. The partial reset technique is used to improve hard-to-detect fault activation. This DFT approach is completed with classical insertion of observation points in order to improve fault propagation. Numerous experimental results on ISCAS'89 benchmark circuits show that 100% fault efficiency can be achieved at low cost.     

Sequential Circuit Test Generation Using a Symbolic/Genetic Hybrid Approach

Symbolic and genetic techniques are combined in a new approach to sequential circuit test generation that uses circuit decomposition, rather than the algorithmic decomposition used in previous hybrid test generators. Symbolic techniques are used to generate test sequences for the control logic, and genetic algorithms are used to generate sequences for the datapath. The combined sequences provide higher fault coverages than those generated by existing deterministic and GA-based test generators, and execution times are significantly lower in many cases.     

Scalable Test Generators for High-Speed Datapath Circuits

This paper explores the design of efficient test sets and test-pattern generators for on-line BIST. The target applications are high-performance, scalable datapath circuits for which fast and complete fault coverage is required. Because of the presence of carry-lookahead, most existing BIST methods are unsuitable for these applications. High-level models are used to identify potential test sets for a small version of the circuit to be tested. Then a regular test set is extracted and a test generator TG is designed to meet the following goals: scalability, small test set size, full fault coverage, and very low hardware overhead. TG takes the form of a twisted ring counter with a small decoder array. We apply our technique to various datapath circuits including a carry-lookahead adder, an arithmetic-logic unit, and a multiplier-adder.     

A Ring Architecture Strategy for BIST Test Pattern Generation

This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under test (CUT), i.e., no test point insertion. The set of patterns generated by a pseudo-random pattern generator, e.g. a Linear Feedback Shift Register (LFSR), is transformed into a new set of patterns that provides the desired fault coverage. To transform these patterns, a ring architecture composed by a set of masks is used. During on-chip test pattern generation, each mask is successively selected to map the original pattern sequence into a new test sequence. We describe an efficient algorithm that constructs a ring of masks from the test cubes provided by an automatic test pattern generator (ATPG) tool. Moreover, we show that rings of masks are implemented very easily at low silicon area cost, without requiring any logic synthesis tool; a combinational mapping logic corresponding to the masks is placed between the LFSR and the CUT, together with a looped shift register that acts as a mask selecting circuit. Experimental results are given at the end of the paper, demonstrating the effectiveness of the proposed approach in terms of area overhead, fault coverage and test sequence length. Note that this paper is an extended version of [1].     

Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences

The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. In this context, it has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when a high robust delay fault coverage is targeted. In this paper, we show that random SIC (RSIC) test sequences achieve a higher fault coverage than random MIC (RMIC) test sequences when both robust and non-robust tests are under consideration. Experimental results given in this paper are based on a software generation of RSIC test sequences that can be easily generated in this case. For a built-in self-test (BIST) purpose, hardware generated RSIC sequences have to be used. This kind of generation will be shortly discussed at the end of the paper.