A 1.2 V 114 mW Dual-Band Direct-Conversion DVB-H Tuner in 0.13 $mu$ m CMOS

A fully integrated direct-conversion tuner is implemented in 0.13 $muhbox{m}$ CMOS technology. A broadband noise-canceling balun LNA with the proposed dual cross-coupling technique helps achieve an overall receiver noise figure from 3.7 to 4.3 dB while consuming only 3.6 mW. The proposed current-mode switching scheme improves the achievable SNIR with a gain step of 15 dB, providing IIP3 improvement of 18 dB and NF degradation of only 6 dB. Moreover, design trade-offs are carefully considered in designing the baseband circuit, which provides wide gain tuning and bandwidth accuracy with a DC offset residual less than 6 mV. The measured maximum SNR values are better than 30 dB over wide input power levels, ensuring robust reception in a mobile environment. All circuit blocks are operated at 1.2 V. As a result, the tuner consumes power as low as 114 mW in the continuous mode. This compact tuner supports both UHF and L- bands, and occupies only 7.2 $ {hbox{mm}}^{2}$ die area.      

A 51 to 65 GHz Low-Power Bulk-Driven Mixer Using 0.13 $mu$m CMOS Technology

A low-voltage and low-power down-conversion bulk-driven mixer using standard 0.13 $mu$ m CMOS technology is presented in this letter. To work on a low supply voltage and low power consumption applications while maintaining reasonable performance, the bulk-driven technique is selected in this V-band mixer design. The mixer has a conversion gain of $0 pm 1.5$ dB from 51 to 65 GHz with low supply voltage of 1 V and low power consumption of 3 mW. To our knowledge, the MMIC is the highest frequency CMOS bulk-driven mixer to date with good conversion gain and low power consumption among the recently published active mixers around 60 GHz.      

A 24 GHz Amplitude Monopulse Comparator in 0.13 $mu$m CMOS

This letter presents the design and implementation of a wideband 24 GHz amplitude monopulse comparator in 0.13 $mu$m CMOS technology. The circuit results in 9.6 dB gain in the sum channel at 24 GHz with a 3-dB bandwidth of 23.0–25.2 GHz, and a sum/difference ratio of $> 25$ dB at 20–26 GHz. The measured input P1 dB is ${-}14.4$ dBm at 24 GHz. The chip is only 0.55$,times,$ 0.50 mm$^{2}$ (without pads) and consumes 44 mA from a 1.5 V supply, including the input active baluns and the differential to single-ended output stages (28 mA without the input and output stages). To our knowledge, this is the first demonstration of a high performance mm-wave CMOS monopulse comparator RFIC.      

0.13 $mu$ m SiGe BiCMOS Technology Fully Dedicated to mm-Wave Applications

This paper presents a complete 0.13$,muhbox{m}$ SiGe BiCMOS technology fully dedicated to millimeter-wave applications, including a high-speed (230/280 GHz ${rm f}_{rm T}/{rm f}_{rm MAX}$) and medium voltage SiGe HBT, thick-copper back-end designed for high performance transmission lines and inductors, 2 $hbox{fF}/muhbox{m}^{2}$ high-linearity MIM capacitor and complementary double gate oxide MOS transistors. Details are given on HBT integration, reliability and models as well as on back-end devices models.      

Plasmon-Waveguide Interband Cascade Lasers Near 7.5 $mu$ m

Broad-area plasmon-waveguide interband cascade lasers with emission wavelengths near 7.5 mu m were demonstrated at temperatures up to 121 K in continuous-wave mode. Their threshold current densities and voltages varied from 72 A/cm² and 2.1 V at 84 K to 400 A/cm² and 2.7 V at 121 K, showing very efficient use of bias voltage (e.g., voltage efficiency of about 90% at 84 K) at this long wavelength. These plasmon-waveguide lasers also operated in pulsed mode at temperatures up to 165 K with emission wavelengths near 7.6 mum and threshold current density of 1100 A/cm².     

A 0.6 V Low-Power Wide-Range Delay-Locked Loop in 0.18 $mu$m CMOS

In this letter, a delay-locked loop (DLL) suitable for low-power and low-voltage operations is presented. To overcome the performance limitations, such as a restricted locking range and elevated output jitters, a novel voltage-controlled delay cell and a phase/frequency detector with a start controller are employed in the proposed DLL. Using a standard 0.18 mum CMOS process, the fabricated circuit exhibits a locking range from 85 to 550 MHz. The measured peak-to-peak and rms jitters at 550 MHz are 25.6 and 3.8 ps, respectively. Operated at a supply voltage of 0.6 V, the power consumption of the DLL circuit varies from 2.4 to 4.2 mW within the entire locking range.     

A $K$ -Band CMOS Distributed Doubler With Current-Reuse Technique

A $K$-band distributed frequency doubler is developed in 0.18 $mu{rm m}$ CMOS technology. This doubler combines the distributed topology for broadband characteristics and current-reuse technique to improve the conversion gain. The high-pass drain line and high-pass inter-stage matching network are used to obtain a good fundamental rejection. A measured conversion gain of better than ${- 12.3}~{rm dB}$ is obtained, and the fundamental rejection is better than 30 dB for the output frequency between 18 and 26 GHz. The dc power consumption is 10.5 mW with a chip size of 0.55$,times,$0.5 ${rm mm}^{2}$.      

A 0.1 mm$^{2}$ , Wide Bandwidth Continuous-Time $SigmaDelta$ ADC Based on a Time Encoding Quantizer in 0.13 $mu$ m CMOS

The ADC shown in this paper uses an innovative sigma-delta (SigmaDelta) architecture that replaces the flash quantizer and mismatch corrected DAC of a multibit continuous time (CT) modulator by a time domain encoder similar to a PWM modulator to reduce the effective ADC area. The modulator achieves the resolution of a multibit design using single bit circuitry by concentrating most of the quantization error energy around a single frequency, which is afterwards removed, seizing the zeros of a sinc decimation filter. The non flat error spectrum is accomplished by use of two filter loops, one of which is made to operate in a self-oscillating mode. An experimental CT-SigmaDelta ADC prototype has been fabricated in 0.13 mum CMOS which implements a third order modulator with two operating modes. Measurements show an effective number of bits (ENOB) of 10 bits and 12 bits in a signal bandwidth of 17 MHz and 6.4 MHz, respectively, and a power-efficient figure of merit (FoM = Pwr/2 middot BW middot 2^ENOB) of 0.48 pJ/conversion at 1.5 V supply. The active area of the ADC is 0.105 mm².     

A 1.8 V 900 $mu$ W 4.5 GHz VCO and Prescaler in 0.18 $mu$m CMOS Using Charge-Recycling Technique

This letter presents a charge-recycling VCO and divider in 0.18 $mu$m CMOS technology. The power consumption of the proposed circuit is significantly reduced by stacking the low-voltage divider on the top of the low-voltage VCO, and hence, the VCO reuses the current from the divider. To enhance the reliability of the proposed circuit under supply voltage variation, transistor sharing and adaptive body-biasing techniques are employed. It allows the proposed circuit to operate down to 1.45 V of supply voltage without degrading the FoM. Experimental results show that the proposed circuit achieves 900 $mu$W of power consumption and ${-}184$ dBc/Hz of FoM at 1.8 V.      

An E-TSPC Divide-by-2 Circuit With Forward Body Biasing in 0.25 $mu$ m CMOS

A forward body biasing (FBB) technique is employed by an extended true-single-phase-clock (E-TSPC) divide-by-2 circuit in 0.25 mu m CMOS for an efficient on-chip control of power and speed. By applying the forward body bias voltage of 0.4 V, the maximum operating frequency is improved by 78% while the current dissipation is increased only by 21%. As a result, the divider figure-of-merit is improved by 46%. The phase noise however is not significantly affected by the forward body biasing. We believe that the FBB technique can be an efficient means for on-chip scaling of speed and power in E-TSPC RF frequency divider circuits.     

A 10 GHz Phase-Locked Loop With a Compact Low-Pass Filter in 0.18 $mu$ m CMOS

In this letter, a multi-gigahertz phase-locked loop (PLL) with a compact low-pass filter is presented. By using a novel dual-path control in the PLL architecture, the capacitance in the loop filter can be effectively reduced for high-level integration while maintaining the required loop bandwidth. Consequently, the noise resulted from off-chip components is therefore eliminated, leading to lower timing jitter at the PLL output waveforms. In addition, the timing jitter is further suppressed due to the use of decomposed phase and frequency detection. Based on the proposed techniques, a 10 GHz PLL is implemented in 0.18 mum CMOS for demonstration. Consuming a dc power of 113 mW from a 1.8 V supply, the fabricated circuit exhibits a locking range from 10.1 to 11 GHz. At an output frequency of 10.3 GHz, the measured peak-to-peak and rms jitter are 3.78 and 0.44 ps, respectively.     

Widely Tunable Micro-Mechanical External-Cavity Diode Laser Emitting Around 2.1 $mu$ m

A widely tunable $(Delta lambda/lambda =7hbox{%})$ micro-mechanical external cavity GaSb-based diode laser ($mu$ ECL) emitting around 2.1 $mu$ m is presented. A micro-machined grating with a rectangular grating profile, which can be tilted electrostatically, is employed as wavelength selective element within the external cavity using a Littrow configuration. An optimized grating profile leads to a high diffraction efficiency in the ${-}1$st diffraction order and therefore to a broad tuning range of 152 nm. The maximum output power of the fiber coupled $mu$ ECL system varied only moderately between 22 and 10 mW across the tuning range.      

$n$ -SIFT: $n$ -Dimensional Scale Invariant Feature Transform

We propose the $n$ -dimensional scale invariant feature transform ( $n$-SIFT) method for extracting and matching salient features from scalar images of arbitrary dimensionality, and compare this method's performance to other related features. The proposed features extend the concepts used for 2-D scalar images in the computer vision SIFT technique for extracting and matching distinctive scale invariant features. We apply the features to images of arbitrary dimensionality through the use of hyperspherical coordinates for gradients and multidimensional histograms to create the feature vectors. We analyze the performance of a fully automated multimodal medical image matching technique based on these features, and successfully apply the technique to determine accurate feature point correspondence between pairs of 3-D MRI images and dynamic $3{rm D} + {rm time}$ CT data.      

A 2.4-GHz Resistive Feedback LNA in 0.13-$mu$m CMOS

A $g_{m}$-boosted resistive feedback low-noise amplifier (LNA) using a series inductor matching network and its application to a 2.4 GHz LNA is presented. While keeping the advantage of easy and reliable input matching of a resistive feedback topology, it takes an extra advantage of $g_{m}$ -boosting as in inductively degenerated topology. The gain of the LNA increases by the $Q$ -factor of the series RLC input network, and its noise figure (NF) is reduced by a similar factor. By exploiting the $g_{m}$-boosting property, the proposed fully integrated LNA achieves a noise figure of 2.0 dB, S21 of 24 dB, and IIP3 of ${- 11}~ hbox{dBm}$ while consuming 2.6 mW from a 1.2 V supply, and occupies 0.6 ${hbox {mm}}^{2}$ in 0.13-$mu{hbox {m}}$ CMOS, which provides the best figure of merit. This paper also includes an LNA of the same topology with an external input matching network which has an NF of 1.2 dB.      

A K-Band High-Gain Down-Conversion Mixer in 0.18 $mu$m CMOS Technology

A high gain CMOS down conversion mixer with a gain enhancement technique is presented. This technique includes negative resistance generation, parasitic capacitance cancellation and current-injection. These are implemented with an additional circuitry. This mixer has a conversion gain of 9.12 dB, input 1 dB compression point of -11 dBm at 24 GHz, while consuming 16.2 mW from 1.8 V supply. Between 22 and 26 GHz, the LO-to-RF and RF-to-LO isolations are better than 35 dB and 26 dB, respectively.     

Ultra-Low-Voltage 20-GHz Frequency Dividers Using Transformer Feedback in 0.18-$mu$ m CMOS Process

This paper presents the design and analysis of ultra- low-voltage (ULV) high-frequency dividers using transformer feedback. Specifically, a differential-input differential-output injection-locked (IL) divider topology with transformer feedback and a wideband transformer-coupled (TC) divider with quadrature outputs are demonstrated, both of which can operate well at supply voltages as low as the device's threshold voltages. Fabricated in a standard 0.18-mum CMOS process, the ULV-IL divider measures an input frequency range from 16.1 GHz to 20 GHz while consuming a total power from 2.75 mW to 4.35 mW at 0.5 V supply, and the TC-divider measures an input frequency range of 27.8% from 15.1 GHz to 20 GHz with IQ sideband rejection of - 31 dBc while consuming power from 11.4 mW to 13.6 mW at 0.6 V supply.     

70 GHz Folded Loop Dual-Mode Bandpass Filter Fabricated Using 0.18 $mu$ m Standard CMOS Technology

This letter presents the design and implementation of a 70 GHz millimeter-wave compact folded loop dual-mode on-chip bandpass filter (BPF) using a 0.18 $mu$m standard CMOS process. A compact BPF, consisting of such a planar ring resonator structure having dual transmission zeros was fabricated and designed. The size of the designed filter is 650$,times,$ 670 $mu$ m$^{2}$ . Calculated circuit model, EM simulated and measured results of the proposed filter operating at 70 GHz are shown in a good agreement and have good performance. The filter has a 3-dB bandwidth of about 18 GHz at the center frequency of 70 GHz. The measured insertion loss of the passband is about 3.6 dB and the return loss is better than 10 dB within the passband.      

A Wideband PLL-Based G/FSK Transmitter in 0.18 $mu$m CMOS

A wideband phase-locked loop (PLL)-based G/FSK transmitter (TX) architecture is presented in this paper. In the proposed TX, the G/FSK data is applied outside the loop; hence, the data rate is not constrained by the PLL bandwidth. In addition, the PLL remains locked all the time, preventing the carrier frequency from drifting. In this architecture, the G/FSK modulation signal is generated from a proposed Sigma-Delta modulated Phase Rotator $(SigmaDelta{hbox{-PR}})$. By properly combining the multi-phase signals from the PLL output, the $SigmaDelta{hbox{-PR}}$ effectively operates as a fractional frequency divider, which can synthesize modulation signals with fine-resolution frequencies. The proposed $SigmaDelta{hbox{-PR}}$ adopts the input signal as the phase transition trigger, facilitating a glitch-free operation. The impact of the $SigmaDelta{hbox{-PR}}$ on the TX output noise is also analyzed in this paper. The proposed TX with the $SigmaDelta{hbox{-PR}}$ is digitally programmable and can generate various G/FSK signals for different applications. Fabricated in a 0.18 $muhbox{m}$ CMOS technology, the proposed TX draws 6.3 mA from a 1.4 V supply, and delivers an output power of $-$11 dBm. With a maximum data rate of 6 Mb/s, the TX achieves an energy efficiency of 1.5 nJ/bit.      

A 10–40 GHz Broadband Subharmonic Monolithic Mixer in 0.18 $mu$ m CMOS Technology

A 10–40 GHz broadband subharmonic monolithic passive mixer using the standard 0.18 $mu$ m CMOS process is demonstrated. The proposed mixer is composed of a two-stage Wilkinson power combiner, a short stub and a low-pass filter. Likewise, the mixer utilizes a pair of anti-parallel gate-drain-connected diodes to achieve subharmonic mixing mechanism. The two-stage Wilkinson power combiner is used to excite a radio frequency (RF) and local oscillation (LO) signals into diodes and to perform broadband operation. The low-pass filter supports an IF frequency range from dc to 2.5 GHz. This proposed configuration leads to a die size of less than 1.1$,times,$ 0.67 mm$^{2}$ . The measured results demonstrate a conversion loss of 15.6–17.6 dB, an LO-to-RF isolation better than 12 dB, a high 2LO-to-RF isolation of 51–59 dB over 10–40 GHz RF bandwidth, and a 1 dB compression power of 8 dBm.      

High-Q Slow-Wave Coplanar Transmission Lines on 0.35 $mu$m CMOS Process

In this letter, experimental results and trends for shielded coplanar waveguide transmission lines (S-CPW) implemented in a 0.35 $mu$m CMOS technology are provided. Because of the introduction of floating strips below the CPW transmission line, high effective dielectric permittivity and quality factor are obtained. Three different geometries of S-CPW transmission lines are characterized. For the best geometry, the measured effective dielectric permittivity reaches 48, leading to a very high slow-wave factor and high miniaturization. In addition, measurements demonstrate a quality factor ranging from 20 to 40 between 10 and 40 GHz, demonstrating state-of-the-art results for transmission lines realized in a low-cost CMOS standard technology.