程控真空高压器件老炼台的研制

程控真空高压器件老炼台由可调直流高压电源、储能器、高压脉冲变压器、高压开关、触发器、控制器、工控机、程控真空计、打印机、存贮示波器、限流电阻箱、极性转换器、高压击穿检测器及高压脉冲分压器等构成。该装置通过真空高压器件内真空度和高压击穿信号为判据,决定高压脉冲电压幅度和限流电阻的增减,实现自动控制老炼工艺过程。     

陶瓷电容分压器幅度线性度研究

高功率电脉冲装置常使用电容分压器监测其电压值。电容分压器的幅度线性度表征了分压器在大电压与小电压下分压比的一致程度。线性度的好坏直接关系到监测的电压值的准确程度。本文对陶瓷电容分压器进行原理分析,并通过仿真软件在脉宽为200 ns的矩形脉冲高压源(500 V~4 kV)与半高宽约为10 μs的冲击高压源(10~100 kV)下分别对陶瓷电容分压器的性能进行仿真,并设计加工。之后分别采用两种高压源对分压器进行实验研究,研究显示,陶瓷电容分压器的幅度线性度在500 V~100 kV之内为1.5%,线性度较好,可以将小信号下校准的分压比用于大信号的测量中。     

介质基板电容分压器幅度线性度研究

高功率电脉冲装置常使用电容分压器来监测其电压值。电容分压器的幅度线性度表征了分压器在大电压与小电压下分压比的一致程度,线性度的好坏直接关系到监测的电压值的准确程度。本文通过对介质基板电容分压器进行原理分析,并通过仿真软件在脉宽为200 ns的矩形脉冲高压源(500 V～4 kV)与半高宽约为10μs的冲击高压源(10～100 kV)下分别对介质基板电容分压器的性能进行仿真,并设计加工。之后分别采用两种高压源对分压器进行实验研究,结果显示,介质基板电容分压器的幅度线性度在500 V～100 kV之内为1.16%,线性度较好,可以将小信号下校准的分压比用于大信号的测量中。     

脉冲电阻分压器的性能分析和电感补偿

在自动检测领域,高压窄脉冲的测量是非常重要的,脉冲分压器结合AD采集卡是常用的测量系统的主要组成部分.电阻分压器因其结构简单、性能优良、使用方便等特性而具有广泛的应用.本文讨论了电阻元件杂散电容对脉冲电阻分压器性能的影响,引入传递函数的概念对其进行理论分析,提出了电感补偿的方法.实验结论和理论计算结果一致,验证了电感补偿的可行性.     

不同阻值电阻分压器对MOV残压测试的影响

冲击电阻分压器是测量压敏电阻(Metal Oxide Varistor,MOV)残压必不可少的设备之一,为了测量残压的准确性,利用三组不同分压器对高压臂电阻值优选范围进行试验研究,同时在源阻抗为0.45Ω和1.1Ω的8/20μs波形冲击电流发生器下进行MOV残压试验。试验结果表明冲击电压发生器源阻抗低时,A、B、C三组分压器在20kA下测得残压不会发生分压比线性偏离,20kA以上高压臂阻值越高,分压器越稳定;冲击电压发生器源阻抗上升至1.1Ω时,A、C分压器在不同冲击电流下测试分压比均稳定,高压臂阻值对测量MOV残压影响很小。     

具有高压互连线的多区双RESURF LDMOS击穿特性

对600V以上级具有高压互连线的多区双RESURF LDMOS击穿特性进行了实验研究,并对器件进行了二维、三维仿真分析.利用多区P-top降场层的结终端扩展作用以及圆形结构曲率效应的影响,增强具有高压互连线的横向高压器件漂移区耗尽,从而降低高压互连线对器件耐压的影响.实验与仿真结果表明,器件的击穿电压随着互连线宽度的减小而增加,并与P-top降场层浓度存在强的依赖关系,三维仿真结果与实验结果较吻合,而二维仿真并不能较好反映具有高压互连线的高压器件击穿特性.在不增加掩模版数、采用额外工艺步骤的条件下,具有30μm高压互连线宽度的多区双RESURF LDMOS击穿电压实验值为640V.所设计的高压互连器件结构可用于电平位移、高压结隔离终端,满足高压领域的电路设计需要.     

具有高压互连线的多区双RESURF LDMOS击穿特性

对600V以上级具有高压互连线的多区双RESURF LDMOS击穿特性进行了实验研究,并对器件进行了二维、三维仿真分析.利用多区P-top降场层的结终端扩展作用以及圆形结构曲率效应的影响,增强具有高压互连线的横向高压器件漂移区耗尽,从而降低高压互连线对器件耐压的影响.实验与仿真结果表明,器件的击穿电压随着互连线宽度的减小而增加,并与P-top降场层浓度存在强的依赖关系,三维仿真结果与实验结果较吻合,而二维仿真并不能较好反映具有高压互连线的高压器件击穿特性.在不增加掩模版数、采用额外工艺步骤的条件下,具有30μm高压互连线宽度的多区双RESURF LDMOS击穿电压实验值为640V.所设计的高压互连器件结构可用于电平位移、高压结隔离终端,满足高压领域的电路设计需要.     

SOI RESURF器件高压互连线效应的二维解析模型

高压互连线效应是影响集成功率器件性能的重要因素之一。首先提出一个高压互连线效应对SOI横向高压器件的漂移区电势和电场分布影响的二维解析模型,进而得到漂移区在不完全耗尽和完全耗尽情况下的器件击穿电压解析表达式,而后利用所建立的模型,研究器件结构参数对击穿特性的影响规律,定量揭示在高压互连线作用下器件击穿多生在阳极PN结的物理本质,指出通过优化场氧厚度可以弱化高压互连线对器件击穿的负面影响,并给出用于指导设计的理论公式。模型的正确性通过半导体二维器件仿真软件MEDICI进行了验证。     

具有多等位环的高压屏蔽新结构MER-LDMOS耐压分析

提出一种多等位环(multiple equipotential rings,MER)的高压屏蔽新结构MER-LDMOS,并解释了该结构的屏蔽机理,通过2D器件模拟验证了屏蔽机理的正确性.讨论了p-top剂量、等位环长度、等位环间距以及氧化层厚度对MER-LDMOS击穿电压的影响.结果表明MER-LDMOS突破常规LDMOS高压屏蔽的能力,击穿电压较常规LDMOS提高一倍以上;同时,该结构具有工艺简单、工艺容差大、反向泄漏电流小等优点,为高压集成电路中高压屏蔽的问题提供了一种新的解决方案.     

针尖电极尖端直径对带有针尖结构的摩擦纳米发电机输出的影响

摩擦纳米发电机(TENG)由于其超高电压特性而备受关注.为了进一步提升TENG的输出性能,受益于对自然界闪电击穿空气产生巨大能量的观察,引入对称针尖结构.利用TENG产生的高压来击穿对称针尖微小区域的空气,从而产生能量更为集中的高压.通过电学性能测试得到,带有针尖结构的TENG的开路电压达到2.5 kV(不携带针尖结构...     

A novel exponential power combiner/divider

A simple and novel theoretical analysis for an exponential two-way power combiner/divider is developed. The proposed power combiner/divider's parameters, such as input impedance and reflection and transmission coefficients, are determined. The capacitance effect due to the finite thickness of the coupled-line conductor for both uniform and nonuniform transmission lines is found. The properties of the combiner/divider were tested experimentally, and experimental results are presented     

Avalanche breakdown in high-voltage D-MOS devices

A new type of voltage breakdown occurring in high-voltage D-MOS transistors is described. This effect severely reduces the high-voltage capability of these devices when the gate field plate is extended through the drift region toward overlapping the n⁺drain contact region. The breakdown is shown to be due to an avalanche phenomenon appearing close to the n⁺region, due to the very high field induced in this NIOS structure in nonequilibrium. A first-order theory is developed to confirm the conclusions of the experimental study.     

LC-Tank Colpitts Injection-Locked Frequency Divider With Even and Odd Modulo

A new injection-locked frequency divider (ILFD) using a standard 0.18 $mu$m CMOS process is presented. The ILFD is based on a differential Colpitts voltage controlled oscillator (VCO) with a direct injection MOSFET for coupling an external signal to the resonators. The VCO is composed of two single-ended VCOs coupled with two transformers. Measurement results show that at the supply voltage of 1.4 V the divider's free-running frequency is tunable from 4.77 to 5.08 GHz, and the proposed circuit can function as a first harmonic injection-locked oscillator, divide-by-2, -3, and -4 frequency divider. At the incident power of 0 dBm the divide-by-2 operation range is from the incident frequency 7.7 to 11.5 GHz and the divide-by-4 operation range is from the incident frequency 18.9 to 20.2 GHz.      

高压直流电桥对电缆高阻击穿故障的定位

高压直流电桥具有定位精度高、操作简单、使用方便等优点,在电缆故障定位中得到广泛应用,但它要实现精确定位还依赖于知道故障电缆的准确长度,在一些电缆长度不明确且对路面开挖要求较严格的场合,高压直流电桥精确定位故障有相当大的困难。为此根据电容器反复充放电的特性,将GZD型高压直流电桥现场改造成简易高压脉冲发生器,可对电力电缆高阻击穿故障实现精确定位。     

High-voltage planar p-n junctions

A concentric ring junction has been devised to prevent surface breakdown of a planar junction. By properly choosing the spacing between the main junction and the ring, the ring junction acts like a voltage divider at the surface. In addition, the ring junction minimizes the effect of the junction curvature at the periphery of a planar junction. Devices fabricated with three such rings showed breakdown voltages of 2000 and 3200 volts on n-type silicon with impurity concentrations 6.5 × 10¹³and 2.5 × 10¹³cm^-3, respectively. That the structure operated as proposed was corroborated by comparison of the reverse leakage current with a one parameter fit to a theoretically calculated current obtained from the approximated volume of the space charge regions. These results together with the photo response measurements indicate that the field-limiting ring junction can be used successfully to obtain high-voltage planar p-n junctions.     

基于3 dB 定向耦合器的0.14 THz 功率分配器设计方法

介绍了一种基于3 dB 定向耦合器的0.14 THz 功率分配器设计方法。由于太赫兹频段的器件尺寸越来越小型化、微型化,特别是对于功率分配器中的核心结构,造成精密机械加工方式难以实现。典型的波导3 dB 定向耦合器结构是90电桥结构,其耦合缝隙之间的间距仅有不到0.5 mm,这样的尺寸是机加时产生的应力难以承受的。通过分析波导定向耦合器支路间的相位关系得出:如果耦合缝隙的间距增加到半波长的整数倍,支路间的相位差仍为90,但这样变化的结果是带宽的降低。通过耦合缝隙间距的适度增加,降低了机加的难度,工作相对带宽降到10%。经仿真分析,结果得到了验证。加工的样品测试结果表明,在0.133 ~0.147 THz 的频率范围内,插入损耗小于1 dB,回波损耗小于-20 dB。     

场板结构浅平面结高压器件

本文采用浅平面结制作场板结构高压器件，根据二维模拟器件击穿电压分析结果选择器件参数：深，场氧化层厚度，场板宽度和内部电极间距。结果，半绝缘钝化结构击穿电压的计算值与实验值相关较大，而绝缘层钝化结构的两者较接近。     

High-voltage solutions in CMOS technology

This paper presents trends on CMOS high-voltage techniques for power integrated circuits (PICs). Several fully CMOS compatible drain engineering techniques will be presented. Experimental devices were fabricated in standard CMOS processes from three different lithography generations (2, 0.7 and 0.5 μm) without resorting to any extra processing steps. MOS devices layout specificity towards performance improvement, namely breakdown, parasitic effects and degradation, will be emphasized.A recently developed technique used to enlarge high-voltage devices safe-operating area and reduce leakage current will also be presented due to the very promising experimental results.Comparison with more sophisticated and expensive technologies still reveals CMOS as a highly accessible and versatile technology for future PICs.     

Process and device design of a 1000-V MOS IC

High-voltage MOS devices and logic N-MOS circuits have been integrated on the same chip by using a silicon-gate isoplanar process that is compatible with present N-MOS LSI technology. The electrical characteristics of high-voltage MOS devices are modeled and characterized in terms of channel length, drift-layer length, drift-layer ion dose, and extended source field-plate effect. The theoretical calculations of on-resistanee, saturation drain current, and pinchoff voltage agree well with the experimental results. Based on the experimental and theoretical results, the device structure and the process parameters are optimized to obtain maximum drain saturation current with a low on-resistance and a drain breakdown of 1000 V. The optimized high-voltage MOS device can perform with a saturation drain current as high as 84 mA with an on-resistance as low as 300 Ω within an area of 520 µm × 1320 µm while maintaining a drain breakdown of 1000 V.     

Thermal stability and secondary breakdown in planar power MOSFET's

The destructive secondary-breakdown mechanism of high-voltage n-channel power MOSFET's is discussed. A model is proposed in which the secondary breakdown is caused primarily by the negative-resistance effects of a parasitic bipolar transistor structure. The model suggests that destructive breakdown can be suppressed by a new no-surface-breakdown structure fabricated on a p^-on p⁺epitaxial wafer. Power MOSFET's having this structure have been realized and are completely free from secondary breakdowns, as suggested by the model. In addition, experimental evidence for excellent thermal stability of the power MOSFET is given by infrared scanner measurements of the temperature rise in the chip compared with bipolar transistors. An n-channel planar power MOSFET with a 400-W power limitation at 220-V breakdown voltage and a maximum current of 12 A has been successfully fabricated.