Novel multilayering technique using folded flexible circuits

Multilayer circuit board technology offers the only feasible way to route high-density conductors through a narrow space. This technology has two limitations: the rigid multilayer circuit board typically used is not always compact enough for the application, and it is expensive. In this paper, we present a less expensive alternative that additionally achieves the required compactness: flexible circuits that are folded in a unique and organized pattern. Flexible circuits have the unique property of being three-dimensional (3-D), that can be shaped in multiplanar configurations and reinforced in specific areas for specific applications. Rearranging the two-dimensional layout of conductors on rigid circuit boards to the 3-D configuration of flexible circuits results in significant compactness. The compactness results from a structured folding of several parts in complementary directions, which allows intermediate portions to be stacked on each other. This technique also makes it possible to increase the conductor density on multilayer circuits by eliminating the need for electroplated holes called "vias." The final folded multilayer circuit is fabricated from a single flexible circuit comprising a series of foldable strips, rigid and flexible, which are interconnected, folded, and bonded into a composite structure. This folding greatly reduces the physical area occupied by the conductors associated with a planar circuit board by slightly increasing the thickness. The slightly increased thickness does not impinge on space needs for other purposes because ample space is available in the thickness dimension for heat to dissipate from the circuit board. In our application, we are able to save 67% of the unfolded area and additional saving is possible, depending on the application. The folded circuit can be bonded after the first fold, or folded subsequently to reduce its area further. It can then be bonded with glue as a composite multilayer structure.     

Non-destructive high-resolution characterization of buried interfaces for advanced interconnect and packaging architectures: Experiments and modeling

Characterization of buried interfaces in advanced interconnect and packaging structures is a critical challenge as complementary metal-oxide-semiconductor (CMOS) devices are scaled and as novel packaging and interconnect concepts and materials such as three-dimensional (3-D) circuits, and ultra-low dielectric constant insulators are developed. Critical information that needs to be obtained from such inspection includes detection of unbonded bumps in flip-chip packages; missing interconnections in bonded wafers and presence of delaminations in interconnect layers. In this paper, we discuss in detail our experimental and theoretical investigation of different non-destructive characterization techniques namely acoustic imaging, infra-red imaging and transient thermal microscopy to analyze and quantify the quality of buried interfaces. The imaging resolution is shown to critically depend on the material thickness through which the incident probe beam has to propagate to form the images. Defects in buried interfaces such as voids in bonded wafers appear as regions of bright contrast in acoustic imaging due to large acoustic impedance mismatch at the voids. In the case of transient thermal microscopy, unbonded areas will lead to non-uniform temperature distribution at the surface of the substrate when the sample is rapidly heated with a flash lamp. The localized temperature rise at the defect and its temporal evolution can be related in turn to the defect size. We discuss capabilities and limitations of the different techniques for inspection of buried interfaces with an emphasis on characterizing bonded interfaces for 3-D integrated circuits. It is shown that acoustic imaging with single spherical lens is better suited to study bond quality compared to thermal microscopy due to its better detection capabilities. Infra-red imaging was found to be unsuitable for investigation of bonded interfaces in wafers containing multiple layers of metallization.     

Wafer-scale 3D integration of InGaAs photodiode arrays with Si readout circuits by oxide bonding and through-oxide vias

A new wafer-scale three dimensional (3D) integration technique, originally developed for Si, is applied to hybridize InP-based photodiode arrays with Si readout circuits. The infrared (IR) photodiodes consisted of an InGaAs absorption layer grown on the InP substrate and were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits to allow 3D integration in the Si fabrication facility. The finished 150-mm-diameter InP wafer was directly bonded to the SOI wafer and interconnected to the Si readout circuits by through-oxide vias (TOV). A 32 × 32 array with 6-μm pixel size was demonstrated. The 3D integration of InP with Si wafers achieved the smallest pixel size, which is less than a half of that can be achieved using conventional flip-chip bump bonding technique.     

Operational-amplifier compilation with performance optimization

A method for designing analog circuits in which topological design is followed by simultaneous device sizing and layout design is described. By merging circuit and layout design into a single design process, analog circuits can be optimally designed taking layout parasitics fully into account. Using the method, a CMOS operational-amplifier compiler (OAC) has been developed. Given a set of performance specifications and process parameters, OAC generates a layout with circuit performance optimized to meet specified performance constraints. A procedural layout technique is employed to generate a compact and practical layout. A nonlinear optimization method for device sizing which relies on the results of simulations based on the circuit extracted from the layout is applied. Design experiments have shown that OAC can produce satisfactory results with respect to both circuit performance and layout density     

集成电路版图欧拉路径的快速判寻方法

版图欧拉路径法是实现集成电路版图面积最小化的常用方法.讨论了版图欧拉路径与布尔表达式的关系,提出一种版图欧拉路径快速判寻方法.利用该方法,设计了几种典型电路的版图欧拉路径,并运用集成电路设计软件设计其中一种电路,经过优化后的版图面积明显减小.该方法快速、准确、方便,具有广阔的应用前景.     

Self-consistent modeling of heating and MOSFET performance in 3-D integrated circuits

We present a new method for finding the temperature profile of vertically stacked three-dimensional (3-D) digital integrated circuits (ICs). Using our model, we achieve spatial thermal resolution at the desired circuit level, which can be as small as a single MOSFET. To resolve heating of 3-D ICs, we solve nonisothermal device equations self-consistently with lumped heat flow equations for the entire 3-D IC. Our methodology accounts for operational variations due to technology nodes (hardware: device), chip floor plans (hardware: layout), operating speed (hardware: clock frequency), and running applications (software). To model hardware, we first decide on an appropriate device configuration. We then calculate elements of the lumped thermal network using the 3-D IC layout. To include software, chip floor plan, and duty cycle-related performance variations, we employ a statistical Monte Carlo type algorithm. In this paper, we investigate performance of vertically stacked 3-D ICs, with each layer modeled after a Pentium III. Our calculated results show that layers within the stacked 3-D ICs, especially the ones in the middle, may greatly suffer from thermal heating.     

Effect of IC layout on the reliability of CMOS amplifiers

With shrinking device size and increasing circuit complexity, interconnect reliability has become the main factor that affects the integrated circuit (IC) reliability. Electromigration (EM) is the major failure mechanism for interconnect reliability. However, little research had been done on the effect of IC layout on the void nucleation time (i.e. the time where the vacancies in the metal gather and nucleate into a tiny void) in the interconnections of the circuits due to electromigration using 3D modeling. In this paper, we construct the 3D models for a CMOS class-AB amplifier and a RF low noise amplifier (LNA), and investigate the impact of layout design on the void nucleation time through the computation of the atomic flux divergence (AFD) of the 3D circuit models. From the simulation results we find that, there is a change in the value of the maximum total AFD with the change in the number of contacts or the inter-transistor distance. A change in the location of the maximum total AFD is observed in the LNA circuit with different finger number as a result of the change in the line width and the transistor rotation. This indicates a different reliability lifetime and void formation location with different layout designs.     

Semicustom Design Methodology of Power Gated Circuits for Low Leakage Applications

The application of power gating to cell-based semi- custom design typically calls for customized cell libraries, which incurs substantial engineering efforts. In this brief, a semicustom design methodology for power gated circuits that allows unmodified conventional standard-cell elements is proposed. In particular, a new power network architecture is proposed for cell-based power gating circuits. The impact of body bias on current switch design and the layout method of current switch for flexible placement are investigated. The circuit elements that supplement cell-based power gating design are then discussed, including output interface circuits and state retention flip-flops. The proposed methodology is applied to ISCAS benchmark circuits and to a commercial Viterbi decoder with 0.18-mum CMOS technology.     

Design methodology for full custom CMOS microcomputers

A highly structured design methodology is necessary to be successful in the design of VLSI integrated circuits with more than 100000 transistors on a chip. Such a methodology is described: it is based on the regularity of the circuit architecture with an associated chip floor plan and on a new layout technique named metal oriented layout.This methodology has been tested with the design of a 13500 MOS microcomputer. From the instruction set and through different levels of instruction interpretation, the architecture and associated chip floor plan are generated. The detailed logic design is made directly in symbolic layout with the chip floor plan in mind.The proposed design methodology can be best appreciated by the short development time and small chip area required for the designed 13500 MOS microcomputer.     

Analysis of the impact of proximity correction algorithms oncircuit performance

Variation in channel length degrades circuit reliability and yield. A common way to compensate for this problem is to increase the mean channel length, which, unfortunately, degrades circuit performance for digital circuits. One source of channel length variation is lithography, during which the line width is influenced by local layout patterns. It is possible to compensate for this effect by resizing transistor gates appropriately on the mask. However, the effectiveness of the correction is limited by constraints such as the mask correction resolution. To determine how to design a good correction scheme with limited resources, we have developed a method to compare different correction algorithms in terms of their impact on the performance of one of the main functional blocks in a state-of-the-art microprocessor. In particular, to evaluate correction algorithms while avoiding the high cost associated with generating multiple mask sets and fabricating product wafers with each of these mask sets, we present a method for predicting the correction results using simulation. Our methodology involves a DRC-based approach for gate resizing, along with critical path simulation for evaluating circuit performance. In-line CD measurement data were used to measure the impact of the proximity effect on transistor channel length. Electrical test results were used to calibrate the device models for circuit simulation     

MASHER: An automatic VLSI layout system

This paper describes a system for the automatic layout of VLSI circuits designed using Path Programmable Logic (PPL) methodology. A formal model has been developed which serves as a framework for the manipulation of PPL circuits. This model supports two basic operations: wire folding and wire splitting. User specified constraints guide the PPL layout process. External wires, those which reach outside of the circuit, may be routed to a particular edge, ordered, or placed adjacently. Heuristics are used to select folds. A heuristic has been developed which chooses those folds which place the fewest restrictions on the circuit. The MASHER system has been fully implemented and a number of real circuits have been laid out. Examples are presented comparing MASHER layouts with both hand layouts and other computer generated layouts.     

Maximizing the Functional Yield of Wafer-to-Wafer 3-D Integration

Three-dimensional integrated circuit technology with through-silicon vias offers many advantages, including improved form factor, increased circuit performance, robust heterogenous integration, and reduced costs. Wafer-to-wafer integration supports the highest possible density of through-silicon vias and highest throughput; however, in contrast to die-to-wafer integration, it does not benefit from the ability to bond only tested and diced good die. In wafer-to-wafer integration, wafers are entirely bonded together, which can unintentionally integrate a bad die from one wafer to a good die from another wafer reducing the yield. In this paper, we propose solutions that maximize the yield of wafer-to-wafer 3-D integration, assuming that the individual die can be tested on the wafers before bonding. We exploit some of the available flexibility in the integration process, and propose wafer assignment algorithms that maximize the number of good 3-D ICs. Our algorithms range from scalable, fast heuristics to optimal methods that exactly maximize the yield of wafer-to-wafer 3-D integration. Using realistic defect models and yield simulations, we demonstrate the effectiveness of our methods up to large numbers of wafer stacks. Our results demonstrate that it is possible to significantly improve the yield in comparison to yield-oblivious wafer assignment methods.      

Yield modeling based on in-line scanner defect sizing and acircuit's critical area

Wafers containing a large number of defects on any layer should be discarded in order to avoid the cost associated with processing wafers that are unlikely to yield. Normally decisions about scrapping wafers are based on defect counts. However, including the size of defects can improve the accuracy of such dispositions. If the size of defects is taken into account, critical area provides an estimate of the kill ratio associated with defects of a given size, where the critical area of a layer of a circuit is computed from a circuit's layout. In this paper, the accuracy of the sizing of defects by in-line scanners is analyzed. Then, the impact of defect sizing inaccuracy on estimates of layer yield is discussed, and a methodology to more accurately compute layer yield and kill ratios is presented, which calibrates for inaccuracy in defect sizing by in-line scanners     

Circuit layout

This paper gives a general overview of circuit layout, taking a unified approach to various styles of integrated circuits, printed circuit boards, and hybrid circuits. A lot of attention is given to the layout of large and complicated circuits, in particular, to the layout of very-large-scale-integration (VLSI) chips. Though the paper is an overview, and one could almost say a tutorial, it is intended for readers with some basic knowledge of what a circuit layout is and what some of the basic problems are. The main subjects discussed are: assignment of gates, placement methods, loose routing, final routing, and problems associated with the implementation of a hierarchical system. The emphasis is on new, not widely published methods, and on methods that seem to have potential for solving some of the current problems. Practical examples illustrate this rather personal account of circuit layout and sugsest where we may go from here.     

信号流驱动的模拟电路版图综合方法

提出了一种新的基于信号流分析的模拟电路版图综合方法.电路分析子系统采用新提出的信号流分析方法再结合已有的电路拓扑分析和电路灵敏性分析方法生成布图约束控制电路性能的衰减.由于考虑了电路中有关信号流的启发式信息,该方法的复杂性较一般的纯粹性能驱动方法小.然后分别在器件生成子系统、布图子系统和布线子系统中实现这些约束,使得这些约束在最容易实现的阶段得到满足.实际的电路例子已经证明了这一方法可以获得出色的电路性能.     

An ant colony based mapping of quantum circuits to nearest neighbor architectures

Although this decade is witnessing tremendous advancements in fabrication technologies for quantum circuits, this industry is facing several design challenges and technological constraints. Nearest Neighbor (NN) enforcement is one such design constraint that demands the physical qubits to be adjacent. In the last couple of years, this domain has made progress starting from designing advanced algorithms to improved synthesis methodologies, even though developing efficient design solutions remains an active area of research.Here, we propose such a synthesis technique that efficiently transforms quantum circuits to NN designs. To find the NN solution, we have taken help of an ant colony algorithm which completes the circuit conversion in two phases: in the first phase, it finds the global qubit ordering for the input circuit and, in the second phase, a heuristic driven look-ahead scheme is executed for local reordering of gates. The proposed algorithm is first fitted into a 1D design and, later, mapped to 2D and 3D configurations. The combination of such heuristic and the meta-heuristic schemes has resulted promising solutions in the transformation of quantum circuits to NN-compliant architectures. We have tested our algorithm over a wide spectrum of benchmarks and comparisons with state-of-the-art design approaches showed considerable improvements.     

A Signal-Flow Driven Automatic Physical Synthesis Methodology for Analog Circuits

This paper introduces a novel automatic physical synthesis methodology for analog circuits based on the signal-flow analysis.Circuit analysis sub-system adopts the newly advanced methodology,circuit topology analysis,and circuit sensitivity analysis to generate layout constraints and control performance degradations.Considering the heuristic information about signalflow，complexity of the methodology is less than the pure performance-driven methodology.And then these constraints are implemented in device generation,placement，and routing sub-systems separately,which makes the different constraints be satisfied at most easily implemented stages.Excellent circuit performance obtained by the methodology is demonstrated by practical circuit examples.     

Analysis of Manufacturability Factors for Analog CMOS ADC Building Blocks

In this paper, the layout of analog CMOSintegrated circuits is considered as one of the mostimportant manufacturability factors. Various layoutdesign styles are introduced and applied to the physicaldesign of latched comparators and A/D converter buildingblocks. In the following examination, post-layoutsimulation results are discussed and compared withmeasurement of the A/D circuits that were fabricated in a0.35 m digital CMOS process. It is shown in thispaper that different circuit layout styles can result insignificant differences in circuit performance.Additionally, it is shown that the layout-relatedperformance variability is attributed to statisticalprocessing variations.     

三维集成电路中TSV的热特性研究

基于Comsol Multiphysics平台,通过使用有限元仿真对三维集成电路的硅通孔(TSV)模型进行了热仿真分析。分别探究了TSV金属层填充材料及TSV的形状、结构、布局和插入密度对三维(3D)集成电路TSV热特性的影响。结果表明:TSV金属层填充材料的热导率越高,其热特性就越好,并且采用新型碳纳米材料进行填充比采用传统金属材料更能提高3D集成电路的热可靠性;矩形形状的TSV比传统圆形形状的TSV更有利于3D集成电路散热;矩形同轴以及矩形双环TSV相比其他结构TSV,更能提高TSV的热特性;TSV布局越均匀,其热特性越好;随着TSV插入密度的增加,其热特性越好,当插入密度达6%时,增加TSV的数目对TSV热特性的影响将大幅减小。