Gate leakage properties of MOS devices with tri-layer high-k gate dielectric

Gate leakage of deep-submicron MOSFET with stack high-k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked when it is used for MOSFET with SiO₂ and high-k dielectric material as gate dielectrics, respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO₂/HfSiON with a U-shape nitrogen profile and a like-Si/SiO₂ interface, which is proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high-k dielectric. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5-nm HfO₂ and 1.2-nm HfSiON exhibits the lowest gate leakage.     

Temperature dependence of gate induced drain leakage current insilicon CMOS devices

The temperature dependence of the gate induced drain leakage (GIDL) current in CMOS devices is investigated from 20K up to 300K. It is shown that, at sufficiently high electric field, the conventional band-to-band tunnelling GIDL current law is applicable down to near-liquid helium temperatures for both nand p-channel devices. The exponential factor B of the GIDL current law is found to be nearly independent of temperature. Moreover, the decrease of the GIDL current as the temperature is lowered, is shown to originate from the temperature variation of the pre-exponential coefficient A of the GIDL current law     

A review of gate tunneling current in MOS devices

Gate current in metal–oxide–semiconductor (MOS) devices, caused by carriers tunneling through a classically forbidden energy barrier, is studied in this paper. The physical mechanisms of tunneling in an MOS structure are reviewed, along with the particularities of tunneling in modern MOS transistors, including effects such as direct tunneling, polysilicon depletion, hole tunneling and valence band tunneling and gate current partitioning. The modeling approach to gate current used in several compact MOS models is presented and compared. Also, some of the effects of this gate current in the performance of digital, analog and RF circuits is discussed, and it is shown how new effects and considerations will come into play when designing circuits that use MOSFETs with ultra-thin oxides.     

Atomic-layer-deposited tantalum silicate as a gate dielectric for III-V MOS devices

TaSiO_x thin films with Si/(Ta + Si) mole fractions between 0 and 0.6 have been deposited using atomic-layer deposition on Si and InGaAs at 250 °C. Interface defects on InGaAs were on the order of 10¹² cm⁻² eV⁻¹, which is comparable to state-of-the-art Al₂O₃ deposited by atomic-layer deposition using Al(CH₃)₃ and H₂O while the dielectric permittivity of TaSiO_x is considerably higher.     

An analysis of equivalent circuit with gate protection in MOS devices

The dependence of the resistance associated with the equivalent circuit with gate protection on the electrical breakdown voltage was analyzed in terms of the transient solution of the equivalent circuit. The series resistance for the input voltage and the dynamic resistance in the breakdown region of the protective diode are found to have pronounced effects on the electrical breakdown voltage of the gate oxide, while the distributed resistance has a lesser effect on it.     

Physical and electrical characteristics of HfN gate electrode for advanced MOS devices

In this letter, the physical and electrical properties of physical vapor deposited (PVD) hafnium nitride (HfN) is studied for the first time as the metal gate electrode for advanced MOS devices applications. It is found that HfN possesses a midgap work function in tantalum nitride (TaN)/HfN/SiO/sub 2//Si MOS structures. TaN/HfN stacked metal-gated MOS capacitors exhibit negligible variations on equivalent oxide thickness (EOT), leakage current, and work function upon high-temperature treatments (up to 1000 /spl deg/C), demonstrating the excellent thermal stability of HfN metal gate on SiO/sub 2/. Our results suggest that HfN metal electrode is an ideal candidate for the fully depleted SOI and/or symmetric double gate MOS devices application.     

Transformerless capacitive coupling of gate signals for seriesoperation of power MOS devices

A reliable configuration for triggering a series string of power metal oxide semiconductor (MOS) devices without the use of transformer coupling is presented. A capacitor is inserted between the gate and ground of each metal oxide semiconductor field effect transistor (MOSFET), except for the bottom MOSFET in the stack. Using a single input voltage signal to trigger the bottom MOSFET, a voltage division across the network of device capacitance and inserted capacitances triggers the entire series stack reliably. Design formulas are presented and simple circuit protection is discussed. Simulation shows reliable operation and experimental verification is presented, Application of the method is applied to series insulated gate bipolar transistors (IGBTs)     

Plasma charging damage on MOS devices with gate insulator ofhigh-dielectric constant material

Plasma charging effects on the gate insulator of high-dielectric constant (k) material in MOS devices deserve to be investigated because of different trap-assisted conduction mechanisms. Plasma-induced degradation in gate-leakage current and time to breakdown is clearly observed in this work. MOS device with Si₃N₄ film seems to have smaller degradation of gate-leakage current while it suffers shorter time to breakdown as compared to Ta₂O₅ samples. For devices with Ta₂O₅ film, a larger physical thickness suffers more reliability degradation from plasma charging damage because of the richer traps. Thus, a smaller physical thickness of high-k dielectric film is favorable for sub-micron MOS devices of ULSI application     

Simplified quantitative stress-induced leakage current (SILC) model for MOS devices

A simplified quantitative model for the steady-state component of stress-induced leakage current (SILC) in MOS capacitors with ultrathin oxide layers has been developed by assuming a two-step inelastic trap-assisted tunneling (ITAT) process as the conduction mechanism. By using our model, we reduced the time of numerical calculations of SILC to 17% of the standard method while maintaining a high accuracy of the results. We also confirmed that the SILC component must not be neglected when calculating the gate current in modern devices, especially at low fields. Our simplified model helped us to investigate the dependence of SILC on the oxide field and the oxide thickness. We also shed some light on the reasons that cause the peak in the SILC–oxide thickness relation.     

Annealing of radiation-induced positive charge in MOS devices with aluminum and polysilicon gate contacts

This paper discusses the removal of radiation-induced positive charge from MOS structures by low temperature thermal anneals. Results are presented for structures in which the gate oxide is covered either by an aluminum or by a polysilicon contact during the anneal. The anneals were performed in forming gas, nitrogen and hydrogen ambients. The presence of aluminum over the gate oxide is found to play an important role in the annealing of radiation-induced positive charge in these structures . While a 400?C anneal is sufficient to remove this charge from capacit or structures with aluminum gates, it leaves a small amount of residual charge (about 6xl0¹⁰}cm²}) in structures with polysilicon gates. Anneals at temperatures in excess of 550?C are required to remove this charge completely from the polysilicon-gated MOS devices. However when a thin layer of aluminum is present over the polysilicon contact during the anneal the charge can be removed easily at 400?C. The results in capacitor structures are consistent with those found in polysilicon gate MOSFET’s with similar coverage over the gate oxide.     

The electron irradiation effects on silicon gate dioxide used for power MOS devices

The work provides experimental results of high energy electron irradiation effects on silicon dioxide used for power MOS devices. A systematic increase of the threshold voltage has been observed in irradiated IGBT and VDMOS devices processed on Si1 0 0 and Si1 1 1, respectively. The threshold voltage shift has been interpreted as a result of the accumulated charge in the gate oxide. Single event gate rupture has been observed and attributed to the recoil ion interaction with the gate SiO₂. The result has been corroborated by reliability stress tests. After electron irradiation, an increase in breakdown voltage appeared on all devices which was attributed to a change in the surface impact ionisation coefficient. The change is most notable in devices processed on Si substrate with 1 1 1 orientation.     

Accumulation gate capacitance of MOS devices with ultrathin high-/spl kappa/ gate dielectrics: modeling and characterization

A quantum-mechanical (QM) model is presented for accumulation gate capacitance of MOS structures with high-/spl kappa/ gate dielectrics. The model incorporates effects due to penetration of wave functions of accumulation carriers into the gate dielectric. Excellent agreement is obtained between simulation and experimental C-V data. It is found that the slope of the C-V curves in weak and moderate accumulation as well as gate capacitance in strong accumulation varies from one dielectric material to another. Inclusion of penetration effect is essential to accurately describe this behavior. The physically based calculation shows that the relationship between the accumulation semiconductor capacitance and Si surface potential may be approximated by a linear function in moderate accumulation. Using this relationship, a simple technique to extract dielectric capacitance for high-/spl kappa/ gate dielectrics is proposed. The accuracy of the technique is verified by successfully applying the method to a number of different simulated and experimental C-V characteristics. The proposed technique is also compared with another method available in the literature. The improvements made in the proposed technique by properly incorporating QM and other physical effects are clearly demonstrated.     

On threshold and flat-band voltages for MOS devices with polysilicon gate and nonuniformly doped substrate

Expressions for the flat-band voltage V_FB and threshold voltage V_T for MOS devices with polysilicon gate and nonuniformly doped substrate are given. The role of metal-semiconductor contacts and the assumptions involved in the analysis are discussed. Both V_FB and V_T have three extra terms over the conventional expressions, two terms result from nonuniform doping and one is due to a voltage drop in the gate produced by space charge. Contrasts are made to devices with metal gates and uniformly doped substrates. The commonly used expression for mobile channel charge in terms of gate voltage is clarified.     

Impact of gate induced drain leakage on overall leakage ofsubmicrometer CMOS VLSI circuits

In this paper, the impact of gate induced drain leakage (GIDL) on the overall leakage of submicrometer VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down complimentary metal-oxide-semiconductor (CMOS) devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in scaled CMOS digital VLSI circuits. We present the experimental and simulation data of GIDL current as a function of 0.35-μm CMOS technology parameters and layout of CMOS standard cells. The obtained results show that a poorly designed standard cell library for VLSI application may result in extremely high leakage current and poor yield     

Modeling study of ultrathin gate oxides using direct tunnelingcurrent and capacitance-voltage measurements in MOS devices

Using both quantum mechanical calculations for the silicon substrate and a modified WKB approximation for the transmission probability, direct tunneling currents across ultra-thin gate oxides of MOS structures have been modeled for electrons from the inversion layers in p-type Si substrates. The modeled direct tunneling currents have been compared to experimental data obtained from nMOSFET's with direct tunnel gate oxides. Excellent agreement between the model and experimental data for gate oxides as thin as 1.5 nm has been achieved. Advanced capacitance-voltage techniques have been employed to complement direct tunneling current modeling and measurements. With capacitance-voltage (C-V) techniques, direct tunneling currents can be used as a sensitive characterization technique for direct tunnel gate oxides. The effects of both silicon substrate doping concentration and polysilicon doping concentration on the direct tunneling current have also been studied as a function of applied gate voltage     

Thermal annealing effect on electrical properties of metal nitride gate electrodes with hafnium oxide gate dielectrics in nano-metric MOS devices

Electrical properties of hafnium oxide (HfO₂) gate dielectric with various metal nitride gate electrodes, i.e., tantalum nitride (TaN), molybdenum nitride (MoN), and tungsten nitride (WN), were studied over a range of HfO₂ thicknesses, e.g., 2.5-10 nm, and post-metal annealing (PMA) temperatures, e.g., 600 °C to 800 °C. The work function of the nitride gate electrode was dependent on the material and the post-metal annealing (PMA) temperature. The scanning transmission electron microscopy technique is used to observe the effect of PMA on the interfacial gate dielectric thickness. After high-temperature annealing, the metal nitride gates were suitable for NMOS. At the same PMA temperature, the oxide-trapped charges increased and the interface state densities decreased with the increase of the HfO₂ thickness for TaN and WN gate electrodes. However, for MoN gate electrode the interface state density is almost independent of film thickness. Therefore, dielectric properties of the HfO₂ high-k film depend not only on the metal nitride gate electrode material but also the post-metal annealing condition as well as the film thickness. During constant voltage stress of the MOS capacitors, an increase in the time-dependent gate leakage current is also observed.     

On the thermal stability of atomic layer deposited TiN as gate electrode in MOS devices

The work function of ALD TiN was found to be above 5 eV after RTP annealing below 800/spl deg/C in a nitrogen atmosphere, while higher annealing temperatures cause a drop in work function by about 0.3-0.5 eV. The effect was found for TiN metal gates on both SiO/sub 2/ and Al/sub 2/O/sub 3/ gate dielectrics in MOS-capacitors and was seen in C-V as well as in I-V measurements. On the contrary, annealing of SiO/sub 2/ capacitors in oxygen-enriched N/sub 2/ atmosphere increased the work function. A variation in EOT of less than 2 A was demonstrated for the various annealing temperatures, concluding that the ALD TiN is stable in contact with the different dielectric materials. However, the decrease in work function that is found in this investigation may implicate that ALD TiN is less suitable as a metal gate for pMOSFETs.     

Threshold-alterable Si-gate MOS devices

An electrically threshold-alterable n-channel MOS device with polysilicon gate is experimentally realized by employing a polysilicon-oxynitride-nitride-oxide-silicon (SONOS) structure. Because of several high-temperature processing steps after the nitride deposition, it was found necessary to increase the thin-oxide thickness of the SONOS devices in order to achieve better charge retentivity. It has been shown that the SONOS device can be used in MOS integrated circuits. Some memory and switching characteristics of the SONOS devices with oxide thickness of ∼30 Å are presented.     

Radiation resistant MOS devices

A detailed study indicates that the radiation resistance of MOS transistors is controlled by the details of technology. It has been found that an MOS structure can be created that remains operational for gamma doses above 10⁷rad. It will be shown how the radiation resistance varies with gate oxidation and the metals employed. Two metals were used in the experiments: aluminum and chromium. The interrelationship between radiation and thermal stability will also be discussed. It will be shown that there is some connection between the two as long as the same basic technology is used. It is possible however, that combinations that result in thermal stability can still show a low radiation resistance. The radiation generates positive-charge centers in the oxide and these centers are related to "minor" bonds in the oxide. In this respect, the oxide-metal interactions have been considered. It follows from our studies that the greatest radiation resistance will be found forp-enhancement devices and for certainn-depletion structures. The measurements will show results forP-enhancement units with radiation resistance one-hundred times greater than previously reported figures, both for MOS and bipolar transistros.     

A model of the stress induced leakage current in gate oxides

A new quantitative model of the stress induced leakage current (SILC) in MOS capacitors with thin oxide layers has been developed by assuming the inelastic trap-assisted tunneling as the conduction mechanism. The oxide band structure has been simplified by replacing the trapezoidal barrier with two rectangular barriers. An excellent agreement between simulations and experiments has been found by adopting a trap distribution Gaussian in space and in energy. Only minor variations of the trap distribution parameters were observed by increasing the injected charge during electrical stress, indicating that oxide neutral defects with similar characteristics are generated at any stage of the stress