Design of anti-jamming current-sensing circuit for current-mode buck regulator

A novel anti-jamming integrated CMOS current-sensing circuit for current-mode buck regulators is presented.Based on the widely-used traditional current-sensing structure,anti-jamming performance is improved significantly by adding on-chip capacitors and one-shot circuit.Also the transient response is faster through the introduction of current offset.The circuit iS concise,simple to implement and suits for SoC applications with single power supply.A dual-output current-mode DC-DC buck converter with proposed structure has been fabricated with a 0.5μm CMOS process for validation.In the 2.5-5.5 V input range,the two channels work steadily in the load current range of 0-600 mA.And the measured maximum efficiency is up to 96%.     

电流模降压变换器抗干扰电流采样电路设计

A novel anti-jamming integrated CMOS current-sensing circuit for current-mode buck regulators is presented. Based on the widely-used traditional current-sensing structure, anti-jamming performance is improved significantly by adding on-chip capacitors and one-shot circuit. Also the transient response is faster through the introduction of current offset. The circuit is concise, simple to implement and suits for SoC applications with single power supply. A dualoutput current-mode DC-DC buck converter with proposed structure has been fabricated with a 0.5 μm CMOS process for validation. In the 2.5–5.5 V input range, the two channels work steadily in the load current range of 0–600 mA. And the measured maximum efficiency is up to 96%.     

一款电流型控制的DC／DC降压转换器

本文提出一种新型电感电流检测电路,该检测电路不需要一个放大器作为电压镜像,从而使用的器件更少,功耗更低。该电感电流检测电路应用于DC／DC降压转换器,采用CSM 0．18μm CMOS工艺进行设计和仿真,仿真结果显示该电感电流检测电路的精度可达到96％,输出电压的纹波仅为1mV。     

On-chip CMOS current-sensing circuit for DC-DC buck converter

An on-chip CMOS current-sensing circuit for a DC-DC buck converter is presented. The circuit can measure the inductor current through sensing the voltage of the switch node during the converter on-state. By matching the MOSFETs, the achieved sense ratio is almost independent of temperature, model and supply voltage. The proposed circuit is suitable for low power DC-DC applications with high load current.     

A high-efficiency,low-noise power solution for a dual-channel GNSS RF receiver

A high-efficiency low-noise power solution for a dual-channel GNSS RF receiver is presented.The power solution involves a DC-DC buck converter and a followed low-dropout regulator(LDO).The pulsewidth -modulation(PWM) control method is adopted for better noise performance.An improved low-power highfrequency PWM control circuit is proposed,which halves the average quiescent current of the buck converter to 80μA by periodically shutting down the OTA.The size of the output stage has also been optimized to achieve high efficiency under a light load condition.In addition,a novel soft-start circuit based on a current limiter has been implemented to avoid inrush current.Fabricated with commercial 180-nm CMOS technology,the DC-DC converter achieves a peak efficiency of 93.1%under a 2 MHz working frequency.The whole receiver consumes only 20.2 mA from a 3.3 V power supply and has a noise figure of 2.5 dB.     

A novel winding-coupled buck converter for high-frequency, high-step-down DC-DC conversion

This paper analyzes the fundamental limitations of the buck converter for high-frequency, high-step-down dc-dc conversion. Further modification with additional coupled windings in the buck converter yields a novel topology, which significantly improves the efficiency without compromising the transient response. An integrated magnetic structure is proposed for these windings so that the same magnetic cores used in the buck converter can be used here as well. Furthermore, it is easy to implement a lossless clamp circuit to limit the device voltage stress and to recover inductor leakage energy. This new topology is applied for a 12V-to-1.5V/25A voltage regulator module (VRM) design. At a switching frequency of 2MHz, over 80% full-load efficiency is achieved, which is 8% higher than that of the conventional buck converter.     

基于LM5117P的降压型直流开关稳压电源设计

降压型直流开关稳压电源是一种单向DC-DC变换器,实现稳定直流降压功能.本系统采用同步降压控制器LM5117P作为电路控制核心,以同步Buck电路作为降压主电路,通过闭环回路反馈设计以及芯片本身的精准采样,将输入电压16V降为5V恒压输出.     

一种用于高压降压型转换器的高精度强驱动能力驱动电路

This paper presents a novel driving circuit for the high-side switch of high voltage buck regulators.A 40 V P-channel lateral double-diffused metal–oxide–semiconductor device whose drain–source and drain–gate can resist high voltage, but whose source–gate must be less than 5 V, is used as the high-side switch. The proposed driving circuit provides a stable and accurate 5 V driving voltage for protecting the high-side switch from breakdown and achieving low on-resistance and simple loop stability design. Furthermore, the driving circuit with excellent driving capability decreases the switching loss and dead time is also developed to reduce the shoot-through current loss. Therefore, power efficiency is greatly improved. An asynchronous buck regulator with the proposed technique has been successfully fabricated by a 0.35 m CDMOS technology. From the results, compared with the accuracy of16.38% of the driving voltage in conventional design, a high accuracy of 1.38% is achieved in this work. Moreover,power efficiency is up to 95% at 12 V input and 5 V output.     

A Low-Dropout Regulator for SoC With Q-Reduction

A low-dropout regulator for SoC, with an advanced Q-reduction circuit to minimize both the on-chip capacitance and the minimum output-current requirement down to 100 muA, is introduced in this paper. The idea has been implemented in a standard 0.35-mum CMOS technology (V_THN ap 0.55 V and |V_THP| ap 0.75 V). The required on-chip capacitance is reduced to 6 pF, comparing to 25 pF for the case without Q-reduction circuit. From the experimental results, the proposed regulator-circuit implementation enables voltage regulation down to a 1.2-V supply voltage, and a dropout voltage of 200 mV at 100-mA maximum output current     

A dual-mode fast-transient average-current-mode buck converter without slope-compensation

A dual-mode fast-transient average-current-mode buck converter without slope-compensation is proposed in this paper. The benefits of the average-current-mode are fast-transient response, simple compensation design, and no requirement for slope-compensation, furthermore, that minimizes some power management problems, such as EMI, size, design complexity, and cost. Average-current-mode control employs two loop control methods, an inner loop for current and an outer one for voltage. The proposed buck converter using the current-sensing and average-current-mode control techniques can be stable even if the duty cycle is greater than 50%. Also, adaptively switch between pulse-width modulation (PWM) and pulse-frequency modulation (PFM) is operated with high conversion efficiency. Under light load condition, the proposed buck converter enters PFM mode to decrease the output ripple. Even more, switching PWM mode realizes a smooth transition under heavy load condition. Therefore, PFM is used to improve the efficiency at light load. Dual-mode buck converter has high conversion efficiency over a wide load conditions. The proposed buck converter has been fabricated with TSMC 0.35 μm CMOS 2P4M processes, the total chip area is 1.45×1.11 mm². Maximum output current is 450 mA at the output voltage 1.8 V. When the supply voltage is 3.6 V, the output voltage can be 0.8-2.8 V. Maximum transient response is less than 10 μs. Finally, the theoretical analysis is verified to be correct by simulations and experiments.     

A 95 nA quiescent current hysteretic mode buck converter with sample and hold reference

A nano ampere (nA) hysteretic mode buck converter is presented in this paper. Nano ampere current sleep phase and fast response burst phase are implemented. The converter achieves nano-watt power consumption in sleep phase while ensures fast wake-up from sleep phase to burst phase. New developed ultra low power sample-hold voltage reference and 1 kHz oscillator draw currents of 20 and 10 nA respectively. The circuit was implemented in a 0.35 μm CMOS process. The measurement result shows that the converter’s quiescent current (Iq) in sleep phase is as low as 95 nA. Benefit from the ultra-low Iq, the circuit achieves conversion efficiency of 79.8% at 2 μA load, regulating output at 2.5 V with a 3.6 V supply. The peak efficiency is up to 94% at 50 mA load.     

A feedback loop regulated bootstrap driver circuit with improved drive capability for high voltage buck DC–DC converter

A novel bootstrap driver circuit applied to high voltage buck DC–DC converter is proposed. The gate driver voltage of the high side switch is regulated by a feedback loop to obtain accurate and stable bootstrapped voltage. The charging current of bootstrap capacitor is provided by the input power of the DC–DC converter directly instead of internal low voltage power source, so larger driver capability of the proposed circuit can be achieved. The bootstrap driver circuit starts to charge the bootstrap capacitor before the switch node SW drop to zero voltage at high-side switch off-time. Thus inadequate bootstrap voltage is avoided. The proposed circuit has been implemented in a high voltage buck DC–DC converter with 0.6 µm 40 V CDMOS process. The experimental results show that the bootstrap driver circuit provides 5 V stable bootstrap voltage with higher drive capability to drive high side switch. The proposed circuit is suitable for high voltage, large current buck DC–DC converter.     

A 200-mA, 93% peak power efficiency, single-inductor, dual-output DC–DC buck converter

A single-inductor dual-output (SIDO) DC–DC buck converter is presented. The circuit uses only one (external) inductor to provide two independent output voltages ranging from 1.2 V to the power supply (2.6–5 V) with a maximum total output current of 200 mA. The proposed converter has been fabricated in a 0.35-μm p-substrate CMOS technology. Measurement results demonstrate that a peak power efficiency as high as 93.3% can be achieved. An automatic substrate bias switch technique, that cancels the body effect of the p-channel output power transistors, improves the converter power efficiency performance.     

Integrated current-mode DC–DC boost converter with high-performance control circuit

In this paper, integrated BiCMOS amplifier and current-sensing circuits are introduced for high-performance DC–DC boost converter. By exploiting the advantage of BiCMOS technology, the high gain amplifier and accurately sensed inductor current are obtained in the feedback control circuit. The proposed current-sensing circuit adopts a current-mirror instead of op-amplifier as a voltage follower so that it would reduce power consumption with a smaller chip-size. Bipolar transistor is also applied in the differential pair and current sources of the error amplifier to obtain a fast transient response. Frequency response shows the amplifier gain with the compensator affects significantly on the stability of the converter. The chip is fabricated in 0.35 µm 2-poly 4-metal BiCMOS process. The measurement shows that the current-sensing circuit can operate with accuracy of higher than 90 % at the frequency from 10 to 200 kHz and the transient time of the error amplifier is controlled within 10 µs. The converter with chip-size of 1 mm² operates at the output voltage of 4.5–9 V with the frequency of 0.01–1 MHz.     

250 mV Supply Voltage Digital Low‐Dropout Regulator Using Fast Current Tracking Scheme

This paper proposes a 250 mV supply voltage digital low‐dropout (LDO) regulator. The proposed LDO regulator reduces the supply voltage to 250 mV by implementing with all digital circuits in a 0.11 μm CMOS process. The fast current tracking scheme achieves the fast settling time of the output voltage by eliminating the ringing problem. The over‐voltage and under‐voltage detection circuits decrease the overshoot and undershoot voltages by changing the switch array current rapidly. The switch bias circuit reduces the size of the current switch array to 1/3, which applies a forward body bias voltage at low supply voltage. The fabricated LDO regulator worked at 0.25 V to 1.2 V supply voltage. It achieved 250 mV supply voltage and 220 mV output voltage with 99.5% current efficiency and 8 mV ripple voltage at 20 μA to 200 μA load current.     

DC-DC降压芯片使能保护电路的设计

文中主要对DC-DC降压芯片电路进行研究,重点设计了使能保护电路模块。该电路模块设计了1.5 V和2.5 V两个比较电压点。当UEN小于1.5 V,整个芯片关断。当UEN超过1.5 V但小于2.5 V时,电源供电正常。当使能UEN大于2.5 V后,整个芯片正常工作。电路采用CMSC1μm5 V/40 V HVCMOS工艺中的5 V低压器件来构建,并在Cadence软件下进行了仿真验证。     

A New Monolithic Fast-Response Buck Converter Using Spike-Reduction Current-Sensing Circuits

A new monolithic fast-response buck converter using spike-reduction current-sensing circuits is proposed in this paper. The proposed converters are designed and implemented with TSMC 0.35-mum DPQM CMOS processes. The operation frequency can be up to 1.887 MHz. The response time is only 2 mus and compared with other references. The maximum output current is 750 mA, and the maximum power efficiency can be up to 89.1% at 2.442-W output power. The chip area is only 2.157 mm².     

降压/升压DC-DC转换器四开关控制方法

便携式电子应用设备常常要求它的系统电压,介于电池充分充电的电压和未充分放电的电压范围之间。比如,对于锂离子电池,当输入为2．8伏到4．2伏时,输出为3．3伏。达到这种要求最佳的解决方法就是高效率、同相的四开关拓扑结构的降压／升压DC-DC转换器,这种方法利用一种控制方案,它可以实现降压、降压／升压、升压三种模式自动并且平稳地转换。经HSPICE仿真,采用Hynix0．5um 5VCMOS工艺,在输入电压2．5～5．5V、输出电压3．3V、频率1MHz时,效率高达95％以上。是输出电压处于电池电压范围内的单节锂离子电池、多节碱性电池或NiMH电池应用的理想选择,解决了在便携式电子设备电源设计过程中所遇到的问题。     

A voltage-mode PWM buck regulator with end-point prediction

The end-point prediction (EPP) scheme for voltage-mode buck regulators is proposed. Internal nodal voltages of the regulator controller are predicted and set automatically by the proposed algorithms and circuits. The settling time of the regulator can therefore be significantly reduced for faster dynamic responses, even with dominant-pole compensation. Proven experimentally by a voltage-mode buck regulator implemented in a 0.35-/spl mu/m CMOS technology, the reference-tracking speed using the EPP scheme is faster than the conventional buck regulator by about six times.     

A multiple-output switched-capacitor DC–DC converter for individual brightness control of RGB LEDs with time-interleaved control and output current regulation

In this paper, an integrated multiple-output switched-capacitor (SC) converter with time-interleaved control and output current regulation is presented. The SC converter can reduce the number of passive components and die areas by using only one flying capacitor and by sharing active devices. The proposed converter has three outputs for individual brightness control of red–green–blue (RGB) LEDs. Each output directly regulates the current due to the V–I characteristics of LEDs, which are sensitive to PVT variations. In the proposed converter, the current-sensing technique is used to control the output current, instead of current-regulation elements (resistors or linear regulators). Additionally, in order to reduce the active area, three outputs share one current-sensing circuit. In order to improve the sensing accuracy, bias current compensation is applied to a current-sensing circuit. The proposed converter has been fabricated with a CMOS 0.13-μm 1P6M CMOS process. The input voltage range of the converter is 2.5–3.3 V, and the switching frequency is 200 kHz. The peak power efficiency reaches 71.8 % at V _IN =2.5 V, I _LED1 = 10 mA, I _LED2 = 18 mA, and I _LED3 = 20 mA. The current variations of individual outputs at different supply voltages are less than 0.89, 0.72, and 0.63 %, respectively.