A high performance super self-aligned 3 V/5 V BiCMOS technologywith extremely low parasitics for low-power mixed-signal applications

A high performance BiCMOS technology, BEST2 (Bipolar Enhanced super Self-aligned Technology) designed for supporting low-power multiGHz mixed-signal applications is presented. Process modules to produce low parasitic device structures are described. The developed BiCMOS process implemented with 1 μm design rules (0.5 μm as one nesting tolerance) has achieved f_l and f_max for npn bipolar (A_e=1×2 μm²) of 23 GHz and 24 GHz at V_ce=3 V, respectively, with BV_ceo⩾5.5 volts, and βV_A product of 2400. Typical measured ECL gate delay is 48 ps/37 ps per stage (A_e=1×2 μm² ; 500 mV swing) at 0.6 mA/2.1 mA switching currents, and CMOS gate delay (gate oxide=125 Å, L_eff=0.6 μm; V_th,nch =0.45 V; V_th,pch=-0.45 V) 70 ps/stage. A BiCMOS phase-locked-loop (emitter width=1 μm; gate L_eff=0.7 μm) has achieved 6 GHz operation at 2 V power supply with total power consumption of 60 mW     

RF power LDMOSFET on SOI

We have fabricated a SOI laterally diffused MOSFET that is designed for use in radio frequency power amplifiers for wireless system-on-a-chip applications. The device is fabricated on a thin-film SOI wafer using a process that is suitable for integration with SOI CMOS. An under-source body contact is implemented and both a high breakdown voltage and a high f_t are attained. The device performance compares favorably with bulk silicon rf power MOSFETs. For a gate length of 0.7 μm the device f_t is 14 GHz, f_max is 18 GHz, and the breakdown voltage approaches 25 V     

Simulation of SOI devices and circuits using BSIM3SOI

A versatile SOI model derived from the BSIM3v3 bulk MOSFET model is capable of simulating partially and fully depleted devices with options for self-heating and floating body effects. The model can automatically switch between fully and partially depleted regimes. After refining body current models we for the first time present successful dc and transient device and circuit simulation of an SOI MOSFET technology with L_eff below 0.2 μm     

On the SiO2-based gate-dielectric scaling limit forlow-standby power applications in the context of a 0.13 μm CMOS logictechnology

This paper describes a leading-edge 0.13 μm low-leakage CMOS logic technology. To achieve competitive off-state leakage current (I _off) and gate delay (T_d) performance at operating voltages (V_cc) of 1.5 V and 1.2 V, devices with 0.11 μm nominal gate length (L_g-nom) and various gate-oxide thicknesses (T_ox) were fabricated and studied. The results show that low power and memory applications are limited to oxides not thinner than 21.4 Å in order to keep acceptable off-state power consumption at V_cc=1.2 V. Specifically, two different device designs are introduced here. One design named LP (T_ox=26 Å) is targeted for V_cc=1.5 V with worst case I_off <10 pA/μm and nominal gate delay 24 ps/gate. Another design, named LP1 (T_ox=22 Å) is targeted for V_cc =1.2 V with worst case I_off<20 pA/μm and nominal gate delay 27 ps/gate. This work demonstrates n/pMOSFETs with excellent 520/210 and 390/160 μA/μm nominal drive currents at V_cc for LP and LP1, respectively. Process capability for low-power applications is demonstrated using a CMOS 6T-SRAM with 2.43 μm² cell size. In addition, intrinsic gate-oxide TDDB tests of LP1 (T _ox=22 Å) demonstrate that gate oxide reliability far exceeding 10 years is achieved for both n/pMOSFETs at T=125°C and V _cc=1.5 V     

SOI and bulk CMOS frequency dividers operating above 15 GHz

Dual-phase dynamic pseudo-NMOS ([DP]²) frequency dividers have been implemented in a partially scaled 0.1 μm CMOS technology. For 4:1 dividers on silicon-on-insulator (SOI) and bulk substrates, the maximum speed, power consumption, and extracted [DP]² latch delays are 18.75 and 15.4 GHz, 13.5 and 9.8 mW and 13.3 and 16.2 ps, respectively, at 1.5 V     

Experimental high performance sub-0.1 μm channel nMOSFET's

Very high performance sub-0.1 μm channel nMOSFET's are fabricated with 35 Å gate oxide and shallow source-drain extensions. An 8.8-ps/stage delay at V_dd=1.5 V is recorded from a 0.08 μm channel nMOS ring oscillator at 85 K. The room temperature delay is 11.3 ps/stage. These are the fastest switching speeds reported to date for any silicon devices at these temperatures. Cutoff frequencies (f_T) of a 0.08 μm channel device are 93 GHz at 300 K, and 119 GHz at 85 K, respectively. Record saturation transconductances, 740 mS/mm at 300 K and 1040 mS/mm at 85 K, are obtained from a 0.05 μm channel device. Good subthreshold characteristics are achieved for 0.09 μm channel devices with a source-drain halo process     

A room temperature 0.1 μm CMOS on SOI

An advanced 0.1 μm CMOS technology on SOI is presented. In order to minimize short channel effects, relatively thick nondepleted (0.15 μm) SOI film, highly nonuniform channel doping and source-drain extension-halo were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 μm were obtained. It is shown that undepleted SOI results in better short channel effect when compared to ultrathin depleted SOI. Devices with little short channel effect all the way to below 500 Å effective channel length were obtained. Furthermore, utilization of source-drain extension-halo minimizes the bipolar effect inherent in the floating body. These devices were applied to a variety of circuits: Very high speeds were obtained: Unloaded delay was 20 ps, unloaded NAND (FI=FO=3) was 64 ps, and loaded NAND (FI=FO=3, C_L=0.3 pF) delay was 130 ps at supply of 1.8 V. This technology was applied to a self-resetting 512 K SRAM. Access times of 2.5 ns at 1.5 V and 3.5 ns at 1.0 V were obtained     

Partially depleted SOI NMOSFET's with self-aligned polysilicon gateformed on the recessed channel region

A new SOI NMOSFET with a “LOCOS-like” shape self-aligned polysilicon gate formed on the recessed channel region has been fabricated by a mix-and-match technology. For the first time, we developed a new scheme for implementing self-alignment in both source/drain and gate structure in recessed channel device fabrication. Symmetric source/drain doping profile was obtained and highly symmetric electrical characteristics were observed. Drain current measured from 0.3 μm SOI devices with V_z of 0.773 V and T_ox=7.6 nm is 360 μA/μm at V_GS=3.5 V and V _DS=2.5 V. Improved breakdown characteristics were obtained and the BV_DSS (the drain voltage for 1 nA/μm of I_D at T_GS=0 V) of the device with L_eff=0.3 μm under the floating body condition was as high as 3.7 V     

An SOI LDMOS/CMOS/BJT technology for integrated power amplifiersused in wireless transceiver applications

This paper describes a SOI LDMOS/CMOS/BJT technology that can be used in portable wireless communication applications. This technology allows the complete integration of the front-end circuits with the baseband circuits for low-cost/low-power/high-volume single-chip transceiver implementation. The LDMOS transistors (0.35 μm channel length, 3.8 μm drift length, 4.5 GHz f_T and 21 V breakdown voltage), CMOS transistors (1.5 μm channel length, 0.8/-1.2 V threshold voltage), lateral NPN transistor (18 V BV_CBO and h _FE of 20), and high Q-factor (up to 6.1 at 900 MHz and 7.2 at 1.8 GHz) on-chip inductors are fabricated. A fully-functional high performance integrated power amplifier for 900 MHz wireless transceiver application is also demonstrated     

Fully depleted CMOS/SOI device design guidelines for low-powerapplications

We report the fully depleted (FD) CMOS/SOI device design guidelines for low-power applications. Optimal technology, device and circuit parameters are derived and compared with bulk CMOS based design. The differences and similarities are summarized. Device design guidelines using devices with L=0.1 μm for FDSOI low-power applications are presented using an empirical drain saturation current model fitted to experimental data. The model is verified in the deep-submicron regime by two-dimensional (2-D) simulation. For L=0.1 μm FDSOI low-power technology, optimum speed and lower-power occurs at V_dd=3V_th and V_dd=1.5 V_th, respectively. Optimum buried oxide thickness is found to be between 300 and 400 nm for low-power applications. Optimum transistor sizing is when the driver device capacitance is 0.3 times the total load capacitance. Similarly optimum gate oxide thickness is when the driver device gate capacitance is 0.2-0.6 times the total load capacitance for performance and 0.1-0.2 for low-power, respectively. Finally optimum stage ratio for driving large loads is around 2-4 for both high-performance and low-power     

0.25 μm gate length CMOS devices for cryogenic operation

Under cryogenic operation, a low V_th realizes a high speed performance at a greatly reduced power-supply voltage, which is the most attractive feature of Cryo-CMOS. It is very important in sub-0.25 μm Cryo-CMOS devices to reconcile the miniaturization and the low V_th. Double implanted MOSFET's technology was employed to achieve the low V_th while maintaining the short channel effects immunity. We have investigated both the DC characteristics and the speed performance of 0.25 μm gate length CMOS devices for cryogenic operation. The measured transconductances in the saturation region were 600 mS/mm for 0.2 μm gate length n-MOSFET's and 310 mS/mm for 0.25 μm gate length p-MOSFET's at 80 K. The propagation delay time in the fastest CMOS ring oscillator was 22.8 ps at V_dd=1 V at 80 K. The high speed performance at extremely low power-supply voltages has been experimentally demonstrated. The speed analysis suggests that the sub-l0 ps switching of Cryo-CMOS devices will be realized by reducing the parasitic capacitances and through further miniaturization down to 0.1 μm gate length or below     

Submicron super TFTs for 3-D VLSI applications

High performance submicron super TFTs are reported. A novel grain enhancement method is used to form large single grain silicon at the channel region of the TFT, making its structure comparable to SOI MOSFET. The process can be performed with high controllability, thus giving much smaller device-to-device variation compared to conventional TFT process. The reported n-channel super TFT displays a subthreshold swing of 72 mV/dec, g_max=198 mS/mm and an I_dast of 0.3 mA/μm at V_g-V_t=1.5 V, with L_G=0.4 μm and t_ox=110 Å. The super TFT technology will facilitate the formation of three-dimensional (3-D) VLSI circuits and double gate CMOS     

An 0.3-μm Si epitaxial base BiCMOS technology with 37-GHzfmax and 10-V BVceo for RF telecommunication

In this paper, a 0.3-μm BiCMOS technology for mixed analog/digital application is presented. A typical emitter area of this technology is 0.3 μm×1.0 μm. This technology includes high f _max of 37 GHz at the low collector current of 300 μA and high BV_ceo of 10 V NPN transistor, CMOS with L_eff=0.3 μm, and passive elements. By using the shallow and deep trench isolation technology and nonselective epitaxial intrinsic base, the C_jc can be reduced to 1.6 fF, which is the lowest value reported so far. As a results, we have managed to obtain the high f_max at the low current region and high BV _ceo concurrently. These features will contribute to the development of high-performance BiCMOS LSI's for various mixed analog/digital applications     

A dynamic threshold voltage MOSFET (DTMOS) for very low voltageoperation

A new mode of operation for Silicon-On-Insulator (SOI) MOSFET is experimentally investigated. This mode gives rise to a Dynamic Threshold voltage MOSFET (DTMOS). DTMOS threshold voltage drops as gate voltage is raised, resulting in a much higher current drive than regular MOSFET at low V_dd. On the other hand, V_t is high at V_gs =0, thus the leakage current is low. Suitability of this device for ultra low voltage operation is demonstrated by ring oscillator performance down to V_dd=0.5 V     

体硅衬底上的CMOS Fin FET

介绍了一种制作在普通体硅上的 CMOS Fin FET.除了拥有和原来 SOI上 Fin FET类似的 Fin FET结构 ,器件本身在硅衬底中还存在一个凹槽平面 MOSFET,同时该器件结构与传统的 CMOS工艺完全相容 ,并应用了自对准硅化物工艺 .实验中制作了多种应用该结构的 CMOS单管以及 CMOS反相器、环振电路 ,并包括常规的多晶硅和 W/Ti N金属两种栅电极 .分析了实际栅长为 110 nm的硅基 CMOS Fin FET的驱动电流和亚阈值特性 .反相器能正常工作并且在 Vd=3V下 2 0 1级 CMOS环振的最小延迟为 14 6 ps/门 .研究结果表明在未来 VL SI制作中应用该结构的可行性     

A LDMOS technology compatible with CMOS and passive components forintegrated RF power amplifiers

The authors describe a bulk silicon LDMOS technology, which is compatible with CMOS and passive components, for the implementation of RF integrated power amplifiers (IPA's) used in portable wireless communication applications. This technology allows complete integration of the low cost and low power front-end circuits with the baseband circuits for single-chip wireless communication systems. The LDMOS transistor (0.35 μm channel length, 3.85 μm drift length, 3 GHz f _T and 20 V breakdown voltage), CMOS transistors (1.5 μm channel length), and high Q-factor (up to 6.10 at 900 MHz and 7.14 at 1.8 GHz) on-chip inductor are designed and fabricated to show the feasibility of the IPA implementation     

Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

In this paper, we propose a novel operation of a MOSFET that is suitable for ultra-low voltage (0.6 V and below) VLSI circuits. Experimental demonstration was carried out in a Silicon-On-Insulator (SOI) technology. In this device, the threshold voltage of the device is a function of its gate voltage, i.e., as the gate voltage increases the threshold voltage (V_t) drops resulting in a much higher current drive than standard MOSFET for low-power supply voltages. On the other hand, V_t is high at V_gs=0, therefore the leakage current is low. We provide extensive experimental results and two-dimensional (2-D) device and mixed-mode simulations to analyze this device and compare its performance with a standard MOSFET. These results verify excellent inverter dc characteristics down to V_dd=0.2 V, and good ring oscillator performance down to 0.3 V for Dynamic Threshold-Voltage MOSFET (DTMOS)     

A comprehensive study of performance and reliability of P, As, andhybrid As/P nLDD junctions for deep-submicron CMOS logic technology

A comprehensive study of P, As, and hybrid As/P nLDD junctions is presented in terms of performance, reliability, and manufacturability for the first time. It is found that As junctions limit the performance of deep submicron devices due to unacceptable hot-carrier reliability, whereas a hybrid junction (light dose P added to medium dose As) dramatically improves hot-carrier reliability while maintaining high performance and manufacturability. For L_eff of 0.19 μm, using this hybrid junction in a manufacturing process, an inverter gate delay of 32 ps, dc hot carrier life time exceeding ten years, and off-state leakage below 30 pA/μm at 2.9 V have been achieved     

体硅衬底上的CMOS FinFET

介绍了一种制作在普通体硅上的CMOS FinFET.除了拥有和原来SOI上FinFET类似的FinFET结构,器件本身在硅衬底中还存在一个凹槽平面MOSFET,同时该器件结构与传统的CMOS工艺完全相容,并应用了自对准硅化物工艺.实验中制作了多种应用该结构的CMOS单管以及CMOS反相器、环振电路,并包括常规的多晶硅和W/TiN金属两种栅电极.分析了实际栅长为110nm的硅基CMOS FinFET的驱动电流和亚阈值特性.反相器能正常工作并且在Vd=3V下201级CMOS环振的最小延迟为146ps/门.研究结果表明在未来VLSI制作中应用该结构的可行性.     

TFSOI complementary BiCMOS technology for low power applications

A Thin-Film-Silicon-On-Insulator Complementary BiCMOS (TFSOI CBiCMOS) technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 μm CMOS process with the lateral bipolar devices integrated as drop-in modules for CBiCMOS circuits. The near-fully-depleted CMOS device design minimizes sensitivity to silicon thickness variation while maintaining the benefits of SOI devices. The bipolar device structure emphasizes use of a silicided polysilicon base contact to reduce base resistance and minimize current crowding effects. A split-oxide spacer integration allows independent control of the bipolar base width and emitter contact spacing. Excellent low power performance is demonstrated through low current ECL and low voltage, low power CMOS circuits. A 70 ps ECL gate delay at a gate current of 20 μA is achieved. This represents a factor of 3 improvement over bulk trench-isolated double-polysilicon self-aligned bipolar circuits. Similarly, CMOS gate delay shows a factor of 2 improvement over bulk silicon at a power supply voltage of 3.3 V. Finally, a 460 μW 1 GHz prescaler circuit is demonstrated using this technology