An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application

This paper proposes a novel method to reduce the peak power of multiple scan chain based circuits during testing. The peak periodicity and the peak width of the power waveforms for scan-based circuits are analyzed. An interleaving scan architecture based on adding delay buffers among the scan chains is developed which can significantly reduce the peak power. This method can be efficiently integrated with a recently proposed broadcast multiple scan architecture due to the sharing of scan patterns. The effects of the interleaving scan technique applied to the conventional multiple scan and the broadcast multiple scan with 10 scan chains are investigated. Up to 51% peak power reduction can be achieved when the data output of a scan cell is affected by the scan path during scan. When the data output is disabled during scan, up to 76% of peak-power reduction is observed.     

考虑测试功耗的扫描链划分新方法

提出考虑测试功耗的扫描链划分新方法.首先为基于扫描设计电路的峰值测试功耗和平均功耗建模,得出测试功耗主要由内部节点的翻转引起的结论,因此考虑多条扫描链情况,从输入测试集中寻找相容测试单元,利用扫描单元的兼容性,并考虑布局信息,将其分配到不同的扫描链中共享测试输入向量,多扫描链的划分应用图论方法.在ISCAS89平台上的实验结果表明,有效降低了峰值测试功耗和平均测试功耗.     

一种降低多载波信号峰均比的技术

多载波信号峰均比的降低在现代功率放大器研究和设计中具有重要意义。文章基于多载波信号的包络特征,提出了一种全新的峰均比降低技术。理论分析和计算机仿真结果表明:文章所提出的技术可以较大程度的改变信号的包络分布,进而大幅度降低多载波信号的峰均比。从实验结果也可以看出,采用了这种新型多载波信号峰均比降低技术的功率放大器,线性与现有功率放大器相比得到大幅度改善。     

Power-Driven Routing-Constrained Scan Chain Design

Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized scan chains under a given routing constraint. The proposed technique is a three-phase process based on clustering and reordering of scan cells in the design. It allows to reduce average power consumption during scan testing. Owing to this technique, short scan connections in scan chains are guaranteed and congestion problems in the design are avoided.     

JTAG测试中扫描链的配置问题研究

分析了常见扫描链路配置中面临的问题,提出了一种扫描链配置方案。结合工程测试中出现的实际问题,给出了有关扫描链路配置的一些建议和注意事项。     

OFDM系统峰值功率的降低和处理方法

从两个方面对OFDM系统中峰值功率的降低和处理方法进行了综述。一类是从OFDM信号着手,包括编码技术、相位旋转方法、剪截法或者限幅法;另一类方法是对高频功率放大器的实现方面着手,主要是放大器预失真方法。     

Multiple Scan Chain Design for Two-Pattern Testing

Non-standard fault models often require the application of two-pattern testing. A fully-automated approach for generating a multiple scan chain-based architecture is presented so that two-pattern test sets generated for the combinational core can be applied to the sequential circuit. Test time and area overhead constraints are considered.     

Efficient Test Data Compression and Low Power Scan Testing in SoCs

Testing time and power consumption during the testing of SoCs are becoming increasingly important with an increasing volume of test data in intellectual property cores in SoCs. This paper presents a new algorithm to reduce the scan‐in power and test data volume using a modified scan latch reordering algorithm. We apply a scan latch reordering technique to minimize the column hamming distance in scan vectors. During scan latch reordering, the don't‐care inputs in the scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.     

扫描测试和扫描链的构造

本文首先论述了扫描设计与测试向量自动生成（ATPG）这种测试方法的关键技术，并由此为依据，提出部分扫描设计中，扫描链构造的分层次的三个选取原则。     

峰均功率比约束下扩展目标波形优化

针对包络约束条件下扩展目标最优检测波形设计,提出了峰均功率比约束条件下最优检测波形优化方法。首先,建立了扩展目标信号模型;然后,通过将恒定包括约束转换成峰均功率比约束,推导出该约束下扩展目标最优检测波形优化模型;并将该非凸模型转换成易于求解的凸优化模型,由此获得了恒定包络和低起伏包络条件下的最优检测波形;最后,以某典型扩展目标为例,仿真对比了不同约束参数下波形的检测性能,验证了优化所得恒定包络、低起伏包络波形相比于传统Barker 码波形具有更好的检测性能。     

Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing

At-speed scan testing, based on ATPG and ATE, is indispensable to guarantee timing-related test quality in the DSM era. However, at-speed scan testing may incur yield loss due to excessive IR-drop caused by high test (shift & capture) switching activity. This paper discusses the mechanism of circuit malfunction due to IR-drop, and summarizes general approaches to reducing switching activity, by which highlights the problem of current solutions, i.e. only reducing switching activity for one capture while the widely used at-speed scan testing based on the launch-off-capture scheme uses two captures. This paper then proposes a novel X-filling method, called double-capture (DC) X-filling, for generating test vectors with low and balanced capture switching activity for two captures. Applicable to dynamic & static compaction in any ATPG system, DC X-filling can reduce IR-drop, and thus yield loss, without any circuit/clock modification, timing/circuit overhead, fault coverage loss, and additional design effort.

一种可应用于并发在线测试的扫描单元设计

航天等领域对集成电路可靠性要求较高,要求其具有在线测试功能,以便及时发现故障,减少损失。结合现有扫描设计方法,设计了一种改进的扫描单元结构。将该扫描单元应用于时序电路后,能够在电路工作的同时进行测试;通过灵活的时钟选择机制,方便地控制电路进行非并发和并发测试。仿真实验表明,应用本文提出的扫描单元,时序电路能够在增加一定硬件冗余的条件下实现在线测试,时间开销较小,有较高的可靠性和一定的容错能力,实用性强。     

Combining Scan Test and Built-in Self Test

For digital chips containing functional logic and embedded memories, these are usually tested separately: Scan test is used for testing functional logic; Memory Built-in Self Test (MBIST) is run for embedded memories. A new approach is proposed to exercise scan test and MBIST in parallel in order to reduce production test time and improve stress tests. It requires only small additional logic and allows to simultaneously run both test modes. In general, the approach can be used to control simultaneously scan test and any Built-in Self Test (BIST) providing a simple pass/fail result.     

基于物理版图信息的低功耗扫描测试方法

芯片测试模式下功耗过高的情形会极大地降低芯片良率,已经成为越来越严重的问题。针对此问题,本文提出了一种降低测试功耗的设计方法。该方法采用贪婪算法来改变扫描链顺序,同时考虑芯片物理版图中寄存器单元的具体位置,能够实现在不影响测试覆盖率和绕线的前提下,快速有效地降低测试功耗。与已有的多种方法相比,该方法更快速更合理,可以应用于多种芯片的扫描链设计。该方法通过一款实际的电力线载波通信芯片验证,分别将平均功耗和瞬态功耗降至77%和83%。     

A New Scan Partition Scheme for Low‐Power Embedded Systems

A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low‐power embedded systems. In scan‐based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph‐based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively.     

Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees

In this paper, a new method for reducing scan shifts is presented. Scan design is one of the most popular designs for test method for sequential circuits. However, for circuits with many flip-flops, it requires a long test application time and high test-data volume. Our new scan method utilizes two configurations of scan chains, a folding scan tree and a fully compatible scan tree to alleviate these problems. It is observed that uncompacted test patterns typically contain a large fraction of don't care values. This property is exploited in the fully compatible scan tree to reduce scan shifts without degrading fault coverage. Then, a folding scan tree is configured to further reduce the length of scan chain and scan shifts. Experimental results on benchmark circuits show that this scan method can significantly reduce scan shifts. Hiroyuki Yotsuyanagi received his B.E., M.E. and Ph.D degrees from Osaka University, in 1993, 1995 and 1998, respectively. In 1998 he joined the Department of Electrical and Electronic Engineering, the University of Tokushima, where he is currently an Associate Professor. His research interest includes test synthesis for sequential circuits and current testing for CMOS ICs. He is a member of the IEICE and the IEEE. Toshimasa Kuchii received B.E., M.E., and Ph.D. degrees in Electrical and Electronic Engineering from the University of Tokushima in 1994, 1996, and 1999, respectively. He is currently a DFT engineer at Sharp Corporation. His research interests are DFT methodologies for SoC devices, PLL jitter testing, and DFT for image sensor devices. Shigeki Nishikawa received B.E. in the Department of Information and Behavioral Sciences from Hiroshima University in 1980. He is currently a manager of LSI test engineering department at Sharp Corporation. His research interests are DFT, DFM and the total solution of testing technologies in the CAE tools. Masaki Hashizume received his B.E. and M.E. degrees in electrical engineering from the Univ. of Tokushima and Dr.E. degree from Kyoto Univ., in 1978, 1980 and 1993, respectively. He is currently a Professor of the Department of Electrical and Electronic Engineering, Faculty of Engineering, the Univ. of Tokushima. His research interests are logic synthesis and supply current testing of logic circuits. Kozo Kinoshita received B.E., M.E., and Ph.D. in Communication Engineering from Osaka University in 1959, 1961, and 1964, respectively. From 1964 to 1966 he was an Assistant Professor and from 1967 to 1977, an Associate Professor of Electronic Engineering at Osaka University, Osaka, Japan. From 1978 to 1989, he was a Professor in the Department of Information and Behavioral Sciences, Hiroshima University, Hiroshima, Japan. From 1989 to 2000, he again joined Osaka University as a Professor in the Department of Applied Physics, and is enumerates professor of Osaka University. Since April 2000, he has been a professor at Faculty of Informatics, Osaka Gakuin University, and is the Dean of Informatics. His fields of interest are test generation, fault diagnosis, memory testing, current testing, crosstalk testing, compact testing and testable design for logic circuits. He organized a series of Asian Test Symposium and was the Group Chair of Asian and Pacific Activities in Test Technology Technical Council of IEEE Computer Society until 2002. Prof. Kinoshita is IEEE Life Fellow, IEICE Fellow and a member of the Institute of Information Processing of Japan. He was a member of the editorial board of JETTA until 2000.     

基于门控结构的低功耗扫描测试方案

针对芯片测试功耗过高,严重影响芯片的良率的问题,提出了门控扫描时钟方法和门控组合逻辑方法相结合的测试方案来降低芯片测试功耗。采用该测试方案,使用Synopsys公司的DFT Compiler软件,完成了一款电力网载波通信芯片的可测性设计。结果表明,该测试方案在不降低响测试覆盖率和不增加测试时间的前提下,最终将测试功耗降低了37.3%。该测试方案能够快速有效地降低芯片测试功耗,具有广泛的应用价值。     

Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing

In this paper we propose a new approach to generate a primary input blocking pattern for applying to the primary inputs during shift cycle such that the switching activity occurred in the combinational part of the circuit under test can be suppressed as much as possible. The primary input blocking technique suppresses transitions of gates in the combinational part during scan by assigning controlling values to one of the gates' inputs. However, simultaneously assigning controlling values to the gates may result in conflicts in the setting of binary values on the primary inputs. Instead of the heuristics based on fanout in other approaches, we use the impact function which is based on transition density to determine the priorities of the gates to be blocked. Experiments performed on the ISCAS 89 benchmark circuits show that the proposed approach can always produce better results than the existing approaches.

Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations

Scan-based cores impose considerable test power challenges due to excessive switching activity during shift cycles. The consequent test power constraints force system-on-chip (SOC) designers to sacrifice parallelism among core tests, as exceeding power thresholds may damage the chip being tested. Reduction of test power for SOC cores can thus increase the number of cores that can be tested in parallel, improving significantly SOC test application time. In this paper, we propose a scan chain modification technique that inserts logic gates on the scan path. The consequent beneficial test data transformations are utilized to reduce the scan chain transitions during shift cycles and hence test power. We introduce a matrix band algebra that models the impact of logic gate insertion between scan cells on the test stimulus and response transformations realized. As we have successfully modeled the response transformations as well, the methodology we propose is capable of truly minimizing the overall test power. The test vectors and responses are analyzed in an intertwined manner, identifying the best possible scan chain modification, which is realized at minimal area cost. Experimental results justify the efficacy of the proposed methodology as well.

基于镜像对称参考切片的多扫描链测试数据压缩方法

为了减少测试数据和测试时间,该文提出一种基于镜像对称参考切片的多扫描链测试数据压缩方法。采用两个相互镜像对称的参考切片与扫描切片做相容性比较,提高了相容概率。若扫描切片与参考切片相容,只需要很少的几位编码就可以表示这个扫描切片,并且可以并行载入多扫描链;若不相容,参考切片被该扫描切片替换。提出一种最长相容策略,用来处理扫描切片与参考切片同时满足多种相容关系时的选取问题。根据Huffman编码原理确定不同相容情况的编码码字,可以进一步提高测试数据的压缩率。实验结果表明所提方法的平均测试数据压缩率达到了69.13%。