A new method to electrically determine effective MOSFET channel width

A new, easy, and accurate electrical measurement method for determining process bias of MOSFET channel width is proposed. This method is based on the linear relationship between the effective width and the channel conductance (or drain current) of a MOSFET operating in the linear region. Constant and sufficiently high gate voltages compared with the threshold voltage of the device are used in the measurement to minimize the error due to the threshold-voltage variation with W in narrow-width devices. The validity of the method is supported by identical results obtained using different gate voltages.     

A new approach to determine the effective channel length and thedrain-and-source series resistance of miniaturized MOSFET's

A new decoupled C-V method is proposed to determine the intrinsic (effective) channel region and extrinsic overlap region for miniaturized MOSFET's. In this approach, a unique channel-length-independent extrinsic overlap region is extracted at a critical gate bias, so bias-independent effective channel lengths (L_eff) are achieved. Furthermore, the two-dimensional (2D) charge sharing effect is separated from the effective channel region. Based on this L_eff and the associated bias-dependent channel mobility, μ_eff , the drain-and-source series resistance (R_DS) can be derived from the I-V characteristics for each device individually. For the first time, the assumption or approximation for R_DS and μ_eff can be avoided, thus the difficulties and controversy encountered in the conventional I-V method can be solved. The 2D charge sharing effect is incorporated into the bias-dependent R_DS. This bias dependence is closely related to the drain/source doping profile and the channel dopant concentration. The proposed L_eff and R_DS extraction method has been verified by an analytical I-V model which shows excellent agreements with the measured I-V characteristics     

A capacitance method to determine channel lengths for conventional and LDD MOSFET's

A simple method for determining the channel length and in situ gate-oxide thickness of MOSFETs is described. The method is based on the linear relationship between the intrinsic gate capacitance and effective channel length. Measurements from two gate biases on devices of different channel lengths are sufficient to obtain a full characterization. In contrast to the channel-resistance method, the accuracy of the capacitance method is independent of the source-drain and contact series resistance. It can, therefore, be used for conventional as well as lightly-doped drain (LDD) devices. Channel length and gate-oxide thickness determined by this method are given for conventional and LDD MOSFET's. For conventional MOSFET's, the new method agrees with the traditional effective length measurements to better than 0.1 µm.     

A simple method to determine channel widths for conventional and LDD MOSFET's

A new method to determine the channel widths and in situ gate-oxide thicknesses of conventional and LDD MOSFET's is described. The method is based on the linear relationship between the intrinsic gate capacitance and effective channel width. Measurements from two gate biases on devices of different channel widths are sufficient to obtain a full characterization. Channel widths and gate-oxide thicknesses determined by this method are given for both types of devices. This method applies to large-size as well as small-size, test devices.     

A new method to determine MOSFET channel length

A new method is proposed to electrically determine MOS transistor channel length with both accuracy and convenience. Based on the linear region relationship between effective channel length Leffand channel resistance Rchanof an MOS transistor, this method determines Leffby applying relatively large but constant gate voltage to eliminate threshold voltage determination and takes into account external resistance. Comparison of this method with SEM measurement shows very good agreement (within ±0.1 µm resolution limit of our SEM technique).     

A study of the validity of capacitance-based method for extractingthe effective channel length of MOSFET's

The capacitance-based method (C-V method) is a straightforward method for extracting the effective channel length of MOSFETs. This paper investigates the validity of such a method based on results simulated from a two-dimensional (2-D) device simulator. The effective channel length extracted from the C-V method is also compared with those obtained from other methods reported in the literature     

Extraction of metallurgical effective channel length in LDD MOSFET's

A new extraction method of metallurgical effective channel length (L/sub met/) in LDD MOSFET's is proposed. This method is based on the clear device physics. First, the carrier density modulation effect is overcome by "paired V/sub TH/" method. Second, the effect of charge sharing is eliminated by extrapolating L/sub eff/ found by "paired V/sub TH/" method to that at zero depletion width between the lightly doped region and the substrate. Both simulation and experimental results demonstrate the accuracy and usefulness of our approach. For example, the device simulation result shows that the extracted L/sub met/ has only 60 /spl Aring/ error compared with the physical dimension defined by the distance between the source and drain n/sup -/ metallurgical junctions. Proposed method is accurate, reliable enough to be used for the routine monitoring in manufacturing environment.<>     

Gate-voltage-dependent effective channel length and series resistance of LDD MOSFET's

A measurement algorithm to extract the effective channel length and source-drain series resistance of MOSFET's is presented. This extraction algorithm is applicable to both conventional and LDD MOSFET's. It is shown that the effective channel length and the source-drain series resistance of an LDD device are gate-voltage dependent. The effective channel length of an LDD device is not necessarily the metallurgical junction separation between the source and drain as it is commonly seen in a conventional device. A more generalized interpretation of effective channel length is introduced to understand the physical meaning of this gate-voltage dependence. The result also indicates that the effective channel length and source-drain resistance are two inseparable device parameters regardless of LDD or conventional FET's.     

A capacitance method to determine the gate-to-drain/Source overlap length of MOSFET's

A method is described which uses accurate measurement of gate-to-drain/source overlap capacitances to determine the gate-to-drain/ source overlap length for process control as well as device characterization. The method might also be a useful analytical tool in studying lateral dopant diffusion. Using this technique, the variation in overlap length of MOSFET's in a 4-in wafer is mapped. It is found that a significant spread of the overlap exits and is attributable to the implant shadowing by the polysilicon gate.     

An improved method to determine MOSFET channel length

An accurate and simple method to determine channel length and parasitic drain/source series resistance is presented. This method is based on measured data of two identical devices with different channel lengths. Because of its simplicity, the technique is suitable for use in automatic parameter testing systems.     

Accuracy of an effective channel length/External resistance extraction algorithm for MOSFET's

The accuracy of an effective channel length/external resistance extraction algorithm for MOSFET's is assessed. This is accomplished by exercising the algorithm with current-voltage data generated by two-dimensional numerical device simulation; the extracted quantities are directly compared to their known counterparts as they exist in the cross section of the simulated device. Extracted effective channel length is found to be within 0.07 µm of the metallurgical channel length in both the conventional and LDD MOSFET's studied here. Extracted external resistance is found to be a reasonable first-order estimate of actual device resistance external to the metallurgical channel but is unable to supply proper information regarding the gate bias dependence of this quantity.     

Channel potential and channel width in narrow buried-channel MOSFET's

A new method is described for determining the effective width over which incremental charge spreads in a narrow buried-channel transistor. The method is based on the transconductance in the buried-channel mode. Experimental results for effective widths and channel potential shifts are presented for MOSFET's with effective channel widths from 2 to 10 µm. Two-dimensional numerical calculations verify the experimental results.     

A channel resistance derivative method for effective channel lengthextraction in LDD MOSFETs

A channel resistance derivative method for extracting the electrical effective channel length and series resistance is proposed, and demonstrated on an advanced 0.35 μm LDD CMOS technology. A clear graphic image of the L_EFF and R_SD is obtained directly from the measured channel resistance and its derivative with respect to the gate bias. The method also provides guidelines for the proper gate bias range selection in traditional L_EFF extraction techniques     

A modification on "An improved method to determine MOSFET channel length"

A brief review of a recent paper [1] describing a method to electrically determine the effective channel length is presented. The method uses a simplifying approximation. By defining some new terms this application can be avoided leading to a new method. Finally, data is presented comparing the two methods for MOSFET's clearly violating the approximation and exemplifying the general applicability of the new method.     

Fast determination of the effective channel length and the gate Oxide thickness in polycrystalline Silicon MOSFET's

MOSFET's with variable channel lengths have been fabricated in both mono- and fine-grained polycrystalline silicon. We present a new method based upon a simple CV technique, to measure the effective channel length and gate oxide thickness. The channel-length reduction of the poly-Si MOSFET's was about 7.8 µm from which an effective lateral diffusion coefficient at 1000°C of phosphorus of 5 × 10^-13cm²/s was calculated. The electron mobility was in the range of 10-20 cm²/V.s and the threshold voltage was about 17 V. The MOSFET's in mono-Si have been used as a reference. The results of measurements on these devices are in agreement with literature.     

A new method for extracting the effective channel length of MOSFETs

A new and simple method to extract the effective channel length L_eff of metal-oxide superconductor field effect transistor (MOSFET)s is presented. The method, which is developed based on an auxiliary integral function, has the advantage of determining the value of L_eff not influenced by the series resistances of the MOSFET. The method is tested in the environments of device simulation and measurements. In addition, comparison is made between the results obtained from the present method and a widely used L_eff extraction method.     

An effective channel length determination method for LDD MOSFETs

We propose a definition of MOSFET effective channel length (L_EFF), that provides a method of determining L_EFF as a constant, and external resistance (R_EXT) virtually as a constant, even for lightly doped drain (LDD) transistors. A unified relationship between this L_EFF and MOSFET drive current (linear and saturation) that is common to a wide range of drain structures was confirmed. Therefore, the L_EFF is useful, not only for compact analytical models, but also as an index of MOSFET performance applicable to both single drain and LDD devices. The dependence of the channel length on the source/drain structure was clarified by introducing the concept of local contribution to channel length. The L_EFF varies, even if the metallurgical channel length is fixed, depending on the design of the source/drain     

On the accuracy of channel length characterization of LDD MOSFET's

A comprehensive investigation into the various mechanisms that limit the accuracy of channel length extraction techniques for lightly doped drain (LDD) MOSFET's is presented. Analytic equations are derived to quantify the sensitivity of the extraction techniques to the geometry effect, and bias dependence of the n^-source and drain resistance. The analytic approach is supplemented and verified by exercising channel length extraction algorithms on current-voltage characteristics obtained from rigorous numerical simulations of a variety of LDD MOSFET's. The analyses clearly show that low gate overdrives and consistent threshold voltage measurements are required to accurately extract the metallurgical channel length. The analytic equations can be used to project the limitations of channel length extraction methods for future submicrometer LDD MOSFET's.     

Reduction of channel hot-electron-generated substrate current insub-150-nm channel length Si MOSFET's

Channel hot-electron-generated substrate currents were measured in MOSFET devices with channel lengths down to 0.09 μm, and a family of characteristic plots of substrate current, normalized to drain current, I_SUB/I_D, rather than (V _DS-V_DSAT)^-1 was obtained. For channel lengths greater than 0.5 μm, the characteristics are independent of channel length. For channel lengths in the range of 0.15 μm, the characteristics are independent of channel length. For channel lengths in the range of 0.15 μm, the normalized substrate current at constant V_DS increases with decreasing channel length. However, as the channel length is decreased below 0.15 μm, a decrease of the normalized substrate current is observed. The decrease is larger at 77 K than at 300 K. This decrease accompanies the onset of electron velocity overshoot over a large portion of the channel. It is suggested that the decrease is due either to a decrease of carrier energy because energy relaxation and transit times become comparable, to a relative decrease of the carrier population in the channel, or to both     

Neural network based MOSFET channel length and width decision method for analogue integrated circuits

The channel length and width of a MOSFET are two important parameters selected by the experience of the integrated circuit designer. Since drain current of a transistor is directly adjusted by the aspect ratio, the wrong selection of these parameters changes the circuit characteristics. In this work neural networks are used to decide the most suitable selection of channel length and width of MOSFET. Both p-channel and n-channel transistors are modelled by multi layer perceptron (MLP) neural network and the channel length and width are predicted by MLP. MOSFET level 3 is modelled by MLP, training and test data are obtained from HSPICE design environment with YITAL 1.5μ parameters. Developed network is tested with the current mirror and the differential amplifier circuits. Estimated aspect ratios for each transistor are compared with the HSPICE simulation results.