New Ti-SALICIDE process using Sb and Ge preamorphization forsub-0.2 μm CMOS technology

A new process for thin titanium self-aligned silicide (Ti-SALICIDE) on narrow n⁺ poly-Si lines and n⁺ diffusion layers using preamorphization implantation (PAI) with heavy ions of antimony (Sb) and germanium (Ge) has been demonstrated for application to 0.2-μm CMOS devices and beyond. Preamorphization enhances the phase transformation from C₄₉Ti_xSi _x to C₅₄TiSi₂ and lowers the transformation temperature by 80°C so that it occurs before conglomeration in narrow lines. Preamorphization by Sb and Ge implantation yields better results than that by As. The sheet resistance of TiSi₂ on heavily As doped poly-Si lines are 3.7 Ω/□ and 3.8 Ω/□ for the samples preamorphized by Ge and Sb implantations even with line width down to 0.2 μm. There is less leakage in the Ti-SALICIDE diode with preamorphization than without it. The probable reasons and mechanisms are discussed     

Inductance measurements in YBa2Cu3O7 DC SQUID's with a submicrometer line width

We measured the inductances of submicrometerwide strip lines by using DC superconducting quantum interference devices (SQUID's) fabricated from a single layer of YBa₂Cu₃O₇ thin film, The measured inductances coincided well with some numerically calculated inductances consisting of a magnetic and kinetic component. The proportion of the magnetic component in the total inductance for the line width of 2 μm was estimated from calculation to be 56%, The kinetic component increased with the decrease of the line width and was dominant for line widths less than 1 μm. The inductance per square at 4.2 K was measured to be 1.3 pH/□ for line widths from 0.5 to 2 μm     

Monitoring of TiSi2 formation on narrow polycrystallinesilicon lines using Raman spectroscopy

Micro-Raman spectroscopy is used to monitor titanium silicide (TiSi₂) formation on narrow undoped polycrystalline silicon lines. Linewidths varying from 1.0 μm down to 0.35 μm, with silicidation by rapid thermal anneal (RTA) temperature ranging between 780°C and 1020°C were analyzed. Phase changes between C49 and C54-TiSi₂ phases were clearly observed. Results demonstrate that analysis of the C54-TiSi₂ Raman peak intensity allowed fast and nondestructive estimation of the process window for low resistivity C54-TiSi₂ formation. Comparison with sheet resistivity measurements showed that micro-Raman scattering provides a complimentary means to electrical analysis for the study of TiSi₂ formation     

Comparison of transformation to low-resistivity phase andagglomeration of TiSi2 and CoSi2

The phase transformation and stability of TiSi₂ on n ⁺ diffusions are investigated. Narrower n⁺ diffusions require higher anneal temperatures, or longer anneal times, than wider diffusions for complete transitions from the high-resistivity C49 phase to the low-resistivity C54 phase. A model is presented which explains this in terms of the probability of forming C54 nuclei on narrow diffusions and the influence of diffusion width on C54 grain size. The results are that more C49 and C54 nucleation events are required to completely transform narrow lines. For thin TiSi₂ (40 nm), there is a narrow process window for achieving complete transformation without causing agglomeration of the TiSi₂. The process window decreases with decreasing silicide thickness. A significantly larger process window is achieved with short-time rapid annealing. Similar studies are performed for CoSi₂ on n⁺ and p⁺ diffusions. No linewidth dependence is observed for the transformation from CoSi_x to CoSi₂. There is a broad process window from 575°C to 850°C using furnace annealing, for which the low-resistivity phase is obtained without causing agglomeration     

High-speed InGaP/GaAs heterojunction bipolar transistors withburied SiO2 using WSi as the base electrode

High-speed InGaP/GaAs heterojunction bipolar transistors (HBT's) with a small emitter area are described. WSi is used as the base electrode to fabricate HBT's with a narrow base contact width and a buried SiO₂ structure. An HBT with an emitter area of 0.8×5 μm exhibited an f_T of 105 GHz and an f_max of 120 GHz. These high values are obtained due to the reduction of C_BC by using buried SiO₂ with a narrow base contact width, indicating the great potential of GaAs HBT's for high-speed and low-power circuit applications     

Line impedance and propagation coefficient of narrowsuperconducting coplanar lines made of YBaCuO

The microwave properties of coplanar waveguides with line widths from 1 μm to 40 μm made of superconducting YBaCuO films with a thickness t=180 nm on LaAlO₃ are investigated. The line impedance Z_L and the normalized propagation coefficient β/β₀ of these waveguides are measured between 45 MHz and 26.5 GHz at temperatures between 77.4 K and 92 K. The ratio of the line width w to the distance of the ground layers d is constant with w/d=0.2. Therefore, Z_L and β/β₀ are independent of w for perfectly conducting waveguides. For superconducting waveguides it is found that Z_L and β/β₀ differ from the values of perfectly conducting waveguides. They increase for smaller line widths at a constant temperature. At w=1 μm and T=80 K, Z_L and β/β ₀ are nearly twice as high as calculated for perfect conductors. Furthermore, Z_L and β/β₀ increase with the temperature. It is shown that these effects are attributed to an increase of the inductance per unit length L' due to the superconducting material, whereas the capacitance per unit length C' behaves like C' of perfectly conducting waveguides. Using these results, the dimensions of the superconducting waveguides, which are necessary to obtain a desired Z_L at a given line width w, are calculated     

Analysis of resistance behavior in Ti- and Ni-salicided polysiliconfilms

The sheet resistance of TiSi₂-polycide (TiSi₂-polysilicon) lines increases as they are made narrower. This phenomenon has been investigated in detail. It is found that the relationship between sheet resistance and line width (W) is characterized by three distinct regions according to the value of W. The abrupt increase in sheet resistance observed in the region W⩽0.2 μm cannot be explained in terms of the phase transition from C54 to C49, which we show to be the cause of the rising resistance at larger W. By adopting a new test pattern for sheet resistance measurements and using it in combination with TEM and EDX analysis we conclude that the cause of this abrupt increase is the presence of large inter-grain layers where silicide is very sparse. On the contrary, NiSi films have no such inter-grain layers, and good resistance values can be obtained even with 0.1 μm lines. The NiSi process appears to be a suitable candidate to replace TiSi₂ in future deep-sub-micron high-speed CMOS devices     

CMOS shallow-trench-isolation to 50-nm channel widths

The applicability of shallow-trench-isolation (STI) for CMOS to 50-nm channel widths has been explored. Transistors with channel width to 50 nm and trench width to 200 nm have been fabricated. A comparison of several oxide-filled and polysilicon field-plate-filled STI structures is presented including processing, device performance, and isolation leakage. It is shown that V_th roll off as a function of channel width can be made as small as 65 mV and 145 mV at 100 nm channel width for polysilicon and oxide filled STI, respectively. Off-state currents less than 5×10^-12 A/μm and subthreshold slope around 80 mV/dec have been reached. Isolation breakdown voltages are about 8 V. Poly-filled STI effectively reduces channel edge effects, and provides excellent off-state, on-state, and turn-on characteristics all the way to 50-nm channel widths     

Post Si(C)N hillock nucleation and growth in IC copper lines controlled by diffusional creep

Post Si(C)N hillocks are characterized on Cu interconnects networks. Each network is compounded by standard damascene process electroplated Cu lines with given width and local line density. AFM results show that total volume per area of post Si(C)N hillocks both on narrow and large lines increases linearly with local Cu line density. Two trends of hillocks nucleation and growth are highlighted depending on line width. For line widths inferior to 4 μm, hillocks are located at the line edge. As line density increases, the number of hillocks remains constant but their mean volume proportionally increases. For wider lines, hillocks preferentially nucleate at the center of the line. The number of hillocks proportionally increases as line density increases, but hillock mean volume remains constant. Post Si(C)N hillocks density is found to be proportional to post CMP Cu grain surface boundary density before capping. It is proposed that hillocks growth could be controlled by Cu/Ta interface diffusion on narrowest lines and by grain boundary diffusion on wider ones.     

A low-impedance coplanar waveguide using an SrTiO3 thinfilm for GaAs power MMIC's

A novel structure for coplanar-waveguide transmission lines with low impedance and low loss is demonstrated in this paper. The new structure simply has a high dielectric SrTiO₃ thin film underneath the coplanar conductors. Due to the high dielectric constant of SrTiO₃, the coplanar line exhibited characteristic impedance as low as 18 Ω with a slot width of 5 μm and the center conductor width of 50 μm, while a conventional coplanar line on GaAs showed only 30 Ω with the same configuration. The newly developed coplanar structure is easily applicable for present GaAs monolithic-microwave integrated-circuit (MMIC) technology, especially for power MMIC's and low-impedance devices     

Composite metal etching for submicron integrated circuits

To define metal lines for composite metal structures for integrated circuits with small pitches (<2 μm), the etch selectivity and dimensional control must be improved from existing values of ~1.5:1 and >0.1 μm/line, respectively, without leaving metallic residue and without undercutting the masking layer. These goals have been achieved for a layered metal structure of Ti-W/Al-Cu(2%)/Ti-W with an Applied Materials AME 8330 batch system after examining process parameter spaces defined by the following: (i) reactor pressure, (ii) dc bias voltage, and (iii) gas composition for these two films. The selectivity between Al-Cu(2%) and photoresist increases with decreasing dc bias voltage and increasing Cl₂ content of Cl₂/BCl₃/CHF₃ gas mixtures. In comparison, the selectivity between Ti-W and photoresist increases only with increasing CF₄ content of CF₄/Cl₂ gas mixtures; changes in the other variables examined in this work with Ti-W have no significant effect on selectivity     

Memory array architecture and decoding scheme for 3 V only sectorerasable DINOR flash memory

A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low V_cc and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 μm, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8×1.6 μm² and the chip measures 5.8×5.0 mm ². The divided bit line structure realizes a small NOR type memory cell     

Influence of TiSi2 formation temperature on film thermal stability

This work is addressed to investigate thermal stability of a thin TiSi₂ film, that is its ability to resist degradation due to heat treatments at high temperatures. The study was carried out as a function of the formation RT treatment (675–750°C) at the end of a common process flow. Sheet resistance measurements were employed in order to evaluate this degradation. Electrical measures were performed on large and narrow poly-Si lines, on Van Der Pauw structures and on doped mono-Si substrates. An increase in sheet resistance value of an order of magnitude for silicide formed at temperatures below 700°C with respect to the one formed at temperatures above 700°C was found, particularly on poly-Si lines. The effect is detectable independently of the structure: it was observed also on 0.75-μm wide poly-Si lines, increasing when line width decreases. Different morphological analyses were carried out for investigating the influence of the formation temperature. We explain the increase of the final sheet resistance decreasing the formation temperature as a lower thermal stability of the TiSi₂ film, leading to a thermal grooving of the silicide grains.     

Determination of C54 nucleation site density in narrow stripes by sheet resistance measurements and μ-Raman spectroscopy

The kinetic of the C49–C54 phase transformation at 730°C in TiSi₂ narrow strips for width in the 0.5–1.3-μm range was investigated by resistance measurements and μ-Raman spectroscopy. With this last technique a growth rate of 0.15 μm/s and a nucleation density of about 0.035 sites/μm² were obtained. The fraction of the transformed material as measured by resistance follows the Johnson–Mehl–Avrami equation, with an exponent equal to 1 for all of the analysed linewidths. Nucleation site saturation occurs and the growth is one-dimensional along the length of the strip. The characteristic time increases as 1/W, W being the width of the strip, and, taking into account the growth rate obtained by μ-Raman spectroscopy, the nucleation density resulted 0.034 sites/μm² in excellent agreement with the μ-Raman results.     

Electroabsorption properties of InGaAs/InAlAs multiple quantum wellstructures at 1.5 μm

The electroabsorption properties of InGaAs/InAlAs MQW structures are characterised in terms of Δα, Δα/F and Δα/α₀, where Δα is the electroabsorption, α₀ is the residual absorption coefficient under zero bias, and F is the applied electric field. The limitations of these structures for 1.5 μm modulators are primarily due to the relatively small Δα/F values as a result of the small well width. The results are compared with the literature     

4H-SiC MESFET with 2.8 W/mm power density at 1.8 GHz

MESFET's were fabricated using 4H-SiC substrates and epitaxy. The D.C., S-parameter, and output power characteristics of the 0.7 μm gate length, 332 μm gate width MESFET's were measured. At ν_ds =25 V the current density was about 300 mA/mm and the maximum transconductance was in the range of 38-42 mS/mm. The device had 9.3 dB gain at 5 GHz and f_max=12.9 GHz. At V_ds=54 V the power density was 2.8 W/mm with a power added efficiency=12.7%     

Tunable laser pumped 3 μm Ho:YAlO3 laser

The tuning characteristics of the ⁵I₆ -⁵I₇ transition in a Ho:YAlO₃ laser, intracavity pumped by a 1.079 μm Nd:YalO₃ laser, were studied. Operation on seven distinct lines between 2.844 and 3.017 μm was found, and the threshold and relative slope efficiency of each line was measured. Several of these lines were previously unreported     

Crystallographic texture of C54 titanium disilicide as a function of deep submicron structure geometry

Detailed analysis of the crystallographic texture of C54 TiSi₂ was performed and showed a strong correlation between the geometry of the silicide structures and preferential crystallographic orientation. The study was undertaken on blanket and patterned TiSi₂ films formed in the reaction between 32 nm of Ti and undoped polycrystalline silicon using both in situ x-ray diffraction during heating and post-anneal four-circle pole figure reflection geometry measurements. Full pole figures were taken to determine the distribution of C54 TiSi₂ grain orientations in narrow (0.2 to 1.1 μm) lines which was compared with similar results obtained from unpatterned (blanket) films. While in blanket films we found the presence of weak <311> C54 TiSi₂ crystallographic orientation perpendicular to the sample surface, the <040> preferential orientation dominated in patterned submicron line structures and increased with decreasing linewidth. Using pole figure analysis, we observed strong <040> fiber texture in narrow lines with a slight variation in the tilt of the (040) planes normal in the direction perpendicular to the line (full width at half maximum [FWHM] ≈6°), but very little along the length of the line (FWHM ≈2°). In addition, a preferred in-plane (azimuthal) orientation of <040> crystals was found which showed that most of the <040> grains had their (004) plane normals oriented parallel with the line direction. These findings support a model of the C49 to C54 TiSi₂ transformation involving rapid growth of certain orientations favored by the one-dimensional geometry imposed by narrow lines.     

A very small bipolar transistor technology with sidewall polycidebase electrode for ECL-CMOS LSIs

Very small, high-performance, silicon bipolar transistors (SPOTEC) are developed for use in ECL-CMOS LSIs. The transistors are fabricated with a sidewall polycide base; chemical vapor deposition is used to selectively deposit tungsten on the sidewall surface of the polysilicon base. The tungsten is then silicided. This self-aligned polycide technology makes a narrow (0.4-μm wide), low-resistance (7 Ω/□) base electrode possible. Narrow U-groove isolation and narrow collector metallization techniques are used to reduce the transistor area to 10 μm². A shallow E-B junction and base layer have now been formed by using rapid-vapor-phase doping. The resulting transistors have good I-V characteristics without leakage current or high current gain. They have a high cut-off frequency of 37 GHz (53 GHz with pedestal collector ion implantation and thin epitaxial layer) and small junction capacitances. These transistors facilitate the development of very-high-speed, high-density ULSIs     

Crown-shaped stacked-capacitor cell for 1.5-V operation 64-Mb DRAMs

A self-aligned stacked-capacitor cell called the CROWN cell (a crown-shaped stacked-capacitor cell), used for experimental 64-Mb-DRAMs operated at 1.5 V, has been developed using 0.3-μm electron-beam lithography. This memory cell has an area of 1.28 μm². The word-line pitch and sense-amplifier pitch of this cell are 0.8 and 1.6 μm, respectively. In spite of this small cell area, the CROWN cell has a large capacitor surface area of 3.7 μm² because (1) it has a crown-shaped capacitor electrode, (2) its capacitor is on the data line, and (3) it has a self-aligned memory cell fabrication process and structure. The large capacitor area and a Ta₂O₅ film equivalent to a 2.8-nm SiO₂ film ensure a large storage charge of 33 fC (storage capacitance equals 44 fF) for 1.5-V operation. A small CROWN cell array and a memory test circuit were successfully used to achieve a basic DRAM cell operation