Pill-box capless thermal-heat-pulse annealing of ion-implanted GaAs

A capless annealing method for GaAs, employing short (1-10-s) thermal heat pulses from a graphite strip heater, is described. Results with²⁹Si+ implanted into semi-insulating chromium-doped HB and chromium-doped LEC GaAs are presented. The samples were annealed at temperatures as high as 1000°C in a stationary N2atmosphere with the implanted surface in close contact with a flat graphite strip heater surface. The wafers were covered with a graphite lid, effectively confining the volatile arsenic to a very small volume around the sample and providing a uniform temperature environment. Implantation efficiencies were high, and the quality of the implanted surface remained excellent after annealing.     

Ion implantation in gallium arsenide MESFET technology

The authors emphasize controlled shallow doping of GaAs by ion implantation and its limitations to state-of-the-art GaAs IC technology. The authors discuss the electrical activation behavior of implanted silicon in GaAs upon subsequent capless or silicon nitride capped rapid thermal annealing (RTA). It is demonstrated that atomic H diffuses into the implanted region of GaAs from a plasma-enhanced chemical vapor deposition Si₃N₄ cap during the deposition as well as during subsequent annealing, and the H retards the electrical activation kinetics of the implanted Si. Thru-Si cap dopant implants into GaAs have been studied to enhance dopant concentration in the surface region of the GaAs by recoil-implanted Si from the cap. Application of ion implantation to achieve buried-p layers in GaAs is also briefly discussed     

Halogen lamp annealing of GaAs for MESFET fabrication

Incoherent light from high-intensity halogen lamps was used for capless annealing of 2-inch GaAs wafers following silicon ion implantation. Fabrication of depletion mode MESFETs on the annealed wafers was used to study the DC characteristics and uniformity achieved with this annealing method. An average mutual transconductance of 110 mS/mm was obtained with MESFET fabricated wafers which were uniformly implanted at 5 × 1012 cm?2 with Si+ at 80 keV and subsequently annealed at 900°C for 2 s. The carrier concentration profiles obtained with this method are shown to be sharper than those obtained with furnace annealed wafers, which in turn results in a sharper device pinch-off voltage.     

Rapid thermal annealing of si implanted gaas

Rapid thermal annealing (RTA) technology offers potential advantages for GaAs MESFET device technology such as reducing dopant diffusion and minimizing the redistribution of background impurities. LEC semi-insulating GaAs substrates were implanted with Si at energies from 100 to 400 keV to doses from 1 × 10¹² to 1 × 10¹⁴/cm². The wafers were encapsulated with Si₃N₄ and then annealed at temperatures from 850-1000° C in a commercial RTA system. Wafers were also annealed using a conventional furnace cycle at 850° C to provide a comparison with the RTA wafers. These implanted layers were evaluated using capacitance-voltage and Hall effect measurements. In addition, FET’s were fabricated using selective implants that were annealed with either RTA or furnace cycles. The effects of anneal temperature and anneal time were determined. For a dose of 4 × 10¹²/cm² at 150 keV with anneal times of 5 seconds at 850, 900, 950 and 1000° C the activation steadily increased in the peak of the implant with overlapping profiles in the tail of the profiles, showing that no significant diffusion occurs. In addition, the same activation could be obtained by adjusting the anneal times. A plot of the equivalent anneal times versus 1/T gives an activation energy of 2.3 eV. At a higher dose of 3 × 10¹³ an activation energy of 1.7 eV was obtained. For a dose of 4 × 10¹² at 150 keV both the RTA and furnace annealing give similar activations with mobilities between 4700 and 5000 cm²/V-s. Mobilities decrease to 4000 at a dose of 1 × 10¹³ and to 2500 cm²/V-s at 1 × 10¹⁴/cm². At doses above 1 × 10¹³ the RTA cycles gave better activation than furnace annealed wafers. The MESFET parameters for both RTA and furnace annealed wafers were nearly identical. The average gain and noise figure at 8 GHz were 7.5 and 2.0, respectively, for packaged die from either RTA or furnace annealed materials.     

Capless annealing of silicon implanted gallium arsenide

Numerous commercially available semi-insulating GaAs substrates have been implanted with silicon ions and the post implantation annealing carried out using the technique of capless annealing in an arsine atmosphere. Results are presented on the implanted atomic silicon distribution along with carrier concentration and mobility profiles, Hall mobility and percentage activation figures for various implanted substrates. The phenomenon of thermally induced surface conduction layers in semi-insulating GaAs is discussed in the context of a capless annealing technique.     

Comparison of doping profiles in capless annealed and dielectrically capped — Annealed ion implanted GaAs

Recent results of a capless method of annealing ion implanted GaAs are reported. The physical mechanism and effectiveness of the process are described and comparison of doping profiles from wafers annealed with a reactively sputtered Si₃N₄ dielectric encapsulation and with the capless process is given. Capless annealing is shown to consistently result in narrower profiles for various dopants and implant energies. The observed differences are shown to be consistent with enhanced diffusion in the dielectric capped samples, and the effective diffusion coefficients, which are of the order of 10^?15 cm²/s for Se, differ by as much as a factor of two.     

PMOS integrated circuit fabrication using BF3 plasma immersion ion implantation

The feasibility of plasma immersion ion implantation (PHI) for multi-implant integrated circuit fabrication is demonstrated. Patterned Si wafers were immersed in a BF₃ plasma forp-type doping steps. Boron implants of up to 3 × 10¹⁵ atoms/cm² were achieved by applying microsecond negative voltage (-2 to -30 kV) pulses to the wafers at a frequency of 100 Hz to 1 kHz. After implantation the wafers were annealed using rapid thermal annealing (RTA) at 1060° C for 20 sec to activate the dopants and to recrystallize the implant damaged Si. For the PMOS process sequence both the Si source-drain and polycrystalline Si (poly-Si) gate doping steps were performed using PIII. The functionality of several types of devices, including diodes, capacitors, and transistors, were electrically measured to evaluate the compatibility of PIII with MOS process integration.     

Electrical characteristics of Be-implanted GaAs activated by rapid thermal annealing

Be-implanted GaAs are annealed by rapid thermal annealing (RTA) using halogen lamps. Electrical properties of the annealed GaAs are investigated, emphasizing those at 77K for application to the p+-layer of Be-implanted WSix-gate self-aligned two-dimensional hole gas (2- DHG) FET. An electrical activation of 90 percent (for 2.0 × 10¹³cm^-2) or 80 percent (for 2.2 × 10¹⁴cm^-2) is obtained. An annealing temperature dependence of carrier freezing at 77K is observed for higher dose samples. The phenomenon is attributed to the redistribution of impurity atoms near the high-concentration peak.     

Composite TaSi2/n+poly-Si formation by rapid thermal annealing

Composite TaSi2/n+ poly-Si structures have been formed by rapid thermal annealing (RTA). Polysilicon films 0.2 µm thick were deposited on oxidized Si wafers by LPCVD and heavily doped with phosphorus by diffusion. A layer of TaSix0.22 µm thick was then cosputtered on polysilicon from separate targets. The as-deposited samples were annealed by RTA using high-intensity tungsten lamps. Uniform stoichiometric low-resistivity tantalum disilicide was formed by RTA in 1 s at 1000°C. The sheet resistance and grain size of the silicide layers are comparable to those formed by conventional furnace anneals. The surface morphology of the RTA samples is superior to that obtained by furnace annealing. These results show that RTA technique has a great potential for low-resistivity tantalum silicide formation in VLSI circuits.     

退火对GaAs窗口晶体力学性能的影响

在L EC Ga As晶片中,存在相当大的弹性应变,在高温退火后,晶片的晶格参数的相对变化量不到原生晶片的70 % ,残余应力得以部分释放,从而减小残余应力诱生断裂的可能性,提高了Ga As晶体的断裂模数.原生Ga As晶体加工的样品的断裂模数平均值约为135 MPa,而退火Ga As晶体加工的样品的断裂模数平均值更高,约为15 0 MPa,断裂模数最高值达16 3MPa.     

半绝缘砷化镓中碳含量对热稳定性的影响

本文报导了LEC法半绝缘砷化镓单晶中含碳量对SI-GaAs热稳定性的影响。在800℃以上退火,发现当晶体中C含量大于1.5×10~(16)cm~(-3)时,SI-GaAs的热稳定性变差;而C含量小于5×10~(15)cm~(-3)时,通常表现出良好的热稳定性。     

Investigation of the 1.20-eV photoluminescence band in rapid thermal annealed InP

Deep level photoluminescence of rapid thermal annealed (RTA) undoped liquid-encapsulated Czochralski InP has been studied. Aband occurring at 1.20 eV, not observed in as-grown sample, became a dominant deep level peak after a 10-s rapid thermal annealing process. However, after high temperature or prolonged annealing, it disappeared again. Ion implantation by various species such as phosphorus, argon, and tin was carried out. The 1.20-eV band observed after RTA was found to be suppressed by the phosphorus-implantation but enhanced by tin implantation, suggesting that its origin may be due to the formation of phosphorus vacancy single point defect.     

Characterization of the Back Interface in Strained-Silicon-on-Insulator Channel and Enhancement of Electrical Properties by Heat Treatment

The electrical characteristics of thin strained-silicon-on-insulator (sSOI) wafers were evaluated, and the effects of annealing processes on the back interface states of sSOI wafers were analyzed by using the back-gated (BG) metal–oxide–semiconductor field-effect-transistor structure. The electrical characteristics of the BG MOSFET fabricated on sSOI wafers were superior to that of conventional SOI wafers. However, the rapid thermal annealing (RTA) process induced significant degradations by increasing the back interface states between the strained-Si thin channel and the buried oxide layer. On the other hand, the conventional furnace annealing process at 500 $^{circ}hbox{C}$ in a nitrogen $(hbox{N}_{2})$ ambient was effective for reducing the RTA-induced back interface states, and the performances of the BG sSOI MOSFET annealed in $hbox{N}_{2}$ ambient were significantly improved.      

SI GaAS中S~+注入的电学特性

本文研究了经常规热退火和快速热退火后SIGaAs中S~+注入的电学特性.热退火后,GaAs中注入S~+的快扩散和再分布不决定于S~+或砷空位V_(AS)的扩散而决定于离子注入增强扩散.使用快速热退火方法能抑制注入S~+在GaAs中的增强扩散,明显减小S~+的再分布,可以获得适合于制造GaAs MESFET器件的薄有源层.     

Ion-implantation and activation behavior of Si in MBE-Grown GaAs on Si substrates for GaAs MESFET's

The suitability of MBE-grown GaAs layers on Si substrates has been studied for ion-implanted GaAs MESFET technology. The undoped as-grown GaAs layers had a carrier concentration below 10¹⁴cm^-3. Uniform Si ion implants into 4-µm-thick GaAs layers on Si were annealed at 900°C for 10 s, using a rapid-thermal-annealing (RTA) system. Both the activation and the doping profile were similar to those obtained in bulk semi-insulating GaAs under similar conditions. The SIMS profiles of Si and As atoms near the GaAs/Si heterointerface were identical before and after the RTA process, indicating negigible interdiffusion during the implant activation. Dual implants of a shallow n+ layer and an n-channel layer were used to fabricate GaAs MESFET's with a recess-gate technology. Selective oxygen ion implantation was used for device isolation. The maximum transconductance obtained was 135 mS/ mm compared to typical values of 150-180 mS/mm obtained in our laboratory on GaAs substrates in similar device structures.     

热处理中As压对半绝缘GaAs缺陷的影响

在 95 0°C和 1 1 2 0°C温度下 ,对非掺杂半绝缘 LECGa As进行了不同 As气压条件下的热处理 ,热处理的时间为 2～ 1 4小时。发现不同 As压条件下的热处理可以改变 Ga As晶片的化学配比 ,并导致本征缺陷和电参数的相应变化。在 95 0°C和低 As气压条件下进行 1 4小时热处理 ,可在样品体内 (表面 1 5 0 μm以下 )引入一种本征受主缺陷 ,使电阻率较热处理前增加约 5 0 % ,霍尔迁移率下降 70 %。这种本征受主缺陷的产生是由于热处理过程中样品内发生了 As间隙原子的外扩散。提高热处理过程中的 As气压可以抑制这种本征受主缺陷的产生。真空条件下在 1 1 2 0°C热处理 2～ 8小时并快速冷却后 ,样品中的主要施主缺陷 EL2浓度约下降一个数量级 ,提高热处理过程中的 As气压可以抑制 EL2浓度下降。这种抑制作用是由于在高温、高 As气压条件下 ,发生了间隙原子向样品内部的扩散     

Formation and analysis of shallow arsenic profiles

Shallow arsenic implants were activated by furnace and rapid thermal annealing (RTA). Comparisons of junction depths measured by secondary ion mass spectrometry (SIMS) and spreading resistance (SR) showed SIMS values 50-90 nm deeper than SR values, due to ion knock-on during SIMS profiling     

Co-Implantation and autocompensation in close contact rapid thermal annealing of Si-implanted GaAs:Cr

Close contact rapid thermal annealing of semi-insulating GaAs:Cr implanted with Si, Si + Al, and Si + P has been studied using variable temperature Hall effect measurements and low temperature (4.2K) photoluminescence (PL) spectroscopy. Isochronal (10 sec) and isothermal (1000° C) anneals indicate that As is lost from the surface during close contact annealing at high anneal temperatures and long anneal times. Samples which were implanted with Si alone show maximum activation at an annealing temperature of 900° C, above which activation efficiency decreases. Low temperature Hall and PL measurements indicate that this reduced activation is due to increasing auto-compensation of Si donors by Si acceptors at higher anneal temperatures. However, co-implantation of column V elements can increase the activation of Si implants by reducing Si occupancy of As sites and increasing Si occupancy of Ga sites, and therebyoffset the effects of As loss from the surface. For samples implanted with Si + P, activation increases continuously up to a maximum at an anneal temperature of 1050° C, and both low temperature Hall and PL measurements indicate that autocompensation does not increase in this case as the anneal temperature increases. In contrast, samples implanted with Si + Al show very low activation and very high compensation at all anneal temperatures, as expected. The use of column V co-implants in conjunction with close contact RTA can produce excellent donor activation of Si implanted GaAs.     

Comparison of Poly-Si Thin Films Prepared by Conventional Furnace Annealing and Pulsed Rapid Thermal Annealing

Amorphous silicon films prepared by PECVD on glass substrate were crystallized by conventional furnace annealing (FA) and rapid thermal annealing ( RTA),respectively. From the Raman spectra and scanning electronic microscope(SEM),it found that the thin films made by RTA had smooth and perfect structure,while the thin films annealed by FA had a higher degree of structural disorder.     

Rapid thermal annealing of neutron transmutation doped silicon

Rapid thermal annealing (RTA) of neutron transmutation doped Si wafers is shown to be an alternative to conventional furnace annealing. Measurements of resistivity and deep level transient spectroscopy (DLTS), demonstrated annealing on wafers with diameters up to 75 mm. A 4.5 kW incoherent-light RTA furnace was used. Evidence for crystalline slip was found but this did not appear to affect the results. The slip was more severe for the larger diameter wafers. Some results from a DLTS examination of a partially rapid-thermal-annealed wafer are presented.