A 5-mW sigma-delta modulator with 84-dB dynamic range for GSM/EDGE

A sigma-delta modulator designed as part of a complete GSM/EDGE (enhanced data rate for GSM evolution) transceiver is described. High-resolution wide-band analog-to-digital converters enable the receiver to rely on digital processing, rather than analog filtering, to extract the desired signal from blocking channels. High linearity and low power consumption are the most stringent requirements for the converters in this wireless application. A single-bit 2-2-cascaded modulator operating at 13 MHz has been adopted for high linearity and stability. Low-power low-voltage techniques have been applied along with a top-down design approach in order to minimize the power dissipation. The ΣΔ modulator achieves 13.5 bits of resolution over a bandwidth of 180 kHz while dissipating 5 mW from 1.8-V and 2.4-V supplies. The circuit has been implemented in the CMOS portion of a 0.4-μm (drawn) BiCMOS technology and occupies an active area of 0.4 mm²     

A polar modulator transmitter for GSM/EDGE

This 0.5-/spl mu/m SiGe BiCMOS polar modulator IC adds EDGE transmit capability to a GSM transceiver IC without any RF filters. Envelope information is extracted from the transmit IF and applied to the phase-modulated carrier in an RF variable gain amplifier which follows the integrated transmit VCO. The dual-band IC supports all four GSM bands. In EDGE mode, the IC produces more than 1 dBm of output power with more than 6 dB of margin to the transmit spectrum mask and less than 3% rms phase error. In GSM mode, more than 7 dBm of output power is produced with noise in the receive band less than -164 dBc/Hz.     

A 13.5-mW 185-Msample/s ΔΣ modulator for UMTS/GSMdual-standard IF reception

A system-oriented approach for the design of a UMTS/GSM dual-standard ΔΣ modulator is presented to demonstrate the feasibility of achieving intermediate frequency (IF) around 100 MHz, high dynamic range, and low power consumption at the same time. The circuit prototype implements 78 MHz IF for GSM and 138.24 MHz for wideband code division multiple access (WCDMA), which are set to be 3/4 of the analog-to-digital converter sampling rate. A two-path IF sampling and mixing topology with a low-pass ΔΣ modulator, run at half the sampling rate, is used. Implemented in 0.25-μm CMOS, the circuit achieves dynamic range and peak signal-to-noise and distortion ratio for GSM of 86 and 72 dB, respectively. The corresponding values for WCDMA are 54 and 52 dB, respectively. Optimization is performed at all stages of design to minimize power consumption. The complete circuit consumes less than 11.5 mW for GSM and 13.5 mW for WCDMA at 2.5-V supply, of which 8 mW is due to the analog part     

40-Gb/s high-power modulator driver IC for lightwave communicationsystems

A monolithic integrated modulator driver with a data decision function for high-speed optical fiber links is presented. The integrated circuit (IC) was manufactured in a 0.2-μm gate length AlGaAs/InGaAs high electron mobility transistor technology with an f_T of 68 GHz. The modulator driver IC features differential configuration and operates up to 40 Gb/s with a clock phase margin of 210° and an output voltage swing of 2.9 V_p-p at each output. The maximum slew rate of the output signal is 200 mV/ps. The power dissipation of the circuit is 1.6 W using a single supply voltage of -5 V     

A 35-mW 3.6-mm/sup 2/ fully integrated 0.18-/spl mu/m CMOS GPS radio

A single-chip CMOS Global Positioning System (GPS) radio has been integrated using only a couple of external passive components for the input matching network and one external reference for the synthesizer. The receiver downconverts the GPS L1 signal at 1575.42 MHz to an IF of 9.45 MHz. The complete front-end and frequency synthesizer section have been integrated: low noise amplifier, image rejection mixer, IF active filter, and the full phase-locked loop synthesizer, including voltage-controlled oscillator and loop filter. The front-end measured performances are 81-dB maximum gain, 5.3-dB noise figure, and >30-dB image rejection. The synthesizer features a phase noise of -95 dBc/Hz at 1-MHz offset and a total integrated phase noise of less than 7/spl deg/ rms in the 500-Hz-1.5-MHz band. The front-end and the synthesizer draw, respectively, 11 and 9 mA from a 1.8-V supply. The architecture of the front-end and synthesizer has been geared to high level of integration and reduction of silicon area at the lowest possible power consumption. Consequently, the one reported here is the smallest and most integrated CMOS GPS receiver reported so far.     

A 0.5-mW passive telemetry IC for biomedical applications

A low-power, single-chip, one-channel, fully implantable microtransponder system for low-frequency biomedical sensor applications is described. The circuit is powered by an external RF source at 27/40 MHz. No battery is required. Wireless communication with external monitoring units is realized by absorption modulation. As the radiated power received by a small coil can be as low as a few milliwatts, the data acquisition/transmission system has been optimized for low power consumption. The system has been integrated in a 2-μm 40-V BiCMOS technology. It includes a low-offset amplifier, a low-pass notch filter, an A/D converter, a voltage doubler/rectifier, as well as a low-power voltage regulator. The implemented switched-capacitor amplifier features 45-μV offset and an integrated noise of 21 μV for a bandwidth of 30 Hz while consuming less than 30 μW power. The digitized sensor data are transmitted as low duty-cycle PPM-AM signals with a rate of 1 kBd. The entire system, including the 1.6-kΩ bridge sensor, consumes only 520 μW, which makes it well suited for long-term monitoring of biomedical signals     

A 1.48-mW low-phase-noise analog frequency modulator for wireless biotelemetry

This paper presents a low-phase-noise, hybrid LC-tank, analog frequency modulator for wireless biotelemetry employing on-chip NMOS varactors in the inversion region as the frequency tuning element. We demonstrate that a correct estimate for the destination signal-to-noise ratio, which quantifies the quality of the wirelessly received signal in a frequency-modulated biotelemetry system, is only achieved after taking into account the large-signal oscillation effect on the tank varactor. A prototype chip is fabricated using AMI 1.5-microm double-poly double-metal n-well CMOS process, and exhibits a measured gain factor of 1.21 MHz/V in the mid-range of the tuning voltage and a phase noise of -88.6 dBc/Hz at 10-kHz offset from the 95.1-MHz carrier while dissipating 1.48 mW from a 3 V power supply leading to a figure of merit (FOM) of -166.5 dBc/Hz. The VCO is successfully interfaced with a penetrating silicon microelectrode with 700 microm2 iridium recording sites for wireless in vitro recording of a 50 Hz simulated normal sinus rhythm signal from saline over a distance of approximately 0.25 m. Given a typical gain of approximately 40 dB for fully integrated front-end bioamplifiers, a wireless recording microsystem employing this VCO would be capable of detecting input biopotentials down to the submilivolt range.     

A 10-Gb/s laser/modulator driver IC with a dual-mode activelymatched output buffer

A laser/modulator driver IC for 10-Gb/s-SONET OC-192-fiber optic transmitters is described. Depending on the user application, the IC is capable of driving more than 100 mA of current into a laser diode or over 50 mA into an electro-absorption or Mach-Zehnder modulator. Rise and fall times below 20 pS are achieved. The driver employs a novel dual-mode actively matched output buffer that provides a dc-coupled back termination of either 25 or 50 Ω. Compared to an output buffer with a resistive termination, this buffer dissipates only half as much power. In addition, the buffer has the the ability to reject external bias and will therefore not load bias sources used to set laser threshold currents and modulator offset voltages. The low power consumption makes the IC most suitable for co-packaging with uncooled lasers and electro-absorption modulators. The driver is fabricated in a 0.25-μm gate length production GaAs PHEMT process with substrate thru vias, thin-film resistors, and MIM capacitors     

A 7-ns/850-mW GaAs 4-kb SRAM with little dependence on temperature

A GaAs 1 K×4-kb SRAM designed using a novel circuit technology is described. To reduce the temperature dependence and the scattering of the access time, it was necessary to increase the signal voltage swing and to reduce the leakage current in access transistors of unselected memory cells. In the 4-kb SRAM, source-follower circuits were adopted to increase the voltage swing, and the storage nodes of unselected memory cells were raised by about 0.6 V to reduce the subthreshold leakage current in the access transistors. The 4-kb SRAM was fabricated using 1.0-μm self-aligned MESFETs with buried p-layers beneath the FET regions. A maximum address access time of 7 ns and a power dissipation of 850 mW were obtained for the galloping test pattern at 75°C. Little change in the address access time was observed between 0 and 75°C     

A 27-mW 3.6-gb/s I/O transceiver

This paper describes a 3.6-Gb/s 27-mW transceiver for chip-to-chip applications. A voltage-mode transmitter is proposed that equalizes the channel while maintaining impedance matching. A comparator is proposed that achieves sampling bandwidth control and offset compensation. A novel timing recovery circuit controls the phase by mismatching the current in the charge pump. The architecture maintains high signal integrity while each port consumes only 7.5 mW/Gb/s. The entire design occupies 0.2 mm/sup 2/ in a 0.18-/spl mu/m 1.8-V CMOS technology.     

A 2.5-Gb/s 15-mW clock recovery circuit

This paper describes the design of a 2.5-Gb/s 15-mW clock recovery circuit based on the quadricorrelator architecture. Employing both phase and frequency detection, the circuit combines high-speed operations such as differentiation, full-wave rectification, and mixing in one stage to lower the power dissipation. In addition, a two-stage voltage-controlled oscillator is utilized that incorporates both phase shift elements to provide a wide tuning range and isolation techniques to suppress the feedthrough due to input data transitions. Fabricated in a 20-GHz 1-μm BiCMOS technology, the circuit exhibits an rms jitter of 9.5 ps and a capture range of 300 MHz     

A 1.8 V tri-mode ΣΔ modulator for GSM/WCDMA/WLAN wireless receiver

The next generation of cellular systems will be increasingly similar to a data communication system. Not only will it transfer voice and multimedia data, it will also be integrated with WLAN to access Internet whenever possible. Thus these cellular systems need highly integrated multi-standard receivers. The design of the A/D converter in such receivers is a big challenge. A GSM/WCDMA/WLAN tri-mode receiver is first designed on the system level. A reconfigurable ΣΔ modulator, which is suitable for GSM/WCDMA/WLAN receiver, is then proposed in this paper. According to the different signal bandwidth and Dynamic Range (DR) specifications, this ΣΔ modulator is reconfigured to achieve the required dynamic range with less power consumption. The prototype is implemented in TSMC 0.18-μm CMOS process with 1.8 V power supply. The circuit achieves signal-to-noise-and-distortion-ratio of 82 dB for GSM, 75 dB for WCDMA and 58 dB for WLAN. Ling Zhang obtained her B.S. and M.S. degrees in Automatic Control from Beijing University of Aeronautics and Astronautics, Beijing, China, in 1993 and 1996, respectively. She received the Ph.D. degree in Electrical Engineering from the Ohio State University, Columbus, OH, in 2005. She is currently with Nvidia Corporation, Santa Clara, CA. Her research interests lie in mixed-signal circuits, including multi-standard wireless receiver design, high speed sigma-delta ADC and frequency synthesizer/PLL/CDR. Hyung Joon Kim received the Master and Ph.D degree from Ohio State University, Columbus, Ohio in 1999 and 2005, respectively. Since 2004, he is with Intel Corporation, Chandler, AZ., where he is involved in various wireless receiver designs. Vinay Nadig was born in Bangalore, India in 1977. He received the M.S. degree in Electrical Engineering from The Ohio State University and is currently working towards his PhD degree there. His research interests include low power sigma delta ADCs for wireless receivers and design methodologies for complex mixed signal systems. Mohammed Ismail has over 20 years experience of R&D in the fields of analog, RF and mixed signal integrated circuits. He has held several positions in both industry and academia and has served as a corporate consultant to nearly 30 companies in the US, Europe and the far east. He is The Founding Director of the Analog VLSI Lab at Ohio State and has advised the thesis work of 39 PhD and over 75 MS students. His current interest lies in research involving digitally programmable/configurable fully integrated radios with focus on low voltage/low power first-pass solutions for 3G and 4G wireless handhelds. He publishes intensively in this area and has been awarded 11 patents. He has co-edited and co-authored several books including a text on Analog VLSI Signal and Information Processing, (McGraw Hill). His last book (2004) is entitled CMOS PLLs and VCOs for 4G Wireless, Springer. He co-founded ANACAD-Egypt (now part of Mentor Graphics, Inc.) and Spirea AB, Stockholm (now Firstpass Technologies Inc.), a developer of CMOS radio and mixed signal IPs for handheld wireless applications. Dr. Ismail has been the recipient of several awards including the US National Science Foundation Presidential Young Investigator Award, the US Semiconductor Research Corp Inventor Recognition Awards in 1992 and 1993, the Ohio State Lumley Research Award in 1992 1997 and 2002 and a Fulbright/Nokia fellowship Award in 1995. He is the founder of the International Journal of Analog Integrated Circuits and Signal Processing, Springer and serves as the Journal's Editor-In-Chief. He has served as Associate Editor for many IEEE Transactions, was on the Board of Governors of the IEEE Circuits and Systems Society and is the Founding Editor of “The Chip” a Column in The IEEE Circuits and Devices Magazine. He obtained his BS and MS degrees in Electronics and Communications from Cairo University, Egypt and the PhD degree in Electrical Engineering from the University of Manitoba, Canada. He is a Fellow of IEEE.     

A 56-mW 23-mm/sup 2/ single-chip 180-nm CMOS GPS receiver with 27.2-mW 4.1-mm/sup 2/ radio

A 56-mW 23-mm/sup 2/ GPS receiver with CPU-DSP-64 kRAM-256 kROM and a 27.2-mW 4.1-mm/sup 2/ radio has been integrated in a 180-nm CMOS process. The SoC GPS receiver, connected to an active antenna, provides latitude, longitude, height with 3-m rms precision with no need of external host processor in a [-40, 105]/spl deg/C temperature range. The radio draws 17 mA from a 1.6-1.8-V voltage supply, takes 11 pins of a VFQFPN68 package, and needs just a few passives for input match and a crystal for the reference oscillator. Measured radio performances are NF=4.8 dB, Gp=92 dB, image rejection > 30 dB, -112 dBc/Hz phase noise @ 1 MHz offset from carrier. Though GPS radio linearity and ruggedness have been made compatible with the co-existence of a microprocessor, radio silicon area and power consumption is comparable to state-of-the-art stand-alone GPS radio. The one reported here is the first ever single-chip GPS receiver requiring no external host to achieve satellite tracking and position fix with a total die area of 23 mm/sup 2/ and 56-mW power consumption.     

Cordless telephones and cellular radio: synergies of DECT and GSM

Cordless telephones have traditionally offered low-power, short-range domestic and office telecommunications, whereas cellular radio has offered longer-range, public-access capabilities at a premium price. Today's changing regulatory environment, accompanied by rapid technological developments, is beginning to offer network operators a range of new capabilities through the joint exploitation of these technologies. In this paper this changing environment is reviewed, some public-access cordless experiments are described and the future potential for dual-mode cordless-cellular integration is explored     

A 2.7-V GSM RF transceiver IC

A 2.7-V RF transceiver IC is intended for small, low-cost global system for mobile communications (GSM) handsets. This chip includes a quadrature modulator (QMOD) and an offset phase locked loop (OPLL) in the transmit path and a dual IF receiver that consists of a low noise amplifier (LNA) with an active-bias circuit, two Gilbert-cell mixers, a programmable gain linear amplifier (PGA), and a quadrature demodulator (QDEM). The IC also contains frequency dividers with a very high frequency voltage controlled oscillator (VHF-VCO) to simplify the receiver design. The system evaluation results are the phase error of 2.7° r.m.s. and the noise transmitted in the GSM receiving band of -163 dBc/Hz for transmitters and the reference sensitivity of -105 dBm for receivers. Power-control functions are provided for independent transmit and receive operation. The IC is implemented by using bipolar technology with f_T=15 GHz, r'_bb=150 Ω, and 0.6-μm features     

A 10-Bit 500-MS/s 55-mW CMOS ADC

A pipelined ADC incorporates a digital foreground calibration technique that corrects errors due to capacitor mismatch, gain error, and op amp nonlinearity. Employing a high-speed, low-power op amp topology and an accurate on-chip resistor ladder and designed in 90-nm CMOS technology, the ADC achieves a DNL of 0.4 LSB and an INL of 1 LSB. The prototype digitizes a 233-MHz input with 53-dB SNDR while consuming 55$~$mW from a 1.2-V supply.      

Baseband and audio mixed-signal front-end IC for GSM/EDGE applications

A complete mixed-signal front-end CMOS chip is presented, supporting GSM/EDGE as well as enhanced audio applications. The chosen solution for the transmit section is based on Laurent's approximation of the nonlinear GMSK modulator. This enables burst shaping in the I/Q domain thereby solving the problem of power ramping. Also, up to GPRS class 12 is supported. The receive section on the other hand consists of a low power dual mode continuous-time /spl Sigma//spl Delta/ ADC for I and Q, supporting ZIF and LIF modes of operation and achieving typically 12.5 bit of resolution under production conditions. An on-chip PLL, which supplies all blocks with various clock frequencies, additionally supports clock jitter suppression. The audio section comprises a codec supporting standard formats such as IIS and PCM. It features mono/stereo signaling from various sources in 16bit quality as well as high-drive buffers for 4 /spl Omega/ single-ended loads (capacitively coupled). The whole chip is powered from a 1.5/2.65 V supply voltage and consumes 22 mW in paging mode.     

A 123-mW W-CDMA uplink baseband receiver IC with beamforming capability

In this paper, architecture and circuit design of a beamforming baseband receiver IC for uplink W-CDMA communication systems is presented. In the proposed receiver, a four-antenna-element beamformer and a four-finger RAKE combiner are adopted to exploit both spatial diversity and path diversity receiving. To minimize the size and power consumption of the receiver, a latch-based 1024-tap complex delay line is custom designed for the matched filter in the channel estimation circuit. The receiver chip was fabricated in a 0.35-/spl mu/m n-well CMOS single-poly quadruple-metal technology. The minimum supply voltage with the chip running at the nominal 15.36-MHz clock rate is measured at 2.15 V. The chip has an area of 6 mm by 6.3 mm and a power consumption of about 123 mW.     

A 15-bit 30-MS/s 145-mW three-step ADC for imaging applications

This paper describes the design and realization of a 15-bit 30-MS/s three-step ADC for imaging applications with a peak-to-peak signal to rms noise ratio (DR/sub pp/) of 85 dB. The offsets of the residue amplifiers are independently background calibrated. The ADC is realized in single-poly, 0.18-/spl mu/m CMOS, measures 1.4 mm/sup 2/, and dissipates 145 mW from 1.8-V and 3.3-V supplies.     

一种13位400 kHz 11 mW Σ-Δ模拟/数字转换器

设计了应用于低中频GSM接收机的三阶单环单比特结构Σ-Δ A/D转换器。调制器采用全差分开关电容积分器实现。仿真结果显示,在工作电压为3 V、信号带宽200 kHz、0.35μm CMOS工艺的条件下,过采样率选择为64,信号/噪声失真比(SNDR)达到85 dB,功耗不超过11mW。