Single-electron logic device based on the binary decision diagram

The unit device consists of four tunnel junctions and operates as a two-way switch for single-electron transport. Any combinational logic can be implemented by connecting identical unit devices into a cascade to build the tree of a BDD graph. Several sample designs are presented for logic circuits of NAND, NOR, exclusive-OR, and AND-OR combinational logic. Computer simulation shows that the designed circuits perform the logic operations correctly     

Synthesis for logical initializability of synchronous finite-statemachines

Logical initializability is the property of a gate-level circuit whereby it can be driven to a unique start state when simulated by a three-valued (0, 1, X) simulator. In practice, commercial logic and fault simulators often require initialization under such a three-valued simulation model. In this paper, the first sound and systematic synthesis method is proposed to ensure the logical initializability of synchronous finite-state machines. The method includes both state assignment and combinational logic synthesis steps. It is shown that a previous approach to synthesis-for-initializability, which uses a constrained state assignment method, may produce uninitializable circuits. Here, a new state assignment method is proposed that is guaranteed correct. Furthermore, it is shown that combinational logic synthesis also has a direct impact on initializability; necessary and sufficient constraints on combinational logic synthesis are proposed to guarantee that the resulting gate-level circuits are logically initializable. The above two synthesis steps have been incorporated into a computer-aided design tool, SALSIFY, targeted to both two-level and multilevel implementations     

Design metal-dot based QCA circuits using SPICE model

This paper proposes a SPICE model development methodology for quantum-dot cellular automata (QCA) cells and presents a SPICE model for QCA cells. The model is validated by simulating the basic logic gates such as inverter and majority voter. The proposed model makes it possible to design and simulate QCA combinational circuits and hybrid circuits of QCA and other NANO devices using SPICE. In the second half part of the paper, SET and QCA co-design methodology is proposed and SET is used as a readout interface of the QCA cell array. The SET and QCA hybrid circuit is a promising nano-scale solution.     

判奇电路实现方法探讨

以三输入判奇电路设计为例,通过对其输出函数表达式的形式变换,分别采用多种门电路及译码器、数据选择器等74系列器件进行电路设计,给出了7种电路实现形式,并分析了各种电路实现的优缺点。此例说明了组合逻辑电路设计的灵活性及电路实现的多样性。所采用的设计方法对其他组合逻辑电路设计具有一定的启发与指导意义。     

Wave steering to integrate logic and physical syntheses

Wave steering is a unified logic and physical synthesis scheme that algorithmically generates high-throughput circuits with fast turn-around times. Binary decision diagram (BDD)-type structures are altered to satisfy certain electrical constraints, embedded in silicon with pass transistor logic (PTL), and pipelined to very fine granularity using a novel two-phase clocking scheme. This direct PTL mapping of a logic representation provides good electrical estimations to a front-end tool like the logic synthesizer at an early phase of the design cycle. We apply our wave steering technique to high throughput computation-intensive datapath combinational circuits. We achieve an average speedup of 4.2 times compared to standard cell (SC) implementations of high performance arithmetic circuits at the cost of only about 76% average increase in area. The results look extremely encouraging; all the more so, considering that we also achieve an average reduction of 27% in latency and 15% in power compared to SC circuits.     

A stuck fault model for dynamic CMOS combinational circuits

This paper utilizes the logic transistor function (LTF), that was devised to model the static CMOS combinational circuits at the transistor and logic level, to model the dynamic CMOS combinational circuits. The LTF is a Boolean representation of the circuit output in terms of its input variables and its transistor topology. The LTF is automatically generated using the path algebra technique. The faulty behavior of the circuit can be obtained from the fault-free LTF using a systematic procedure. The model assumes the following logic values (0, 1, I, M), where I, and M imply an indeterminate logical value, and a memory element, respectively. The model is found to be efficient in describing a cluster of dynamic CMOS circuits at both the fault-free and faulty modes of operation. Both single and multiple transistor stuck faults are precisely described using this model. The classical stuck-at and non classical stuck open and short faults are analyzed. A systematic procedure to produce the fault-free and faulty LTFs for different implementations of the dynamic CMOS combinational circuits is presented.     

Compaction-based concurrent error detection for digital circuits

We present a non-intrusive concurrent error detection (CED) method for combinational and sequential digital circuits. We analyze the optimal solution model and point out the limitations that prevent logic synthesis from yielding a minimal-cost monolithic CED implementation. We then propose a compaction-based alternative approach for restricted error models. The proposed method alleviates these limitations by decomposing the CED functionality into: compaction of the circuit outputs, prediction of the compacted responses, and comparison. We model the fault-free and erroneous responses as connected vertices in a graph and perform graph coloring in order to derive the compacted responses. The proposed method is first discussed within the context of combinational circuits, with zero detection latency, and subsequently extended to Finite State Machines (FSMs), with a constant detection latency of one clock cycle. Experimental results demonstrate that the proposed method achieves significant hardware reduction over duplication-based CED, while detecting all possible errors.     

一种新型二元判定图器件和电路

提出了一种基于二元判定图(BDD)原理的新型逻辑器件和电路．BDD器件以电流模式的开关电流存储器为基本单元，具有符合二元判定图的两向通路的特点．用这种器件按照BDD树形图可以构成任意形式的组合逻辑电路．给出了或门、异或门及四位加法器电路的例子，并使用HSPICE仿真器进行了仿真，验证了这种器件及其电路的正确性．     

Redundancies and don't cares in sequential logic synthesis

The relationships between redundant logic and don't care conditions in combinational circuits are well known. Redundancies in a combinational circuit can be explicitly identified using test generation algorithms or implicitly eliminated by specifying don't cares for each gate in the combinational network and minimizing the gates, subject to the don't care conditions.In this article, we explore the relationships between redundant logic and don't care conditions in sequential circuits. Stuck-at faults in a sequential circuit may be testable in the combinational sense, but may be redundant because they do not alter the terminal behavior of a nonscan sequential machine. These sequential redundancies result in a faulty State Transition Graph (STG) that is equivalent to the STG of the true machine.We present a classification of redundant faults in sequential circuits composed of single or interacting finite state machines. For each of the different classes of redundancies, we define don't care sets which if optimally exploited will result in the implicit elimination of any such redundancies in a given circuit. We present systematic methods for the exploitation of sequential don't cares that correspond to sequences of vectors that never appear in cascaded or interacting sequential circuits. Using these don't care sets in an optimal sequential synthesis procedure of state minimization, state assignment, and combinational logic optimization results in fully testable lumped or interacting finite state machines. We present experimental results which indicate that medium-sized irredundant sequential circuits can be synthesized with no area overhead and within reasonable CPU times by exploiting these don't cares.     

Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger

In VLSIs, soft errors resulting from radiation-induced transient pulses frequently occur. In recent high-density and low-power VLSIs, the operation of systems is seriously affected by not only soft errors occurring on memory systems and the latches of logic circuits but also those occurring on the combinational parts of logic circuits. The existing tolerant methods for soft errors on the combinational parts do not provide enough high tolerant capability with small performance penalty. This paper proposes a class of soft error masking circuits by using a Schmitt trigger circuit and a pass transistor. The paper also presents a construction of soft error masking latches (SEM-latches) capable of masking transient pulses occurring on combinational circuits. Moreover, simulation results show that the proposed method has higher soft error tolerant capability than the existing methods. For supply voltage V _DD ?=?3.3 V, the proposed method is capable of masking transient pulses of magnitude 4.0 V or less.     

Dynamic colour table: A novel S‐box for cryptographic applications

In cryptography, S‐boxes play an important role in symmetric ciphers. S‐boxes are used for substitution process to enable diffusion in encryption and decryption of the messages. In most of the conventional and modern symmetric ciphers, the S‐boxes are of static in nature. It will never depend or vary with respect to the message or the key, but dynamic S‐boxes are more resistant to linear and differential attacks when compared with the static S‐boxes. In this paper, we propose the design of a new dynamic colour table (DCT) that can be used as S‐box in symmetric ciphers and it depends upon a master key K . The same key can be used for encryption and decryption in symmetric ciphers. Dynamic colour table is a 64×4 table, having 256 entries. Each column of DCT has 64 unique values. The input to generate the DCT is 160 bit master key K . We have also developed a sub‐key generation algorithm for generating the sub keys and 4 seeds from the master key of 160 bits. These 4 seeds are used to generate the random values in DCT. Dynamic colour table uses the alpha red green blue (ARGB) colour model concept for each entry. Our DCT is so lightweight in nature. Our new DCT have a wide range of applications such as it can be used as S‐boxes in symmetric ciphers or it can be used as pseudorandom number generators. Finally, we show an implementation and the simulated results of DCT. The simulated results are used to analyse the strength of our DCT. The different criterions to verify that DCT has the characteristic of good S‐box are nonlinearity, strong avalanche criterion, bit Independence criterion, differential approximation probability, and linear approximation probability. The performance is measured in terms of time complexity and security. The results show that our DCT is cryptographically stronger to use in various symmetric encryption algorithms.     

Memristor-based combinational circuits: A design methodology for encoders/decoders

The crossbar architecture is viewed as the most likely path towards novel nanotechnologies which are expected to continue the technological revolution. Memristor-based crossbars for integrating memory units have received considerable attention, though little work has been done concerning the implementation of logic. In this work we focus on memristor-based complex combinational circuits. Particularly, we present a design methodology for encoder and decoder circuits. Digital encoders are found in a variety of electronics multi-input combinational circuits (e.g. keyboards) nowadays, converting the logic level ‘1’ data at their inputs into an equivalent binary code at the output. Their counterparts, digital decoders, constitute critical components for nanoelectronics, mainly in peripheral/interface circuitry of nanoelectronic circuits and memory structures. The proposed methodology follows a CMOS-like design scheme which can be used for the efficient design and mapping of any 2ⁿ×n (n×2ⁿ) encoder (decoder) onto the memristor-based crossbar geometry. For their implementation, a hybrid nano/CMOS crossbar type with memristive cross-point structures and available transistors is elaborated, which is a promising solution to the interference between neighboring cross-point devices during access operation. Circuit functionality of the presented encoder/decoder circuits is exhibited with simulations conducted using a simulator environment which incorporates a versatile memristor device model. The proposed design and implementation paradigm constitutes a step towards novel computational architectures exploiting memristor-based logic circuits, and facilitating the design and integration of memristor-based encoder/decoder circuits with nanoelectronics applications of the near future.     

Controlled elements for designing ciphers suitable to efficient VLSI implementation

This work considers the problem of increasing the performance of the ciphers based on Data-Dependent (DD) operations (DDO) for VLSI implementations. New minimum size primitives are proposed to design DDOs. Using advanced DDOs instead of DD permutations (DDP) in the DDP-based iterative ciphers Cobra-H64 and Cobra-H128 the number of rounds has been significantly reduced yielding enhancement of the “performance per cost” value and retaining security at the level of indistinguishability from a random transformation. To obtain further enhancement of this parameter a new crypto-scheme based on the advanced DDOs is proposed. The FPGA implementation of the proposed crypto-scheme achieves higher throughput value and minimizes the allocated resources than the conventional designs. Design of the DDO boxes of different orders is considered and their ASIC implementation is estimated.     

Exact reliability analysis of combinational logic circuits

A novel method is presented for the exact reliability analysis of combinational logic circuits. A model is developed that allows the logic circuit to be presented by a circuit equivalent graph (CEG). The reliability is analyzed by a systematic searching of certain subgraphs from the CEG. A computer algorithm and an example are given. The method gives the exact solution to the combinational logic circuit reliability-analysis problem. This is achieved by proper gate/circuit modeling, which allows the enumeration of all redundant fault vectors in a given circuit. Due to the concept of dominance among fault vectors, the number of necessary enumerations is appreciably reduced, and thus circuits with a few tens of gates can be efficiently analyzed     

CMOS数字电路功耗分析及其应用

讨论了有关ＣＭＯＳ数字电路的功耗分析和低功耗逻辑综合的一些方法。研究了信号的翻转概率与信号概率之间的关系，并由此得到信号翻转次数的表达式。然后讨论了使平均功耗最优的组合逻辑电路优化中的一些方法，最后，提出了两个用于低功耗逻辑综合的基本定理。     

Complex 3D CMOS circuits based on a triple-decker cell

Presents circuit design for a three-dimensional (3D) CMOS integrated process. This process, with its three stacked transistor channels, leads to the very efficient basic circuits: inverter, selector, and NAND2. These elements are used to build a complete cell library with standard elements like NORs, latches, flip-flops, etc. Special macro blocks such as multipliers, SRAMs and content addressable memories (CAMs) complete the circuit library. Novel concepts and implementations of three-dimensional prefabricated semicustom arrays are introduced. These are the NAND array and the selector array, for which technology-dependent logic synthesis is investigated. Area requirements for static 3-D CMOS logic ranges from 50% down to 33% compared to two-dimensional (2-D) CMOS. These figures include the wiring and are caused by the transistor stacking and the large number of interconnection layers used in the 3D CMOS process.<>     

Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion

This paper describes a tunable transient filter (TTF) design for soft error rate reduction in combinational logic circuits. TTFs can be inserted into combinational circuits to suppress propagated single-event transients (SETs) before they can be captured in latches or flip-flops. TTFs are tuned by adjusting the maximum width of the propagated SET that can be suppressed. A TTF requires 6–14 transistors, making it an attractive cost-effective option to reduce the soft error rate in combinational circuits. A global optimization approach based on geometric programming that integrates TTF insertion with dual-V _DD and gate sizing is described. Simulation results for the 65 nm process technology indicate that a 17–48× reduction in the soft error rate can be achieved with this approach.     

Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates

Soft errors caused by particles strike in combinational parts of digital circuits are a major concern in the design of reliable circuits. Several techniques have been presented to protect combinational logic and reduce the overall circuit Soft Error Rate (SER). Such techniques, however, typically come at the cost of significant area and performance overheads. This paper presents a low area and zero-delay overhead method to protect digital circuits’ combinational parts against particles strike. This method is made up of a combination of two sub-methods: (1) a SER estimation method based on signal probability, called Estimation by Characterizing Input Patterns (ECIP) and (2) a protection method based on gate sizing, called Weighted and Timing Aware Gate Sizing (WTAGS). Unlike the previous techniques that either overlook internal nodes signal probability or exploit fault injection, ECIP computes the sensitivity of each gate by analytical calculations of both the probability of transient pulse generation and the probability of transient pulse propagation; these calculations are based on signal probability of the whole circuit nodes which make ECIP much more accurate as well as practical for large circuits. Using the results of ECIP, WTAGS characterizes the most sensitive gates to efficiently allocate the redundancy budget. The simulation results show the SER reduction of about 40% by applying the proposed method to ISCAS’89 benchmark circuits while imposing no delay overhead and 5% area overhead.     

Subthreshold-current reduction circuits for multi-gigabit DRAM's

Two subthreshold-current reduction circuit schemes are described to suppress the increase in current in multi-gigabit DRAM's. One is a hierarchical power-line scheme for iterative circuits. In this scheme, a group of circuits is divided into blocks; only the selected block is supplied with power, while the subthreshold current to the many nonselected blocks is reduced. This scheme minimizes the number of circuits carrying the large subthreshold current. Applications of this scheme to word drivers, decoders and sense-amplifier driving circuits are shown. The other scheme is a switched-power-supply inverter with a level holder for random combinational logic circuits. In the active mode of the chip, the operating period of the inverter is distinguished from the inactive period. The inverter is supplied with power only in the operating period, while in the inactive period the subthreshold current is shut off and the output level is kept by the flip-flop level holder. This scheme shortens the period in which the large subthreshold current flows. Both schemes are evaluated for a conceptually-designed 16-Gb DRAM. They reduce its active current by ten-fold from the conventional 1.2 A to 116 mA     

基于比较器的四值电流型CMOS加减电路设计

该文通过对电流型CMOS电路的阈值控制引入了多值电流型比较器。与2值逻辑电路相比,多值逻辑电路的单条导线允许更多的信息传输。相较于电压信号,电流信号易实现加、减等算术运算,在多值逻辑的设计上更加方便。同时提出了基于比较器的4值基本单元设计方法,实现了4值取大、取小以及反向器的设计,在此基础上设计实现了加法器和减法器。该设计方法在2值、3值以及n值逻辑上同样适用。实验结果表明所设计的电路具有正确的逻辑功能,较之相关文献电流型CMOS全加器有更低的功耗和更少的晶体管数。