A 0.18μm CMOS 3-5 GHz broadband flat gain low noise amplifier

A 3-5 GHz broadband flat gain differential low noise amplifier (LNA) is designed for the impulse radio uitra-wideband (IR-UWB) system. The gain-flatten technique is adopted in this UWB LNA. Serial and shunt peaking techniques are used to achieve broadband input matching and large gain-bandwidth product (GBW). Feedback networks are introduced to further extend the bandwidth and diminish the gain fluctuations. The prototype is fabricated in the SMIC 0.18 μm RF CMOS process. Measurement results show a 3-dB gain bandwidth of 2.4-5.5 GHz with a maximum power gain of 13.2 dB. The excellent gain flatness is achieved with ±0.45 dB gain fluctuations across 3-5 GHz and the minimum noise figure (NF) is 3.2 dB over 2.5-5 GHz. This circuit also shows an excellent input matching characteristic with the measured S11 below-13 dB over 2.9-5.4 GHz. The input-referred 1-dB compression point (IPldB) is -11.7 dBm at 5 GHz. The differential circuit consumes 9.6 mA current from a supply of 1.8 V.     

A 0.18 μm CMOS 3-5 GHz broadband flat gain low noise amplifier

A 3-5 GHz broadband flat gain differential low noise amplifier(LNA) is designed for the impulse radio ultra-wideband(IR-UWB) system.The gain-flatten technique is adopted in this UWB LNA.Serial and shunt peaking techniques are used to achieve broadband input matching and large gain-bandwidth product(GBW).Feedback networks are introduced to further extend the bandwidth and diminish the gain fluctuations.The prototype is fabricated in the SMIC 0.18μm RF CMOS process.Measurement results show a 3-dB gain band...     

A 0.4–2.3 GHz broadband power amplifier extended continuous class-F design technology

A 0.4–2.3 GHz broadband power amplifier (PA) extended continuous class-F design technology is proposed in this paper. Traditional continuous class-F PA performs in high-efficiency only in one octave bandwidth. With the increasing development of wireless communication, the PA is in demand to cover the mainstream communication standards’ working frequencies from 0.4 GHz to 2.2 GHz. In order to achieve this objective, the bandwidths of class-F and continuous class-F PA are analysed and discussed by Fourier series. Also, two criteria, which could reduce the continuous class-F PA’s implementation complexity, are presented and explained to investigate the overlapping area of the transistor’s current and voltage waveforms. The proposed PA design technology is based on the continuous class-F design method and divides the bandwidth into two parts: the first part covers the bandwidth from 1.3 GHz to 2.3 GHz, where the impedances are designed by the continuous class-F method; the other part covers the bandwidth from 0.4 GHz to 1.3 GHz, where the impedance to guarantee PA to be in high-efficiency over this bandwidth is selected and controlled. The improved particle swarm optimisation is employed for realising the multi-impedances of output and input network. A PA based on a commercial 10 W GaN high electron mobility transistor is designed and fabricated to verify the proposed design method. The simulation and measurement results show that the proposed PA could deliver 40–76% power added efficiency and more than 11 dB power gain with more than 40 dBm output power over the bandwidth from 0.4–2.3 GHz.     

A low phase noise and low power 3–5 GHz frequency synthesizer in 0.18 µm CMOS technology

A low power frequency synthesizer for WLAN applications is proposed in this paper. The NMOS transistor-feedback voltage controlled oscillator (VCO) is designed for the purpose of decreasing phase noise. TSPC frequency divider is designed for widening the frequency range with keeping low the power consumption. The phase frequency detector (PFD) with XOR delay cell is designed to have the low blind and dead zone, also for neutralizing the charge pump (CP) output currents; the high gain operational amplifier and miller capacitors are applied to the circuit. The frequency synthesizer is simulated in 0.18 µm CMOS technology while it works at 1.8 V supply voltage. The VCO has a phase noise of −136 dBc/Hz at 1 MHz offset. It has 10.2% tuning range. With existence of a frequency divider in the frequency synthesizer loop the output frequency of the VCO can be divided into the maximum ratio of 18. It is considered that the power consumption of the frequency synthesizer is 4 mW and the chip area is 10,400 µm².     

Design of a 24–40 GHz balanced low noise amplifier using Lange couplers

A wide band （24–40 GHz） fully integrated balanced low noise amplifier （LNA） using Lange couplers was designed and fabricated with a 0.15 μm pseudomorphic HEMT （pHEMT） technology. A new method to design a low-loss and high-coupling Lange coupler for wide band application in microwave frequency was also presented. This Lange coupler has a minimum loss of 0.09 dB and a maximum loss of 0.2 dB over the bandwidth from 20 to 45 GHz. The measured results show that the realized four-stage balanced LNA using this Lange coupler exhibites a noise figure （NF） of less than 2.7 dB and the maximum gain of 30 dB; moreover, a noticeably improved reflection performance is achieved. The input VSWR and the output VSWR are respectively less than 1.45 and 1.35 dB across the 24–40 GHz frequency range.     

High linearity technique for ultra-wideband low noise amplifier in 0.18 μm CMOS technology

A linearization technique for ultra-wideband low noise amplifier (UWB LNA) has been designed and fabricated in standard 0.18 μm CMOS technology. The proposed technique exploits the complementary characteristics of NMOS and PMOS to improve the linearity performance. A two-stage UWB LNA is optimized to achieve high linearity over the 3.1-10.6 GHz range. The first stage adopts inverter topology with resistive feedback to provide high linearity and wideband input matching, whereas the second stage is a cascode amplifier with series and shunt inductive peaking techniques to extend the bandwidth and achieve high gain simultaneously. The proposed UWB LNA exhibits a measured flat gain of 15 dB within the entire band, a minimum noise figure of 3.5 dB, and an IIP3 of 6.4 dBm while consuming 8 mA from a 1.8 V power supply. The total chip area is 0.39 mm², including all pads. The measured input return loss is kept below −11 dB, and the output return loss is −8 dB, from 3.1 to 10.6 GHz.     

3.1–10.6 GHz ultra-wideband LNA design using dual-resonant broadband matching technique

This paper presents an ultra-wideband low noise amplifier design using the dual-resonant broadband matching technique. The proposed LNA achieves a 10.2 dB gain with ±0.9 dB gain flatness over a frequency range of 3.1–10.6 GHz and a ?3-dB bandwidth of 2.4–11.6 GHz. The measured noise figure ranges from 3.2 to 4.7 dB over 3.1–10.6 GHz. At 6.5 GHz, the measured IIP3 and input-referred P1dB are +6 dBm and ?5 dBm, respectively. The proposed LNA occupies an active chip area of 0.56 mm² in a TSMC 0.18 μm RF-CMOS process and consumes 16 mW from a 1.8 V supply.     

A 0.1–1 GHz low power RF receiver front-end with noise cancellation technique for WSN applications

A low power 0.1–1 GHz RF receiver front-end composed of noise-cancelling trans-conductor stage and I/Q switch stage was presented in this paper. The RF receiver front-end chip was fabricated in 0.18 µm RF CMOS. Measurement results show the receiver front-end has a conversion gain of 28.1 dB at high gain mode, and the single-sideband (SSB) noise figure is 6.2 dB. In the low gain mode, the conversion gain of the receiver front-end is 15.5 dB and the IP1dB is −12 dBm. In this design, low power consumption and low cost is achieved by current-reuse and inductor-less topology. The receiver front-end consumes only 5.2 mW from a 1.8 V DC supply and the chip size of the core circuit is 0.12 mm².     

A 2 GHz variable gain low noise amplifier in 0.18-μm CMOS

This paper describes a 2 GHz active variable gain low noise amplifier (VGLNA) in a 0.18-μm CMOS process. The VGLNA provides a 50-Ω input impedance and utilizes a tuned load to provide high selectivity. The VGLNA achieves a maximum small signal gain of 16.8 dB and a minimum gain of 4.6 dB with good input return loss. In the high gain and the low gain modes, the NFs are 0.83 dB and 2.8 dB, respectively. The VGLNA’s IIP3 in the high gain mode is 2.13 dBm. The LNA consumes approximately 4 mA of current from a 1.8-V power supply.     

A 50 MHz-1 GHz high linearity CATV amplifier with a 0.15μm InGaAs PHEMT process

A 50 MHz-1 GHz low noise and high linearity amplifier monolithic-microwave integrated-circuit (MMIC) for cable TV is presented.A shunt AC voltage negative feedback combined with source current negative feedback is adopted to extend the bandwidth and linearity.A novel DC bias feedback is introduced to stabilize the operation point,which improved the linearity further.The circuit was fabricated with a 0.15μm InGaAs PHEMT (pseudomorphic high electron mobility transistor) process.The test was carried out in 75Ωsystems from 50 MHz to 1 GHz.The measurement results showed that it gave a small signal gain of 16.5 dB with little gain ripples of less than±1dB.An excellent noise figure of 1.7-2.9 dB is obtained in the designed band.The IIP3 is 16 dBm, which shows very good linearity.The CSO and CTB are high up to 68 dBc and 77 dBc,respectively.The chip area is 0.56 mm~2 and the power dissipation is 110 mA with a 5 V supply.It is ideally suited to cable TV systems.     

Design a novel 5.8 GHz wideband low noise amplifier in CMOS technology for WLAN applications

A novel complementary metal-oxide semiconductor (CMOS) low noise amplifier (LNA) was designed in this paper for wireless local area network (WLAN) applications in the 5.8?GHz ISM band. The LNA presents low voltage and low power dissipation design integrated in TSMC 0.18?µm standard CMOS technology and achieves a gain of 15.2?dB, a noise figure of 2.5?dB and an IIP3 of ?6.5?dBm with input return loss ?38.5?dB, output return loss of ?46.1?dB while dissipating just 4.96 mW from a 1V supply voltage.     

Design of a low noise distributed amplifier with adjustable gain control in 0.15μm GaAs PHEMT

正A low noise distributed amplifier consisting of 9 gain cells is presented.The chip is fabricated with 0.15-μm GaAs pseudomorphic high electron mobility transistor(PHEMT) technology from Win Semiconductor of Taiwan.A special optional gate bias technique is introduced to allow an adjustable gain control range of 10 dB.A novel cascode structure is adopted to extend the output voltage and bandwidth.The measurement results show that the amplifier gives an average gain of 15 dB with a gain flatness of±1 dB in the 2-20 GHz band.The noise figure is between 2 and 4.1 dB during the band from 2 to 20 GHz.The amplifier also provides 13.8 dBm of output power at a 1 dB gain compression point and 10.5 dBm of input third order intercept point(IIP3),which demonstrates the excellent performance of linearity.The power consumption is 300 mW with a supply of 5 V,and the chip area is 2.36×1.01 mm~2.     

1–8 GHz high efficiency single-stage travelling wave power amplifier

This paper describes a Class-A/AB wideband power amplifier that comprises of a single-stage transistor travelling wave structure in which capacitive coupling and frequency dependent lossy artificial-line are employed at the input of the active device. The proposed technique significantly enhances the amplifier’s gain-bandwidth product, input match and gain flatness performance. To ensure the amplifier delivers a predefined power to the load over its entire operating band 2-to-8 GHz a broadband load-pull technique was applied at the output of the amplifier. To avoid reduction in the amplifier’s bandwidth resulting from parasitic capacitive effects associated with the off-chip choke inductor a wideband RF choke was designed. The 1.31 × 2.93 mm² power amplifier was fabricated using 0.25 μm GaAs pHEMT MMIC process. The measurement results show that the proposed amplifier delivers an average P _sat of 29.5 dBm and P _out,1 dB of 26 dBm, and the corresponding PAE levels are 55 and 35 % for the P _sat and P _out,1 dB, respectively.     

A 5–7 GHz current reuse and g<Subscript>m</Subscript>-boosted common gate low noise amplifier with LC based ESD protection in 32 nm CMOS

Scaling of minimum length of the MOSFET has improved its performance but has reduced the breakdown voltage which makes it prone to Electrostatic Discharge (ESD) damage. This work presents a low-power g _m -boosted common gate (CG) ultra wideband (UWB) low noise amplifier (LNA) architecture, operating in the 5–7 GHz range, employing current-reuse technique with LC based Electrostatic Discharge (ESD) protection. Common gate topology supports wide band input matching and noise figure independent of operating frequency. A PMOS common source topology is used as the g_m-boosting stage in order to reduce the noise figure and to remove the dependency of noise figure from the bias point. The g_m-boosting stage and the amplifier share common bias current to reduce the power consumption of the LNA. A shunt inductor, series capacitor and power clamp are used for protecting the circuit from ESD damage. The ESD circuit is co-designed with the input matching network in order to reduce the area of the layout. The proposed topology has shown significant improvement in gain and noise figure with ESD protection.     

A low-power,low-noise and high linearity 60 GHz wideband CMOS low-noise amplifier for wireless personal area network (WPAN) systems

A low power and low noise figure (NF) 60 GHz wideband low-noise amplifier (LNA) with excellent phase linearity for wireless personal local network (WPAN) systems using standard 90 nm CMOS technology is reported. To achieve sufficient power gain (S₂₁) and reverse isolation (S₁₂), the LNA comprises a common-source (CS) stage followed by a cascode stage and a CS stage. The LNA consumes 14.1 mW, achieving S₁₁ better than ?10 dB for frequencies 55.1–59.5 GHz, S₂₂ better than ?10 dB for frequencies 55.1–59.4 GHz, S₁₂ better than ?42.6 dB for frequencies 50–64 GHz, and group delay variation smaller than ±13.25 ps for frequencies 50.4–63 GHz. Additionally, high and flat S₂₁ of 9.9 ± 1.5 dB is achieved for frequencies 50.4–62.9 GHz, which means the corresponding 3-dB bandwidth is 12.5 GHz. Furthermore, the LNA achieves minimum NF of 3.88 dB at 55.5 GHz and NF of 4.73 ± 0.85 dB for frequencies 50–63.5 GHz, one of the best NF results ever reported for a 60 GHz CMOS LNA.     

2 to 23 GHz BiFET low noise amplifier design flow and implementations in 0.25 μm SiGe BiCMOS technology

Two BiFET LNAs are here reported, implemented in a 0.25 μm BiCMOS technology from ST Microelectronics. First of them, dedicated to WCDMA standard, depicts a 15.5 and 2.85 dB, S₂₁ and noise figure (NF), respectively, under 2 mA current consumption. The second realization operates at 23 GHz for Mini-Link application. It provides a 14 dB gain and 7 dB at 22 GHz NF for an 8.2 mA current consumption under 2.5 V. Both circuits were designed according to a design flow, here depicted, based on input matching, NF and gain optimisation. A large part of the article also deals with high frequency layout considerations. Indeed useful techniques dedicated to integrated microstrip waveguides and RF inter-connections are proposed based on 3D electromagnetic field simulations.     

Design of variable gain low noise amplifier using feedback circuit with memory circuits for 5.2 GHz band

This paper presents a novel adaptive gain control method for Low Noise Amplifiers (LNAs) at the 5.2 GHz band using a feedback circuit, and operating in the baseband signal frequency. A uniform step variable gain can be implemented using a two-stage LNA based on the cascade topology. The feedback circuit consists of seven functional blocks, each of which has been designed for minimum power consumption. The storage circuit in the feedback circuit is used to store the previous signal magnitude, thus avoiding unnecessary power consumption in the LNA. We simulated the performances of LNA in terms of the gain, IIP3, Noise Figure (NF), stability, and power consumption. The adaptive front-end LNA with the feedback circuit can achieve a variable gain from 11.39 dB to 22.74 dB with excellent noise performance even at a high gain mode. The DC power of the proposed variable gain LNA consumes 5.68–6.75 mW under a 1.8 V supply voltage.     

A high-performance 1.2 V–99 μW rail-to-rail CMOS class AB amplifier

This paper presents a compact, reliable 1.2 V low-power rail-to-rail class AB operational amplifier (OpAmp) suitable for integrated battery powered systems which require rail-to-rail input/output swing and high slew-rate while maintaining low power consumption. The OpAmp, fabricated in a standard 0.18 μm CMOS technology, exhibits 86 dB open loop gain and 97 dB CMRR. Experimental measurements prove its correct functionality operating with 1.2 V single supply, performing very competitive characteristics compared with other similar amplifiers reported in the literature. It has rail-to-rail input/output operation, 5 MHz unity gain frequency and a 3.15 V/μs slew-rate for a capacitive load of 100 pF, with a power consumption of 99 μW.