Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

This paper presents a novel approach for implementing ultra-low-power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (subthreshold) regime. Minimum size pMOS transistors with shorted drain-substrate contacts are used as gate-controlled, very high resistivity load devices. Based on the proposed approach, the power consumption and the operation frequency of logic circuits can be scaled down linearly by changing the tail bias current of SCL gates over a very wide range spanning several orders of magnitude, which is not achievable in subthreshold CMOS circuits. Measurements in conventional 0.18 m CMOS technology show that the tail bias current of each gate can be set as low as 10 pA, with a supply voltage of 300 mV, resulting in a power-delay product of less than 1 fJ. Fundamental circuits such as ring oscillators and frequency dividers, as well as more complex digital blocks such as parallel multipliers designed by using the STSCL topology have been experimentally characterized.     

Leakage Current Reduction Using Subthreshold Source-Coupled Logic

The performance of subthreshold source-coupled logic (STSCL) circuits for ultra-low-power applications is explored. It is shown that the power consumption of STSCL circuits can be reduced well below the subthreshold leakage current of static CMOS circuits. STSCL circuits exhibit a better power–delay performance compared with their static CMOS counterparts in situations where the leakage current constitutes a significant part of the power dissipation of static CMOS gates. The superior control on power consumption, in addition to the lower sensitivity to the process and supply voltage variations, makes the STSCL topology very suitable for implementing ultra-low-power low-frequency digital systems in modern nanometer-scale technologies. An analytical approach for comparing the power–delay performance of these two topologies is proposed.      

Circuits and architectures for field programmable gate array with configurable supply voltage

Field programmable gate arrays (FPGAs) with supply voltage (Vdd) programmability have been proposed recently to reduce FPGA power, where the Vdd-level can be customized for FPGA circuit elements and unused circuit elements can be power-gated. In this paper, we first design novel Vdd-programmable and Vdd-gateable interconnect switches with minimal number of configuration SRAM cells. We then evaluate Vdd-programmable FPGA architectures using the new switches. The best architecture in our study uses Vdd-programmable logic blocks and Vdd-gateable interconnects. Compared to the baseline architecture similar to the leading commercial architecture, our best architecture reduces the minimal energy-delay product by 54.39% with 17% more area and 3% more configuration SRAM cells. Our evaluation results also show that LUT size 4 gives the lowest energy consumption, and LUT size 7 leads to the highest performance, both for all evaluated architectures.     

Study of Scaling Trends in Energy Recovery Logic: An Analytical Approach

This paper presents an analytical model to study the scaling trends in energy recovery logic. The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage, device threshold voltage and gate oxide thickness. The proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the nanoscale. This research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.     

Measuring and Modeling the Power Consumption of Energy-Efficient FPGA Coprocessors for GEMM and FFT

In this paper we analyze the power consumption and energy efficiency of general matrix-matrix multiplication (GEMM) and Fast Fourier Transform (FFT) implemented as streaming applications for an FPGA-based coprocessor card. The power consumption is measured with internal voltage sensors and the power draw is broken down onto the systems components in order to classify the energy consumed by the processor cores, the memory, the I/O links and the FPGA card. We present an abstract model that allows for estimating the power consumption of FPGA accelerators on the system level and validate the model using the measured kernels. The performance and energy consumption is compared against optimized multi-threaded software running on the POWER7 host CPUs. Our experimental results show that the accelerator can improve the energy efficiency by an order of magnitude when the computations can be undertaken in a fixed point format. Using floating point data, the gain in energy-efficiency was measured as up to 30 % for the double precision GEMM accelerator and up to 5 × for a 1k complex FFT.     

三种改进结构型BiCMOS逻辑单元的研究

为满足低压、高速、低耗数字系统的应用需求 ,通过采用改进电路结构和优化器件参数的方法 ,设计了三种改进结构型BiCMOS逻辑单元电路。实验结果表明 ,所设计电路不但具有确定的逻辑功能 ,而且获得了高速、低压、低耗和接近于全摆幅的特性 ,它们的工作速度比高速CMOS和原有的互补对称BiCMOS(CBiCMOS)电路快约一倍 ,功耗在 6 0MHz频率下仅高出 1 4 9～ 1 71mW ,但延迟 功耗积却比原CBiCMOS电路平均降低了4 0 3%。     

Technology leverage for ultra-low power information systems

Many applications for future generations of logic and memory chips will be requiring highly sophisticated computing functions at low cost. Small form factors, portability, and low cost will require low power operation. While continued scaling of silicon technology to dimensions below quarter micron devices and interconnections appears technically feasible, higher levels of integration and operation at higher speed have been driving the power consumption of logic chips up instead of down. This paper discusses how scaled submicron silicon technology can provide leverage to reduce power, while gaining in throughput for logic chips, and in capacity for memory functions. Strong reductions in voltage supply have to accompany shrinking dimensions. Materials limits such as tunneling currents through ultra-thin silicon-dioxide gate dielectrics and electromigration in minimum pitch interconnections emerge to be key challenges to realize low power 0.1 μm level CMOS circuits. A more than 10× gain in productivity as measured by the energy*delay product can be realized by shrinking from 0.5-0.125 μm CMOS device technology     

Minimal Energy Asynchronous Dynamic Adders

In battery-operated portable or implantable digital devices, where battery life needs to be maximized, it is necessary to minimize not only power consumption but also energy dissipation. Typical energy optimization measures include voltage reduction and operating at the slowest possible speed. We employ additional methods, including hybrid asynchronous dynamic design to enable operating over a wide range of battery voltage, aggregating large combinational logic blocks, and transistor sizing and reordering. We demonstrate the methods on simple adders, and discuss extension to other circuits. Three novel adders are proposed and analyzed: a 2-bit pass transistor logic (PTL) adder and two dynamic 2-bit adders. Circuit simulations on a 0.18-mum process at low voltage show that leakage energy is below 1%. The proposed adders achieve up to 40% energy savings relative to previously published results, while also operating faster     

An Ultra-Low-Power Integrated RF Energy Harvesting System in 65-nm CMOS Process

In recent years, radio frequency (RF) energy harvesting systems have gained significant interest as inexhaustible replacements for traditional batteries in RF identification and wireless sensor network nodes. This paper presents an ultra-low-power integrated RF energy harvesting circuit in a SMIC 65-nm standard CMOS process. The presented circuit mainly consists of an impedance-matching network, a 10-stage rectifier with order-2 threshold compensation and an ultra-low-power power manager unit (PMU). The PMU consists of a voltage sensor, a voltage limiter and a capacitor-less low-dropout regulator. In the charge mode, the power consumption of the proposed energy harvesting circuit is only 97 nA, and the RF input power can be as low as \(-\)21.4 dBm \((7.24\,\upmu \hbox {W})\). In the burst mode, the device can supply a 1.0-V DC output voltage with a maximum 10-mA load current. The simulated results demonstrate that the modified RF rectifier can obtain a maximum efficiency of 12 % with a 915-MHz RF input. The circuit can operate over a temperature range from \(-40\hbox { to }125\,^{\circ }\hbox {C}\) which exceeds the achievable temperature performance of previous RF energy harvesters in standard CMOS process.     

Characterization of Single-Electron Tunneling Transistors for Designing Low-Power Embedded Systems

Minimizing power consumption is vitally important in embedded system design; power consumption determines battery lifespan. Ultra-low-power designs may even permit embedded systems to operate without batteries by scavenging energy from the environment. Moreover, managing power dissipation is now a key factor in integrated circuit packaging and cooling. As a result, embedded system price, size, weight, and reliability are all strongly dependent on power dissipation. Recent developments in nanoscale devices open new alternatives for low-power embedded system design. Among these, single-electron tunneling transistors (SETs) hold the promise of achieving the lowest power consumption. Unfortunately, most analysis of SETs has focused on single devices instead of architectures, making it difficult to determine whether they are appropriate for low-power embedded systems. Evaluating the use of SETs in large-scale digital systems requires novel architectural and circuit design. SET-based design imposes numerous challenges resulting from low driving strength, relatively large static power consumption, and the presence of reliability problems resulting from random background charge effects. We propose a fault-tolerant, hybrid SET/CMOS, reconfigurable architecture, named IceFlex, that can be tailored to specific requirements and allows tradeoffs among power consumption, performance requirements, operation temperature, fabrication cost, and reliability. Using IceFlex as a testbed, we characterize the benefits and limitations of SETs in embedded system designs. In particular, we focus on the use of SETs in room-temperature ultra-low-power embedded systems such as wireless sensor network nodes. We also consider high-performance applications such as multimedia consumer electronics. We see this work as a first step in determining the potential of ultra-low-power embedded system design using SETs.     

Building ultra-low-power high-temperature digital circuits in standard high-performance SOI technology

For ultra-low-power applications, digital integrated circuits may operate at low frequency to reduce dynamic power consumption. At high temperature, the power consumption of such circuits is completely dominated by static power dissipation due to leakage currents. In this contribution, we propose a new logic style, namely ultra-low-power (ULP) logic style which achieves negative V_gs self-biasing, to benefit from the small area and low dynamic power of high-performance deep-submicron SOI technologies while keeping ultra-low leakage, even at high temperature. In 0.13 μm partially-depleted SOI CMOS technology, the static power consumption at 200 °C is reduced by nearly three orders of magnitude at the expense of increased delay and area.     

一种FPGA低功耗工作的实现方法

FPGA(Field-Programmable Gate Array)即现场可编程门阵列,作为专用集成电路(ASIC)领域中的一种半定制电路,具有成本低、可在线编程等优势,其并行运算的特点适用于大规模信号处理和数据计算等场合.随着近年来FPGA内部逻辑单元数量的提高以及片上系统的出现,应用范围更加广泛,功耗也相应增加.本文提出了一种FPGA低功耗工作的实现方法,利用外部CPU管理FPGA的电源电路,在FPGA程序挂起时降低动态功耗,特别是对需要电池的便携设备电池供电产品,可有效延长工作时间.     

High performance level conversion for dual V/sub DD/ design

Multi-V/sub DD/ design is an effective way to reduce power consumption, but the need for level conversion imposes delay and energy penalties that limit the potential gains. In this paper, we describe new level converting circuits that provide 10%-61% lower energy consumption at equivalent or better speeds compared to those available in the literature. Furthermore, we make the argument that level converters should be evaluated largely by their maximum speed since slower level converters consume valuable timing slack that can be used to reduce the energy of other gates in the circuit. Based on this criterion, we find the new structures to offer up to a 25% speed improvement over conventional level converters. Using an efficient dual V/sub DD/ voltage assignment algorithm, we show that this speed improvement can yield a reduction of up to 7.3% in total circuit power in small benchmark circuits. We also propose embedding the functionality of logic gates into the level converting circuits. For typical values of the second supply voltage, this technique can reduce delay by 15% at constant energy or lower energy by up to 30% at fixed delay.     

Architecture level optimization of 3-dimensional tree-based FPGA

We describe a methodology to design and optimize Three-dimensional (3D) Tree-based FPGA by introducing a break-point at particular tree level interconnect to optimize the speed, area, and power consumption. The ability of the design flow to decide a horizontal or vertical network break-point based on design specifications is a defining feature of our design methodology. The vertical partitioning is organized in such a way to balance the placement of logic blocks and switch blocks into multiple tiers while the horizontal partitioning optimizes the interconnect delay by segregating the logic blocks and programmable interconnect resources into multiple tiers to build a 3D stacked Tree-based FPGA. We finally evaluate the effect of Look-Up-Table (LUT) size, cluster size, speed, area and power consumption of the proposed 3D Tree-based FPGA using our home grown experimental flow and show that the horizontal partitioned 3D stacked Tree-based FPGA with LUT and cluster sizes equal to 4 has the best area-delay product to design and manufacture 3D Tree-based FPGA.     

一种基于FPGA的嵌入式块SRAM的设计

文章中提出了一种应用于FPGA的嵌入式可配置双端口的块存储器。该存储器包括与其他电路的布线接口、可配置逻辑、可配置译码、高速读写电路。在编程状态下,可对所有存储单元进行清零,且编程后为两端口独立的双端存储器。当与FPGA其他逻辑块编程连接时,能实现FIFO等功能。基于2.5V电源电压、chart0.22μm CMOS单多晶五铝工艺设计生产,流片结果表明满足最高工作频率200MHz,可实现不同位数存储器功能。     

A Low-Power Field-Programmable Gate Array Routing Fabric

This paper describes a new programmable routing fabric for field-programmable gate arrays (FPGAs). Our results show that an FPGA using this fabric can achieve 1.57 times lower dynamic power consumption and 1.35 times lower average net delays with only 9% reduction in logic density over a baseline island-style FPGA implemented in the same 65-nm CMOS technology. These improvements in power and delay are achieved by 1) using only short interconnect segments to reduce routed net lengths, and 2) reducing interconnect segment loading due to programming overhead relative to the baseline FPGA without compromising routability. The new routing fabric is also well-suited to monolithically stacked 3-D-IC implementation. It is shown that a 3-D-FPGA using this fabric can achieve a 3.3 times improvement in logic density, a 2.51 times improvement in delay, and a 2.93 times improvement in dynamic power consumption over the same baseline 2-D-FPGA.     

Cycle-Accurate Energy Measurement and Characterization of FPGAs

Field Programmable Gate Arrays (FPGAs) play many important roles, ranging from small glue logic replacement to System-on-Chip (SoC) designs. Nevertheless, FPGA vendors cannot accurately specify the power consumption of their products on device data sheets because the power consumption of FPGAs is strongly dependent on the target circuit, including resource utilization, logic partitioning, mapping, placement and routing. Although major CAD tools have started to report average power consumption under given transition activities, power-efficient FPGA design demands more detailed information about power consumption. In this paper, we introduce an in-house cycle-accurate FPGA energy measurement tool and energy characterization schemes spanning low-level to high-level design. This tool offers all the capabilities necessary to investigate the energy consumption of FPGAs for operation-based energy characterization, which is applicable to high-level and system-wide energy estimation. It also includes features for low-level energy characterization. We compare our tool with Xilinx XPower and demonstrate the state-machine-based energy characterization of an SDRAM controller.The RIACT at Seoul National University provide research facilities for this study. This work was partly supported by the Brain Korea 21 Project.Hyung Gyu Lee received the B.S. degree in Dept. of Computer Engineering from DongGuk University, in 1999, M.S. degree in School of Computer Science and Engineering from Seoul National University, Seoul, Korea, in 2001, and is currently working toward the Ph.D. degree at Seoul National University. His research interests include device-level energy measurement and characterization, system-level low power design and low-power FPGA design.KyungSoo Lee is a M.S. student at the School of Computer Science and Engineering, Seoul National University. He received the B.S. degree in the School of Computer Science and Engineering from Seoul National University, Seoul, Korea, in 2004. He is currently working on low-power systems and embedded systems for his M.S. degree.Yongseok Choi received the B.S. and M.S. degree in the School of Computer Science and Engineering from Seoul National University, Seoul, Korea, in 2000 and 2002, respectively. He is currently working toward the Ph.D. degree in the School of Computer Science and Engineering at Seoul National University. His research interests include embedded systems and low power systems.Naehyuck Chang received his B.S., M.S. and Ph.D. degrees all from Dept. of Control and Instrumentation Engineering, Seoul National University, Seoul, Korea, in 1989, 1992 and 1996, respectively. Since 1997, he has been with School of Computer Science and Engineering, Seoul National University and currently is an Associate Professor. His research interest includes system-level low-power design and embedded systems design.     

On the use of high-impedance power supplies to reduce the substrate switching noise in system-on-chips

This paper analyzes the generation and the propagation in system-on-chips of the switching noise due to embedded core logic blocks. Such disturbances contribute to degrade the performance of the other on-chip circuits and cause unwanted electromagnetic emission. These parasitic effects can be largely ascribed to the steep currents that flow into the power supply interconnects of the core logic blocks and to the parasitic coupling of the system-on-chip building blocks through the silicon substrate they share.In this work it is shown that the substrate voltage bounce due to the switching noise can be significantly attenuated if conventional low-impedance DC power supplies are replaced by high-impedance one. The effectiveness of the proposed approach is validated through computer simulations and experimental tests carried out on the digital core block of a test chip.     

A novel robust FPGA routing switch box design for ultra low power applications

Fabrication cost of application-specific integrated circuits (ASICs) is exponentially rising in deep submicron region due to rapidly rising non-recurring engineering cost. Field programmable gate arrays (FPGAs) provide an attractive alternative to ASICs but consume an order of magnitude higher power. There is a need to explore ways of reducing FPGA power consumption so that they can also be employed in ultra low power (ULP) applications instead of ASICs. Subthreshold region of operation is an ideal choice for ULP low-throughput FPGAs. The routing of an FPGA consumes most of the chip area and primarily determines the circuit delay and power consumption. There is a need to design moderate-speed ULP routing switches for subthreshold FPGA. This article proposes a novel subthreshold FPGA routing switch box (SB) that utilises the leakage voltage through transistor as biasing voltage which shows 69%, 61.2% and 30% improvement in delay, power delay product and delay variation, respectively, over conventional routing SB.     

一种基于新型欠压闭锁电路的能量收集方法

目前自供电无线压电传感器网络已被广泛应用在智能家居及环境监测等领域.组成网络的每个压电传感器节点需要完成不同功耗的任务,如数据采集、存储等低功耗任务和数据无线传输的高功耗任务.针对低功耗和高功耗任务,该文设计了基于新型欠压闭锁电路的双模组能量收集电路,电路具有蓄能周期短和容量大的特点,可分别用于低功耗任务的低功耗级蓄能...