INDEP approach for leakage reduction in nanoscale CMOS circuits

Complementary metal oxide semiconductor (CMOS) technology scaling for improving speed and functionality turns leakage power one of the major concerns for nanoscale circuits design. The minimization of leakage power is a rising challenge for the design of the existing and future nanoscale CMOS circuits. This paper presents a novel, input-dependent, transistor-level, low leakage and reliable INput DEPendent (INDEP) approach for nanoscale CMOS circuits. INDEP approach is based on Boolean logic calculations for the input signals of the extra inserted transistors within the logic circuit. The gate terminals of extra inserted transistors depend on the primary input combinations of the logic circuits. The appropriate selection of input gate voltages of INDEP transistors are reducing the leakage current efficiently along with rail to rail output voltage swing. The important characteristic of INDEP approach is that it works well in both active as well as standby modes of the circuits. This approach overcomes the limitations created by the prevalent current leakage reduction techniques. The simulation results indicate that INDEP approach mitigates 41.6% and 35% leakage power for 1-bit full adder and ISCAS-85 c17 benchmark circuit, respectively, at 32 nm bulk CMOS technology node.     

Dynamic SVL and body bias for low leakage power and high performance in CMOS digital circuits

In this article, a new complementary metal oxide semiconductor design scheme called dynamic self-controllable voltage level (DSVL) is proposed. In the proposed scheme, leakage power is controlled by dynamically disconnecting supply to inactive blocks and adjusting body bias to further limit leakage and to maintain performance. Leakage power measurements at 1.8?V, 75°C demonstrate power reduction by 59.4% in case of 1?bit full adder and by 43.0% in case of a chain of four inverters using SVL circuit as a power switch. Furthermore, we achieve leakage power reduction by 94.7% in case of 1?bit full adder and by 91.8% in case of a chain of four inverters using dynamic body bias. The forward body bias of 0.45?V applied in active mode improves the maximum operating frequency by 16% in case of 1?bit full adder and 5.55% in case of a chain of inverters. Analysis shows that additional benefits of using the DSVL and body bias include high performance, low leakage power consumption in sleep mode, single threshold implementation and state retention even in standby mode.     

Improved accuracy equation for propagation delay of a CMOS inverter in a single ended ring oscillator

In this paper the issue of obtaining an accurate equation for the delay of a CMOS inverter is explored. In the conventional equations provided for the propagation delay, many simplifying assumptions are made. Also some important events that occur during the charging/discharging of the capacitances are neglected. This reduces the accuracy of the conventional delay equations. Since the propagation delay time is used in many applications, such as obtaining the ring oscillator frequency, its accuracy is very important. Hence, we calculate an accurate equation for the propagation delay time. The intricacies and challenges in deriving an improved accuracy equation will be addressed. The approach of deriving an improved equation is explained in detail. The accuracy of the derived equation is verified through simulation. We will look into the obtained equation to evaluate the effect of different parameters on the delay and compare the improved and conventional equations.     

Design of a three-stage ring-type voltage-controlled oscillator with a wide tuning range by controlling the current level in an embedded delay cell

This paper presents a new design for a three-stage voltage-controlled differential ring oscillator embedded with a delay cell for a wide tuning range from 59 MHz to 2.96 GHz by adjusting the current level in the delay cell. The ring oscillator consists of a voltage-to-current converter, coder circuit, three-stage ring with delay cells, and current monitoring circuit to extend the tuning range of the proposed voltage-controlled oscillator. Each functional block has been designed for a minimum power consumption using the TSMC 0.18 μm CMOS technology. We simulate the performances of the proposed voltage-controlled oscillator in terms of phase noise, power consumption, tuning range, and gain. Our simulation results show that the proposed oscillator has the linear frequency–voltage characteristics over a wide tuning range. At each tuning range (mode), the calculated phase noise of the proposed ring oscillator at each tuning range (mode) was −87, −85, −81, and −79 dBc/Hz at a 1 MHz offset from the center frequency. The DC power of the proposed voltage-controlled oscillator consumed 0.86–3 mW under a 1.8 V supply voltage.     

Effect of the discharging and recharging of the stress generated oxide charge in metal–oxide–semiconductor capacitors on the low field leakage current

Low field leakage currents, through thin gate oxides of metal-oxide-semiconductor capacitors, increase after negative high field stress. We have observed that this increase could be reduced and even suppressed if the trapped holes created by the stress were neutralized by application of low voltage pulses. We have also observed that these pulses had the effect of making the recharge of the stress created slow states more and more difficult.     

Temperature dependence of minority hole mobility in n+-GaAs measured with a new variable temperature technique

The temperature-dependent mobility provides essential information for device design and serves as a sensitive probe of minority carrier scattering physics. As examples, dominant scattering mechanisms are identified by characteristic temperature dependencies of mobility and for low temperature bipolar device optimization, accurate minority carrier mobility data are required. We report the first temperature (T) dependent measurement of minority hole mobility in n⁺-GaAs. The minority carrier mobility (μ) was measured with the zero-field time-of-flight technique. In this technique, minority carrier diffusivity (D), where De = μkT, is determined from the transient response of a specially designed photodiode that is excited by a high-speed laser. We have extended the technique to permit continuously variable, T-dependent minority mobility measurements. The unique cryostat design, including device mounting, low-loss feedthroughs and temperature measurement scheme, is presented.     

Design and development of a digital farmer field school. Experiences with a digital learning environment for cocoa production and certification in Sierra Leone

This article reports on the design and development of the Digital Farmer Field School (DFFS). The DFFS offers a tablet-based digital learning environment for farmers and extension agents for knowledge sharing and knowledge co-creation. It provides an alternative to conventional agricultural extension training and monitoring. The prototype DFFS applies Farmer Field School (FFS) learning principles and is designed and developed following user experience (UX) design principles and user interface (UI) design principles from a responsible innovation perspective, using existing FFS material and tailored films which support and enrich the content. The prototype DFFS has been tested in Sierra Leone to assess its success in providing a substitute for face-to-face voluntary sustainability standard certification training for cocoa farmers. Results show that the DFFS as an off-line, telephonically connected and regular on-line updated learning platform offers an appropriate environment in which collective and individual learning is stimulated and facilitated. The DFFS prototype was socio-culturally and technologically appropriate and fitted the operational and strategic communication skills of cocoa farmers and other value chain stakeholders. Films capturing the testing are available as additional learning media.     

一种直扩信号伪码周期及序列的盲估计方法

论述了功率谱二次处理理论和信号子空间分解方法在直接序列扩频(DS/SS)信号的伪码周期估计以及伪码序列盲估计中的应用,提出了利用功率谱二次处理结合信号子空间分解的方法以实现对低信噪比DS/SS信号的完全估计.计算机模拟结果表明,该方法在较低的输入信噪比条件下能良好地工作.     

EVM and BER Simulation of an NADC-TDMA Radiophone Influenced by the Operator's Body in Urban Mobile Environments

This paperpresents the performance evaluation of a portable digital radiophoneinfluencedby the operator's body in urban mobile environments, based on the EVM (errorvector magnitude) and BER (bit error rate) simulation. The type of digitalmodulation follows to the NADC-TDMA standard. A new probability densityfunction(pdf) is proposed to describe the statistic of the EVM in an AWGNchannelunder frequency non-selective slowly fading situation. The simulation combinesthe modified Doppler power spectrum (MDPS) method and a gray coding(/4-DQPSK modulation with square-root raised cosine (SRRC) shaping filter.The performance evaluation based on BER uses an ideal matched-filter-basedreceiver. The results show that the closer of the distance between theradiophone antenna and the operator's head, the poorer of the EVM and BERperformance.     

基于灰度统计的粒子图像速度粒度实时测量新技术

本文提出了一种基于灰度统计判别原理,可以对粒子图像实现速度和粒径实时同时测量的新技术--粒子图像速度粒度场仪.粒子图像速度粒度场仪通过灰度判别解决了DPIV粒子图像中方向二义性问题,简化了DPIV系统,利用图像处理技术实现了对粒子图像粒径的同时测量.以DPIV粒子图像为研究对象,结合图像处理技术,开发了相应的查询算法,实现了速度粒度的同场测量,并利用模拟粒子图像对查询算法进行了分析检验.通过算法检验表明,速度粒度同场测量算法能够很好地处理各种模拟粒子图像,满足未来实际应用对计算精度及测量时间的要求.     

同步时钟偏差存在下的时差定位性能分析及改进的定位方法

同步时钟偏差会显著增加时差（TDOA）定位误差,该文针对这一问题进行了理论性能分析,并提出了改进方法.首先,分析了时钟偏差存在下参数估计方差的克拉美罗界（CRB）,给出了关于目标位置估计方差更为闭式的CRB表达式,随后基于最大似然（ML）估计准则和泰勒级数（TS）定位方法,定量推导了时钟偏差对于TDOA定位精度的影响.接着,提出了可抑制时钟偏差的降维TS定位方法,并且给出了时钟偏差的ML闭式解.最后,数值实验验证了文中理论分析的有效性,并且新方法可以有效抑制同步时钟偏差的影响.     

Photo-degradation of the indium tin oxide (ITO)/organic interface in organic optoelectronic devices and a new outlook on the role of ITO surface treatments and interfacial layers in improving device stability

This work focuses on the effect of light exposure on ITO/organic interface in organic optoelectronic devices, including organic light emitting devices (OLEDs), organic photo-detectors (OPDs) and organic solar cells (OSCs). The results show that irradiation by light in the visible and UV range leads to a gradual deterioration in charge injection and extraction across the interface. A correlation between the performance stability of the devices and the photo-stability of the ITO/organic contacts is established. Studies also show that this photo-induced degradation can be significantly reduced by means of ITO surface treatment or through the insertion of interfacial layers between ITO and the organic layers. X-ray Photoelectron Spectroscopy (XPS) measurements reveal detectable changes in the interface characteristics after irradiation, indicating that the photo-degradation of the ITO/organic contacts is chemical in nature. Changes in XPS characteristics after irradiation suggest a possible reduction in bonds between ITO and its adjacent organic layer. The results shed light on a new material degradation mechanism that appears to have a wide presence in ITO/organic contacts in general, and which may play a key role in limiting the stability of various organic optoelectronic devices such as OLEDs, OSCs and OPDs.