共查询到20条相似文献，搜索用时 15 毫秒
1.
This paper presents a highly efficient ternary flash ADC, designed using the innovative gate-overlap tunnel FET (GOTFET) at the 45 nm technology node. The proposed GOTFETs have on-state currents Ion more than double, while the off-state currents Ioff remaining at least an order of magnitude lower than the corresponding values of the standard 45 nm CMOS technology with the same width. Replacing MOSFETs with the proposed GOTFETs significantly reduces the static power consumption and improves performance. However, the higher Ion increases the dynamic power as well. To minimize the dynamic power, we propose a novel complementary GOTFET (CGOT) based comparator design. In addition to the inherent advantages of the GOTFET technology, the proposed design further reduces the dynamic power, such that the final power delay product (PDP) is merely 6.3% of the PDP in conventional CMOS comparator design. In addition to the novelty related to the innovative GOTFET devices, there are at least two-fold circuit-level novelty reported in this work. Firstly, we propose a novel CGOT based comparator circuit design, which, in addition to the advantages of GOTFET, further reduces the dynamic power such that the PDP is less than 1/3rd of the original PDP of the conventional comparator designed with GOTFETs. Secondly, the proposed CGOT based ADC requires only 48 transistors to encode the comparator outputs into the 2-bit ternary output, which is 30% lower than the 70 transistors necessary for the 2-bit CMOS based ternary flash ADC designs reported earlier in the literature. We propose an efficient 2-bit ternary flash ADC with a resolution of 50 mV and input quantized to 9 levels. Subsequently, we benchmark the performance of the proposed CGOT ternary flash ADC with the same ADC circuit implemented using the standard 45 nm CMOS technology library, all corresponding devices having the same width. We demonstrate that in addition to the superior performance than the corresponding CMOS ADC, the proposed CGOT ADC design consumes significantly lower power. The overall PDP of the proposed CGOT ADC is merely 6.3% of the PDP in corresponding CMOS design. 相似文献
2.
In this article, a new complementary metal oxide semiconductor design scheme called dynamic self-controllable voltage level (DSVL) is proposed. In the proposed scheme, leakage power is controlled by dynamically disconnecting supply to inactive blocks and adjusting body bias to further limit leakage and to maintain performance. Leakage power measurements at 1.8?V, 75°C demonstrate power reduction by 59.4% in case of 1?bit full adder and by 43.0% in case of a chain of four inverters using SVL circuit as a power switch. Furthermore, we achieve leakage power reduction by 94.7% in case of 1?bit full adder and by 91.8% in case of a chain of four inverters using dynamic body bias. The forward body bias of 0.45?V applied in active mode improves the maximum operating frequency by 16% in case of 1?bit full adder and 5.55% in case of a chain of inverters. Analysis shows that additional benefits of using the DSVL and body bias include high performance, low leakage power consumption in sleep mode, single threshold implementation and state retention even in standby mode. 相似文献
3.
This paper proposes a hardware-efficient low-power 2-bit ternary arithmetic logic unit (TALU) design in carbon nano tube field effect transistor technology. The proposed TALU architecture combines adder-subtractor and Ex-OR cell in one cell, thereby reducing the number of transistors by 71% in comparison with other TALU architecture. Further, the proposed TALU is optimised at transistor level with a new pass-transistor logic-based encoder circuit. Hspice simulation results show that the proposed design attains great advantages in power and power-delay product for addition and multiplication operations than reported designs. For instant, at power supply of 0.9 V, the proposed TALU consumes on average 91% and 95% less energy compared to their existing counterparts, for addition and multiplication operations, respectively. 相似文献
4.
提出了一种电荷自补偿技术来降低多米诺电路的功耗,并提高了电路的性能.采用电荷自补偿技术设计了具有不同下拉网络(PDN)和上拉网络(PUN)的多米诺电路,并分别基于65,45和32nm BSIM4 SPICE模型进行了HSPICE仿真.仿真结果表明,电荷自补偿技术在降低电路功耗的同时,提高了电路的性能.与常规多米诺电路技术相比,采用电路自补偿技术的电路的功耗延迟积(PDP)的改进率可达42.37%.此外,以45nm Zipper CMOS全加器为例重点介绍了功耗分布法,从而优化了自补偿路径,达到了功耗最小化的目的.最后,系统分析了补偿通路中晶体管宽长比,电路输入矢量等多方面因素对补偿通路的影响. 相似文献
5.
Vijay Kumar Sharma Manisha Pattanaik Balwinder Raj 《International Journal of Electronics》2013,100(2):200-215
Complementary metal oxide semiconductor (CMOS) technology scaling for improving speed and functionality turns leakage power one of the major concerns for nanoscale circuits design. The minimization of leakage power is a rising challenge for the design of the existing and future nanoscale CMOS circuits. This paper presents a novel, input-dependent, transistor-level, low leakage and reliable INput DEPendent (INDEP) approach for nanoscale CMOS circuits. INDEP approach is based on Boolean logic calculations for the input signals of the extra inserted transistors within the logic circuit. The gate terminals of extra inserted transistors depend on the primary input combinations of the logic circuits. The appropriate selection of input gate voltages of INDEP transistors are reducing the leakage current efficiently along with rail to rail output voltage swing. The important characteristic of INDEP approach is that it works well in both active as well as standby modes of the circuits. This approach overcomes the limitations created by the prevalent current leakage reduction techniques. The simulation results indicate that INDEP approach mitigates 41.6% and 35% leakage power for 1-bit full adder and ISCAS-85 c17 benchmark circuit, respectively, at 32 nm bulk CMOS technology node. 相似文献
6.
Ultra-Low-Power circuits demand has dramatically increased in the last few years. One of the main challenges in designing these circuits is that transistors often run in the sub-threshold regime and their on current is exponentially dependent on the gate-to-source voltage, thus making sub-threshold gates extremely susceptible to power and ground noise phenomena. This paper provides a complete mathematical model in closed form for the delay of sub-threshold CMOS inverters. The novel model can predict the behavior of inverters output signal and therefore it can be extremely useful in the design phase to analyze the variations caused by noise on the output over/undershoot and the gate delay. The proposed model has a general validity since it considers the ground and supply noises completely uncorrelated both in frequency and in amplitude. When a commercial CMOS 45 nm process technology is referenced, the proposed model exhibits a maximum error of only ~16% under different conditions in terms of output load capacitance, input signal rising/falling time, noise phase and frequency. 相似文献
7.
This paper concerns a novel analog front-end of a wireless brain oxymeter smart sensoring instrument based on near-infrared spectroreflectometry (NIRS). The NIRS sensor makes use of dynamic threshold transistors (DTMOS) for low voltage (1 V), low power and low noise enhancement. The design is composed of a transimpedance amplifier (TIA) and an operational transconductance amplifier (OTA). The OTA differential input pairs use DTMOS devices for input common mode range enhancement. The OTA was fabricated in a standard 0.18 μm CMOS process technology. Measurements under a 5 pF capacitive load for the OTA gave a DC open loop gain of 67 dB, unity frequency gain bandwidth of 400 kHz, input and output swings of 0.58 and 0.7 V, a power consumption of 18 μW, and an input referred noise of 134 nV/√Hz at 1 kHz without any extra noise reduction techniques. The achieved features of the proposed oxymeter front-end will allow ultra low-light level measurements, high resolution and good temperature stability. 相似文献
8.
在CDMA系统中,为了对抗多径衰落,使用Rake接收机对接收信号进行处理。在发射端,通过扰码对信号进行加扰处理。Rake接收机对接收的信号进行解扰,相干积分处理,根据功率时堑函数PDP值来计算多径的相位信息。在信噪比比较差的情况下,搜索出来的多径可能是噪声径,这对Rake接收机解调的性能有一定的影响。介绍一种根据扰码自相关特性,来判断搜索出多径是否为噪声径的方法,提高Rake接收机的性能。 相似文献
9.
A CMOS voltage reference, based on body bias technique, has been proposed and simulated using SMIC 0.18 μm CMOS technology in this paper. The proposed circuit can achieve a temperature coefficient of 19.4 ppm/°C in a temperature range from −20 °C to 80 °C, and a line sensitivity of 0.024 mV/V in a supply voltage range from 0.85 V to 2.5 V, without the use of resistors and any other special devices such as thick gate oxides MOSFETs with higher threshold voltage. The supply current at the maximum supply voltage and at 27 °C is 214 nA. The power supply rejection ratio without any filtering capacitor at 10 Hz and 10 kHz are −88.2 dB and −36 dB, respectively. 相似文献
10.
本文介绍了用于ＰＤＰｓ封接的低溶玻璃材料的选择方法和ＰＤＰｓ的封接工艺。我们按照此工艺封接出的ＰＤＰｓ的质量令人满意。 相似文献
11.
提出了一种单端自适应偏置电路,该电路能够根据输入信号功率,动态地调整输出直流电压,以提升射频功率放大器(PA)的线性度及功率回退区域的效率。为验证该电路的功能,设计了一种2.4 GHz PA,该电路基于单端三级结构设计,采用0.18 μm CMOS工艺制造,电路输入及输出阻抗匹配网络均集成于片内。测试结果表明,PA的增益为26.8 dB,S11和S22均小于-10 dB,OP1 dB为23.5 dBm,功率回退6 dB点PAE和峰值PAE分别为14%和24%。该PA对WLAN、ZigBee等2.4 GHz设备具有一定的应用价值。 相似文献
12.
13.
《Microelectronics Journal》2014,45(11):1463-1469
A low-power low-noise amplifier (LNA) utilized a resistive inverter configuration feedback amplifier to achieve the broadband input matching purposes. To achieve low power consumption and high gain, the proposed LNA utilizes a current-reused technique and a splitting-load inductive peaking technique of a resistive-feedback inverter for input matching. Two wideband LNAs are implemented by TSMC 0.18 μm CMOS technology. The first LNA operates at 2–6 GHz. The minimum noise figure is 3.6 dB. The amplifier provides a maximum gain (S21) of 18.5 dB while drawing 10.3 mW from a 1.5-V supply. This chip area is 1.028×0.921 mm2. The second LNA operates at 3.1–10.6 GHz. By using self-forward body bias, it can reduce supply voltage as well as save bias current. The minimum noise figure is 4.8 dB. The amplifier provides a maximum gain (S21) of 17.8 dB while drawing 9.67 mW from a 1.2-V supply. This chip area is 1.274×0.771 mm2. 相似文献
14.
本文分析并解决了应用于TDI CMOS 图像传感器的模拟累加器的寄生问题。为了抑制寄生问题所引入累加器信噪比的降低,在已有的具有去耦开关的模拟累加器中,采用上级板采样,在积分阶段注入补偿电荷,来补偿无法消除的寄生所带来的影响。并且通过加入校正电路来抑制工艺偏差和器件失配带来的影响。在设计中采用0.18-μm 1P4M工艺,供电电压为3.3V。后仿真结果表明,累加器所能提升的信噪比从17.835dB增加到了21.067dB。此外,累加器的整体线性度达到了99.62%。同时通过对电路进行蒙特卡洛仿真,结果表明校正电路很好的抑制了工艺偏差和器件失配带来的影响。所以,本文提出的结构可用于构建高级数的模拟累加器。 相似文献
15.
提出一种数字控制可编程延时单元(Digitally Controlled Programmed Delay Element,DCPDE)结构,对数字控制字可编程延时单元(DCPDE)进行了理论分析和设计方法研究。采用二进制编码控制的电流镜为延时单元提供充、放电电流,实现了信号的上升、下降沿等量延时,本单元可嵌入全数字控制的延时锁定环设计中,能够实现50%占空比420ps～920ps的双沿延时。 相似文献
16.
This paper describes a 1.5-V low dropout regulator (LDO)-free ultra-low-power 2.4-GHz CMOS receiver for direct-powering through a coin battery. By effective merging the quadrature low noise amplifier (LNA), in phase and quadrature (I/Q) mixers, a voltage controlled oscillator (VCO) and a trans-impedance amplifier (TIA) in one cell, while removing the LDO, we fully utilize the available 1.5-V voltage supply for current-reuse between blocks, minimizing the dc current consumption. Specifically, a quadrature LNA operating as both common-source and common-drain provides the I/Q outputs in the signal path. Forward-body-bias applied to the transconductance stage of the I/Q mixers relaxes their voltage headroom consumption. Prototyped in 180-nm CMOS, the receiver exhibits a conversion gain (CG) of 23 dB, a noise figure (NF) of 13.8 dB and an input-referred 3rd-order intercept point (IIP3) of −14 dBm while consuming only 2 mA. The phase noise of the VCO is −118.5 dBc/Hz at 2.5 MHz offset. The low-cost technology and low current consumption renders the receiver suitable for Internet of Things (IoT) devices using the Bluetooth Low Energy (BLE) or ZigBee standards. 相似文献
17.
介绍了一种用于环境温度监测的新型高精度宽电压范围的CMOS温度传感器,采用0.13μm标准CMOS工艺的厚氧器件实现,芯片面积为37μm×41μm。该温度传感器在-20～60°C的温度范围内,采用两点校正方法之后,温度误差为-0.2°C/0.5°C。该温度传感器可以在1.8～3.6V的电源电压范围内安全可靠地工作,并且具有较高的电源抑制比。测试结果表明,其输出电压斜率为3.9mV/°C,1.8V下功耗为1.3μW。 相似文献
18.
《Optical Fiber Technology》2014,20(4):414-421
In this study, our main goal is to investigate the performance optimization conditions for WDM networks. We introduce a network architecture of passive star topology that uses a Multi-channel Control Architecture (MCA) to avoid both the data channels and the receiver collisions. Especially, we propose a synchronous access scheme that exploits the propagation delay parameter in order to assign the data channels to the stations for successful data packet transmission. Thus, we achieve effective bandwidth utilization. An approximate analysis based on Poisson statistics is developed in order to explore the performance measures optimization. Finally, extensive comparative study is given for various stations populations and number of MCA channels. 相似文献
19.
Yo-Sheng Lin Chun-Hao Hu Chi-Ho Chang Ping-Chang Tsao 《International Journal of Electronics》2018,105(6):993-1010
In this work, we demonstrate novel one-dimensional (1D) and two-dimensional (2D) antenna arrays for both microwave wireless power transfer (MWPT) systems and dual-antenna transceivers. The antenna array can be used as the MWPT receiving antenna of an integrated MWPT and Bluetooth (BLE) communication module (MWPT-BLE module) for smart CNC (computer numerical control) spindle incorporated with the cloud computing system SkyMars. The 2D antenna array has n rows of 1 × m 1D array, and each array is composed of multiple (m) differential feeding antenna elements. Each differential feeding antenna element is a differential feeding structure with a microstrip antenna stripe. The stripe length is shorter than one wavelength to minimise the antenna area and to prevent being excited to a high-order mode. That is, the differential feeding antenna element can suppress the even mode. The mutual coupling between the antenna elements can be suppressed, and the isolation between the receiver and the transmitter can be enhanced. An inclination angle of the main beam aligns with the broadside, and the main beam is further concentrated and shrunk at the elevation direction. Moreover, if more differential feeding antenna elements are used, antenna gain and isolation can be further enhanced. The excellent performance of the proposed antenna arrays indicates that they are suitable for both MWPT systems and dual-antenna transceivers. 相似文献
20.
本文概述了近年来该器件的研究与进展,从发光机理、器件研制和应用前景等方面做了详细的叙述。 相似文献