SystemQ: Bridging the gap between queuing-based performance evaluation and SystemC

During early design phases performance evaluation becomes increasingly important since major system-level decisions, such as the allocation of hardware resources and the partitioning of functionality onto architecture building blocks, affect the quality of the design significantly. Quantitative analysis is hard to achieve due to growing complexities, heterogeneity, and concurrency of modern embedded systems. We propose the use of multiclass queuing networks during the specification phase of the design flow for modeling data-flow oriented systems. Starting from an executable high-level queuing model our evaluation framework SystemQ¹ enables successive and systematic refinement of behavior and structure towards established TLM and RTL models based on SystemC. We demonstrate why SystemQ’s multiclass queuing networks are a natural and feasible abstraction for evaluating network processing platforms. In particular we reveal the impact of scheduling policies on the Quality-of-Service, such as the residence time of network traffic in the system. In our case study, we show how stepwise refinement can reduce memory and latency bounds by up to two orders of magnitude and how the choice of only one queuing discipline can affect these properties. The investigated simulation models run in the range of 1 : 100 to 1 : 1 of real-time on a common off-the-shelf Linux PC.     

IPOA组包功能的验证系统

介绍一种对IPOA应用中的组包功能进行RTL功能验证的系统。该验证系统可根据用户输入数据自动产生ATM信元作为激励 ,并对被测系统的输出进行自动验证。通过该验证系统大大提高了验证效率 ,缩短了仿真时间。同时 ,该系统产生的激励可对被测系统进行彻底的功能验证 ,提高了验证过程中代码覆盖率     

大型相控阵雷达可靠性评估方法

大型相控阵雷达整机外场可靠性试验可分为联调联试和验证试验两个阶段。针对现有的整机可靠性评估仅利用验证试验阶段较少的试验数据,导致整机可靠性评估结果置信度低的问题,提出一种基于改进序化关系模型的整机可靠性评估方法。该方法通过构建新的联合似然函数对传统序化关系模型进行改进,并融合联调联试数据和验证试验数据来评估整机的可靠性水平。实例表明:该方法能提高整机平均故障间隔时间在同一置信水平下的估计下限,缩短平均故障间隔时间的估计区间。     

基于虚拟机的兼容微处理器功能验证平台

本文根据验证兼容指令集微处理器的要求，提出了利用虚拟机快速建立微处理器功能验证平台，使用已有的操作系统和应用程序作测试程序验证兼容微处理器的方法，并给出了在验证兼容Intel486指令集微处理器AMEX86中的具体应用。     

面向SoC系统芯片中跨时钟域设计的模型检验方法

 传统方法无法在RTL验证阶段全面验证SoC系统芯片中的跨时钟域设计.为解决此问题,本文首先提出描述亚稳态现象的等价电路实现,用以在RTL验证中准确体现亚稳态现象的实际影响;然后使用线性时序逻辑对跨时钟域设计进行设计规范的描述;为缓解模型检验的空间爆炸问题,进一步针对跨时钟域设计的特点提出基于输入信号的迁移关系分组策略和基于数学归纳的优化策略.实验结果表明本文提出的方法不仅可以在RTL验证阶段有效地发现跨时钟域设计的功能错误,而且可以使验证时间随实验用例中寄存器数量的递增趋势从近似指数级增长减小到近似多项式级增长.     

A methodology aimed at better integration of functional verification and RTL design

The advent of new 65 nm/90 nm VLSI technology and SoC design methodologies has brought an explosive growth in the complexity of modern electronic circuits. As a result, functional verification has become the major bottleneck in any digital design flow. Thus, new methods for easier, faster and more reusable verification are required. This paper proposes a verification methodology (VeriSC2) that guides the implementation of working testbenches during hierarchical decomposition and refinement of the design, even before the RTL implementation starts. This approach uses the SystemC Verification Library (SCV), in a tool capable of automatically generating testbench templates. A case study from a MPEG-4 decoder design is used to show the effectiveness of this approach.     

Behavioral test generation modeling approach for mixed-signal IC verification

An application of behavioral modeling for mixed-signal test generation and applied results are presented. It is shown that test debugging can be provided in the verification test system before silicon by utilizing simulated behavioral mixed-signal models. Due to the behavioral modeling technique, the computational performance was enhanced to a level allowing efficient test development and debugging. Influence on efficiency in design methods is reported.     

FAST: An RTL Fault Simulation Framework based on RTL-to-TLM Abstraction

Functional verification techniques based on fault injection and simulation at register-transfer level (RTL) have been largely investigated in the past years. Although they have various advantages such as scalability and simplicity, they commonly suffer from the low speed of the cycle-accurate RTL simulation. On the other hand, Transaction-level modeling (TLM) allows a simulation speed sensibly faster than RTL. This article presents FAST, a framework to accelerate RTL fault simulation through automatic RTL-to-TLM abstraction. FAST abstracts RTL models injected with any RTL fault model into equivalent injected TLM models thus allowing a very fast fault simulation at TLM level. The article also presents FAST-DT, a new bit-accurate data type library integrated in the framework that allows a further improvement of the simulation speed-up. Finally, the article shows how the generated TLM test patterns can be automatically synthesized into RTL test patterns by exploiting the structural information of the RTL model extracted during the abstraction process. Experimental results have been performed on several designs of different size and complexity to show the methodology effectiveness.     

基于FPGA的软硬件协同仿真加速技术

在系统设计中,硬件复杂电路设计的调试与仿真工作对于设计者来说十分困难。为了降低仿真复杂度,加快仿真速度,本文提出利用FPGA加速的思想,实现软硬件协同加速仿真。经过实验,相对于纯软件仿真,利用软硬件协同加速仿真技术,仿真速度提高近30倍,大大缩短了仿真时间。     

系统级芯片设计语言和验证语言的发展

由于微电子技术的迅速发展和系统芯片的出现,包含微处理器和存储器甚至模拟电路和射频电路在内的系统芯片的规模日益庞大,复杂度日益增加。人们用传统的模拟方法难以完成设计验证工作,出现了所谓“验证危机”。为了适应这种形势,电子设计和验证工具正在发生迅速而深刻的变革。现在基于RTL级的设计和验证方法必须向系统级的设计和验证方法过渡,导致了验证语言的出现和标准化,本文将对当前出现的系统级设计和验证语言进行全面综述,并论述验证语言标准化的情况。分析他们的优缺点和发展趋势。最后简单评述当前的验证方法,说明基于断言的验证是结合形式化验证和传统模拟验证可行的途径。     

A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors

Architectural verification is a critical aspect of the microprocessor design cycle. In this paper, we present a design verification environment centered around a biased random instruction generator for simulation-based architectural verification of pipelined microprocessors. The instruction generator uses biases specified by the user to generate instruction sequences for simulation. These biases are not hard-coded and can thus be changed depending on the specific areas in the design and type of design errors being targeted. Correctness checking is achieved using assertion checking and end-of-state comparison with a high-level architectural model. Several architectural-level errors are introduced into a behavioral model of the DLX processor to investigate the processor's response in the presence of design errors. Simulation experiments conducted using the behavioral model show that biased random instruction sequences provide higher coverage of RTL conditional branches and design errors than random instruction sequences or manually-generated test programs. Furthermore, instruction sequences containing a high percentage of read-after-write (RAW) and control dependencies are the most useful.