Investigation on NBTI-induced dynamic variability in nanoscale CMOS devices: Modeling,experimental evidence,and impact on circuits

With the downscaling of CMOS devices, dynamic variability induced by negative bias temperature instability (NBTI) has become a critical issue. In addition to the time-dependent device-to-device variation (DDV) of NBTI degradation, the cycle-to-cycle variation (CCV) originated from random trap occupation is found non-negligible and should be added into the total dynamic variation. This paper summarizes our recent studies on NBTI-induced dynamic variability, focusing on the CCV effect, with more details on the statistical modeling, circuit reliability simulation methodologies and experimental results. By adding the random trap occupation into consideration, a statistical model for total dynamic variation (DDV + CCV) is proposed. The effective occupancy probability p_eff is introduced as a key parameter for modeling and circuit reliability simulation. With the statistical trap response (STR) method and modified on-the-fly method, the proposed model is validated by the experimental evidence under both DC and AC NBTI. According to the model and experimental results, circuit reliability simulation framework is proposed for both long-term quasi-static and short-term transient performance evaluation with the additional impact of CCV. Two representative digital circuit units, ring oscillator (RO) and SRAM cell, are simulated under different conditions, indicating it necessary to consider the evident influence of the CCV in accurate circuit reliability evaluation. The results are helpful for the reliability/variability-aware circuit design in nanoscale technology.     

Timing-driven logic restructuring for nano-hybrid circuits

As the feature size of the integrated circuits (ICs) scales down, the future of nano-hybrid circuit looks bright in extending Moore's Law. However, mapping a circuit to a nano-fabric structure is vexing due to connectivity constraints. A mainstream methodology is that a circuit is transformed into a nano-fabric preferred structure by buffer insertion to high fan-out gates. However, it may result in timing degradation. Logic replication is a traditional way to split high fan-out gates in logic synthesis but may not be suitable for high fan-out gates with high fan-ins. In this article, a timing-driven logic restructuring framework at the gate level is proposed. The proposed framework identifies the high fan-out gates from a given gate netlist according to the fan-out threshold, following by the restructuring of high fan-out gates through the application of logic replication and buffer insertion. To improve circuit timing from a global perspective, latent critical edges are identified to avoid entrapping critical paths during the restructuring. Experimental results on ISCAS benchmarks indicate that 8.51% timing improvement and 6.13% CPU time reduction can be obtained traded with 4.16% area increase on an average.     

MOSFET output characteristics after oxide breakdown

The performance of nMOSFETs after the gate oxide (SiO₂) dielectric breakdown (BD) has been studied. Different BD hardness, BD path locations along the channel and device aspect ratios have been considered. The results show that the BD of the gate oxide affects the overall I_D-V_DS characteristics and that the BD impact depends on BD hardness and location and device geometry. To describe the post-BD data, a simple BD MOSFET model has been used, which accounts for the after BD additional gate current and drain current effects. The model is able to fit all the observed post-BD behaviours and can be easily included in a circuit simulator, to evaluate the impact of device BD on the post-BD performance of circuits.     

Ultra-thin dielectric breakdown in devices and circuits: A brief review

Time-dependent dielectric breakdown (TDDB), in which the traps in oxide bulk form a conducting path under application of stress voltage for long period of time, has emerged as one of the important sources of performance degradation in advanced devices. In this paper, we give an overview of the recent progress in the understanding of ultra-thin dielectric breakdown in devices and consider its impact at the circuit-level. From the device point of view, the breakdown (BD) phenomenon, including the BD statistics, trap generation models, and BD evolution in ultra-thin dielectric are presented followed by the recent studies on TDDB in high-k metal gate (HKMG) devices and magnetic tunnel junction (MTJ) memories. On the circuit side, we explore methodologies for circuit lifetime assessment, the impact of TDDB on circuit performance degradation, and design techniques to improve circuit reliability.     

Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates

Soft errors caused by particles strike in combinational parts of digital circuits are a major concern in the design of reliable circuits. Several techniques have been presented to protect combinational logic and reduce the overall circuit Soft Error Rate (SER). Such techniques, however, typically come at the cost of significant area and performance overheads. This paper presents a low area and zero-delay overhead method to protect digital circuits’ combinational parts against particles strike. This method is made up of a combination of two sub-methods: (1) a SER estimation method based on signal probability, called Estimation by Characterizing Input Patterns (ECIP) and (2) a protection method based on gate sizing, called Weighted and Timing Aware Gate Sizing (WTAGS). Unlike the previous techniques that either overlook internal nodes signal probability or exploit fault injection, ECIP computes the sensitivity of each gate by analytical calculations of both the probability of transient pulse generation and the probability of transient pulse propagation; these calculations are based on signal probability of the whole circuit nodes which make ECIP much more accurate as well as practical for large circuits. Using the results of ECIP, WTAGS characterizes the most sensitive gates to efficiently allocate the redundancy budget. The simulation results show the SER reduction of about 40% by applying the proposed method to ISCAS’89 benchmark circuits while imposing no delay overhead and 5% area overhead.     

Chip-Package Interaction in 3D stacked IC packages using Finite Element Modelling

Chip Package Interaction (CPI) gained a lot of importance in the last years. The reason is twofold. First, advanced node IC technologies requires dielectrics in the BEOL (back-end-of-line) with a decreasing value for the dielectric constant k. These so-called (ultra) low-k materials have a reduced stiffness and reduced adhesion strength to the barrier materials, making the BEOL much more vulnerable to externally applied mechanical stress due to packaging. Secondly, advanced packaging technologies such as 3D stacked IC’s use thinned dies (down to 25 μm) which can cause much higher stresses at transistor level, resulting in electron mobility shifts of the transistors. Also the copper TSV (through-silicon-via) generates local stress which affects the device performance. This paper considers both the packaging impact on BEOL integrity and transistor mobility shifts for 3D stacked IC (integrated circuit) technologies.     

基于失效物理的集成电路故障定位方法

超大规模集成电路后道工艺(BEOL)中的失效日益增多,例如多层金属化布线桥连、划伤,栅氧化层的静电放电(ESD)损伤、裂纹等失效模式,由于失效点本身尺寸小加上电路规模大,使得失效分析难度增加。为了能够对故障点进行快速、精确定位,提出了基于失效物理的集成电路故障定位方法。根据CMOS反相器电路的失效模式提出了4种主要故障模型:栅极电平连接至电源(地)、栅极连接的金属化高阻或者开路、氧化层漏电和pn结漏电。结合故障模型产生的光发射显微镜(PEM)和光致电阻变化(OBIRCH)现象的特征形貌和位置特点,进行合理的失效物理假设。结果表明,基于该方法可对通孔缺陷、多层金属化布线损伤以及栅氧化层静电放电损伤失效进行有效的定位,快速缩小失效范围,提高失效分析的成功率。     

A new approach to power estimation and reduction in CMOS digital circuits

Modelling and optimization of dynamic capacitive power consumption in digital static CMOS circuits, taking into consideration a reason of a gate switching—gate control mode, is discussed in the present paper. The term ‘gate control mode’ means that a number and type of signals applied to input terminals of the gate have an influence on total amount of energy dissipated during a single switching cycle. Moreover, changes of input signals, which keep the gate output in a steady state, can also cause power consumption. Based on this observation, complex reasons of power losses have been considered. In consequence, the authors propose a new model of dynamic power consumption in static CMOS gates. Appropriate parameters’ calculation method for the new model was developed. The gate power model has been extended to logic networks, and consequently a new measure of the circuit activity was proposed. Switching activity, which is commonly used as a traditional measure, characterizes only the number of signal changes at the circuit node, and it is not sufficient for the proposed model. As the power consumption parameters of CMOS are dependent on their control mode, the authors used probability of the node control mode as a new measure of the circuit activity. Based on the proposed model, a procedure of combinational circuit optimization for power dissipation reduction has been developed. The procedure can be included in a design flow, after technology mapping. Results of the power estimation received for some benchmark circuits are much closer to SPICE simulations than values obtained for other methods. So the model proposed in this study improves the estimation accuracy. Additionally, we can save several percent of the consumed energy.     

Accurate negative bias temperature instability lifetime prediction based on hole injection

Negative bias temperature instability (NBTI) lifetime prediction of thin gate insulator films based on hole injection without gate voltage acceleration is described and lifetime comparison between SiO₂ film and SiON film is made based on the prediction method. The acceleration parameters are most important for the accurate lifetime prediction. The proposed acceleration parameter is not the applied voltage to the gate insulator film and the temperature but quantity of the hole injection to the gate insulator film that directly relates with the quantity of holes in the inversion layer. The degradation mechanism under the excessive voltage and excessive temperature stresses are different from that in the operation conditions. Using the hole injection method, the NBTI lifetime of SiON is less than that of SiO₂. This result agrees with the reported results measured by conventional high gate fields and temperatures. By the introduction of effective stress time (=Q_hole/J_inj0), accurate lifetime prediction in terms of the V_th shift is realized, and by analyzing of relationship between I_D reduction and V_th shift, accurate lifetime prediction in terms of the I_D reduction and the degradation prediction in the circuit level are realized. These results are essential for the accurate NBTI lifetime prediction for further more integrated LSI such as very thin gate insulator films around 1 nm.     

Improved single-pass approach for reliability analysis of digital combinational circuits

Designing a highly reliable digital circuit requires tools and techniques for accurately evaluation of its reliability. In this paper, we present an improved single-pass approach for reliability analysis of digital combinational circuits. The main problem of the basic single-pass method is handling reconvergent fan-outs. The proposed method improves the accuracy of the basic single-pass method in two ways. An efficient method is proposed to compute the joint probability between multiple nodes of the circuit which leads to more accurate calculation of correlation coefficients. The second enhancement consists of two methods called case based and mathematical based and concentrates on accurate calculation of conditional joint correlations which makes the algorithm much more dependable than the basic single-pass method. The case based method checks different conditions of the nodes for calculation of conditional joint correlations, while the mathematical based method uses a heuristic expression. The proposed method is applied to a subset of combinational benchmark circuits and our experiments demonstrate that the proposed method eliminates the weaknesses of the basic single-pass method efficiently.     

The impact of intra-die device parameter variations on path delaysand on the design for yield of low voltage digital circuits

The yield of low voltage digital circuits is found to he sensitive to local gate delay variations due to uncorrelated intra-die parameter deviations. Caused by statistical deviations of the doping concentration they lead to more pronounced delay variations for minimum transistor sizes. Their influence on path delays in digital circuits is verified using a carry select adder test circuit fabricated in 0.5 and 0.35 μm complementary metal-oxide-semiconductor (CMOS) technologies with two different threshold voltages. The increase of the path delay variations for smaller device dimensions and reduced supply voltages as well as the dependence on the path length is shown. It is found that circuits with a large number of critical paths and with a low logic depth are most sensitive to uncorrelated gate delay variations. Scenarios for future technologies show the increased impact of uncorrelated delay variations on digital design. A reduction of the maximal clock frequency of 10% is found for, for example, highly pipelined systems realized in a 0.18-μm CMOS technology     

Vertically integrated SOI circuits for low-power and high-performance applications

Vertical integration offers numerous advantages over conventional structures. By stacking multiple-material layers to form double gate transistors and by stacking multiple device layers to form multidevice-layer integration, vertical integration can emerge as the technology of choice for low-power and high-performance integration. In this paper, we demonstrate that the vertical integration can achieve better circuit performance and power dissipation due to improved device characteristics and reduced interconnect complexity and delay. The structures of vertically integrated double gate (DG) silicon-on-insulator (SOI) devices and circuits, and corresponding multidevice-layer (3-D) SOI circuits are presented; a general double-gate SOI model is provided for the study of symmetric and asymmetric SOI CMOS circuits; circuit speed, power dissipation of double-gate dynamic threshold (DGDT) SOI circuits are investigated and compared to single gate (SG) SOI circuits; potential 3-D SOI circuits are laid out. Chip area, layout complexity, process cost, and impact on circuit performance are studied. Results show that DGDT SOI CMOS circuits provide the best power-delay product, which makes them very attractive for low-voltage low-power applications. Multidevice-layer integration achieves performance improvement by shortening the interconnects. Results indicate that up to 40% of interconnect performance improvements can be expected for a 4-device-layer integration.     

Integrated modeling of Self-heating of confined geometry (FinFET,NWFET, and NSHFET) transistors and its implications for the reliability of sub-20 nm modern integrated circuits

The evolution of transistor topology from planar to confined geometry transistors (i.e., FinFET, Nanowire FET, Nanosheet FET) has met the desired performance specification of sub-20 nm integrated circuits (ICs), but only at the expense of increased power density and thermal resistance. Thus, self-heating effect (SHE) has become a critical issue for performance/reliability of ICs. Indeed, temperature is one of the most important factors determining ICs reliability, such as Negative Bias Temperature Instability (NBTI), Hot Carrier Injection (HCI), and Electromigration (EM). Therefore, an accurate SHE model is essential for predictive, reliability-aware ICs design. Although SHE is collectively determined by the thermal resistances/capacitances associated with various layers of an IC, most researchers focus on isolated components within the hierarchy (i.e., a single transistor, few specific circuit configurations, or specialized package type). This fragmented approach makes it difficult to verify the implications of SHE on performance and reliability of ICs based on confined geometry transistors. In this paper, we combine theoretical modeling and systematic transistor characterization to extract thermal parameters at the transistor level to demonstrate the importance of multi-time constant thermal circuits to predict the spatio-temporal SHE in modern sub-20 nm transistors. Based on the refined Berkeley Short-channel IGFET Model Common Multi-Gate (BSIM-CMG) model, we examine SHE in typical digital circuits (e.g., ring oscillator) and analog circuits (e.g., two-stage operational amplifier) by Verilog-A based HSPICE simulation. Similarly, we develop a physics-based thermal compact model for packaged ICs using an effective media approximation for the Back End Of Line (BEOL) interconnects and ICs packaging. We integrate these components to investigate SHE behavior implication on ICs reliability and explain why one must adopt various (biomimetic) strategies to improve the lifetime of self-heated ICs.     

Epitaxial spinel growth for integrated circuits

This is a report on our investigation of the epitaxial growth of Si-on-spinel-on-Si double-heterostructure integrated circuit material. The spinel epitaxial layers were grown on the Si substrate with an open-tube Al-HCl-MgCl₂-CO₂H₂ VPE system. High electron Hall-mobility and low defect density in the active Si layers were achieved with optimum growth conditions for spinel and silicon. Bipolar transistors, MOS devices and high-voltage bipolar ICs were fabricated in the active Si layers on epitaxially grown spinel.     

Gate controlled 2-DEG varactor for VCO applications in microwave circuits

A novel gate controlled Schottky diode varactor is introduced. The three-terminal varactor is a modulation-doped heterostructure of AlGaAs/GaAs with two Schottky contacts, similar to a metal–semiconductor–metal (MSM) diode. Schottky metal contacts are made to a two-dimensional electron gas (2-DEG). The third contact, the gate contact is formed from highly doped n⁺ GaAs material to allow an open optical window that can be used for optical gating and mixing. Structure capacitance is less than 1 PF and a change of more than 30% from the zero bias capacitance is observed with the applied gate voltage. On the basis of our quasi two-dimensional C–V model, the layer structure and device dimensions can be optimized and scaled to cover a wide range of operations in the microwave and millimeter wave regimes.     

45 nm/32 nm CMOS – Challenge and perspective

Production of 45 nm node CMOS has already started. However, difficulty of new technology development is increasing and some company dropped off from the competition. The big challenge for 45 nm node is the introduction of ArF immersion lithography. Most of the other technologies used for 45 nm node are the extension of those used for 65 nm node. On the other hand, there will be a big jump for 32 nm node technology. The biggest item is metal gate and high-k gate insulator system. Self barrier layer formation for BEOL is also the promising item. Variability is the biggest concern for 32 nm node SRAM. To overcome these difficulties, collaboration between device and circuit engineer is important.     

A robust and fast procedure for the determination of the small signal equivalent circuit of HEMTs

In this paper we present an analytical, fast, accurate and robust technique for the determination of the circuit model elements of HEMTs in the microwave range. By this method the values of the equivalent circuit parameters of the device under test are extracted using three measured scattering (S) parameter sets without any optimization. We also investigated the influence of the reverse transfer conductance Re(Y₁₂) on the modelling by means of a gate drain resistance R_dg. The validity of this method was verified upon a set of pseudomorphic HEMTs having different gate widths tested on wafer at several bias and temperature conditions. Very good agreement between the simulated and measured S-parameters has been obtained. The procedure has been implemented in Agilent VEE language as a fully automated tool to allow an accurate, fast and complete device characterization requiring no operator supervision.     

Soft error modeling and remediation techniques in ASIC designs

Soft errors due to cosmic radiations are the main reliability threat during lifetime operation of digital systems. Fast and accurate estimation of soft error rate (SER) is essential in obtaining the reliability parameters of a digital system in order to balance reliability, performance, and cost of the system. Previous techniques for SER estimation are mainly based on fault injection and random simulations. In this paper, we present an analytical SER modeling technique for ASIC designs that can significantly reduce SER estimation time while achieving very high accuracy. This technique can be used for both combinational and sequential circuits. We also present an approach to obtain uncertainty bounds on estimated error propagation probability (EPP) values used in our SER modeling framework. Comparison of this method with the Monte-Carlo fault injection and simulation approach confirms the accuracy and speed-up of the presented technique for both the computed EPP values and uncertainty bounds.Based on our SER estimation framework, we also present efficient soft error hardening techniques based on selective gate resizing to maximize soft error suppression for the entire logic-level design while minimizing area and delay penalties. Experimental results confirm that these techniques are able to significantly reduce soft error rate with modest area and delay overhead.     

Compensation technique for DC and transient instability of thin film transistor circuits for large-area devices

A reliable driving scheme that can compensate for the inherent instability of hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) is essential for implementation of large-area devices including displays and sensor arrays for bio-imaging applications. In particular, for high precision and high-resolution devices, the technique should be accurate and fast. A new driving scheme is presented that enables control of the DC and transient shift in the threshold voltage (V _T ) and gate voltage of drive/amplifier TFT, while fulfilling the timing requirements for the different applications. The transient shift in the gate voltage has been known to contribute as much as 10% error in controlling the DC shift in the V _T whereas it is less than 0.5% for the driving scheme presented here.     

Fast parallel prefix logic circuits for n2n round-robin arbitration

An n2n round-robin arbiter (RRA) searches its n inputs for a 1, starting from the highest-priority input. It picks the first 1 and outputs its index in one-hot encoding. RRA aims to be fair to its inputs and maintains fairness by simply rotating the input priorities, i.e., the last arbitrated input becomes the lowest-priority input. Arbiters are used to multiplex the usage of shared resources among requestors as well as in dispatch logic where the purpose is load balancing among multiple resources. Today, arbiters have hundreds of ports and usually need to run at very high clock speeds. This article presents a new gate-level RRA circuit called Thermo Coded-Parallel Prefix Arbiter (TC-PPA) that scales to any number of requestors. It uses parallel prefix network topologies (borrowed from fast carry lookahead adders) to generate a thermometer-coded pointer, thus greatly reducing critical path. Code generators were written not only for TC-PPA but also for the 5 highly competitive circuits in the literature (9 including their variants), and a rich set of timing/area results were obtained using a standard-cell based logic synthesis flow with a novel iterative strategy based on binary search. Synthesis runs include results with wire-load and without. Results show that for 54 or more ports (except 256) TC-PPA offers the best timing (lowest latency) as well as competitive area. Contributions also include transaction-level simulations that show when pipelining is used to boost clock rate, latency and input FIFO sizes are adversely affected, and hence pipelining cannot be indiscriminately exploited to trim clock period.