64-bit Block ciphers: hardware implementations and comparison analysis

A performance comparison for the 64-bit block cipher (Triple-DES, IDEA, CAST-128, MISTY1, and KHAZAD) FPGA hardware implementations is given in this paper. All these ciphers are under consideration from the ISO/IEC 18033-3 standard in order to provide an international encryption standard for the 64-bit block ciphers. Two basic architectures are implemented for each cipher. For the non-feedback cipher modes, the pipelined technique between the rounds is used, and the achieved throughput ranges from 3.0 Gbps for IDEA to 6.9 Gbps for Triple-DES. For feedback ciphers modes, the basic iterative architecture is considered and the achieved throughput ranges from 115 Mbps for Triple-DES to 462 Mbps for KHAZAD. The throughput, throughput per slice, latency, and area requirement results are provided for all the ciphers implementations. Our study is an effort to determine the most suitable algorithm for hardware implementation with FPGA devices.     

基于IP-core的64位PCI接口设计与实现

介绍一种Linux下的基于64位PCI总线和多片FPGA的高速计算平台的设计和实现,利用Altera公司的PCI软核——PCI_mt64构建此平台的PCI桥接口模块,设计出一种兼容总线宽度64位/32位、时钟66MHz的PCI规范的接口模块,以及与此相配合的DMA状态机,并给出Linux驱动的关键部分。     

16位DLL在32位应用程序中的调用

本文介绍了将用于专门设备驱动及某些特殊条件下的16位DLL移植到32位操作系统的方法。这些驱动程序无法直接移植到Win32平台,需要用特别的转换程序(THUNKS)来将它们与32位应用程序融合起来。本文描述了编写THUNKS的专门技术。     

SSIS在32位、64位进程中性能研究

通过分析实验,对利用SSIS开发的ETL程序,在32位和64位进程内的效率变化情况进行了研究,为企业级应用迁移提供参考.     

AES算法优化及其在ARM上的实现

为了提高高级加密标准（AES）算法在ARM上的执行效率,针对明文长度和密钥长度均为128位的AES算法,提出了一种在ARM上高效运行并且占用较少ROM空间的实现方案。S盒采用即时计算的方法生成,将列混合和逆列混合修改为针对32位字的操作,密钥扩展采用即时密钥扩展。在S3C2440处理器上实现的实验结果表明,AES算法的优化方案可以在ARM处理器上高效运行并占用了较少的ROM空间。该方案可以应用于存储空间较小的嵌入式系统中。     

The μVP 64-bit vector coprocessor: a new implementation ofhigh-performance numerical computation

The architecture and design of the μVP, a single-chip vector coprocessor developed to meet the needs of high-performance processors, are described. The μVP is a supercomputer component implemented on a single large-scale-integrated (LSI) CMOS chip. With 206 MFLOPS single-precision and 106-MFLOPS double-precision performance at 50 MHz, the μVP offers a rate almost equivalent to that typical minisupercomputers     

高级加密标准算法Rijndael的分析与应用

介绍了高级加密标准Rijndael算法的背景和特点,深入研究和分析了该算法的实现原理和过程,并给出了该算法在文件加解密过程实现的关键代码。     

差分能量攻击样本选取方法

为了解决差分能量攻击(DPA)中的样本选取问题,提出了一套样本选取方法。方法从所使用的实验平台出发,通过理论分析提出样本选取方式和数量,然后进行实验验证。以AES算法为例,分别进行了仿真实验和实测实验,验证了所提出的选取方法的准确性。结果表明,仿真攻击的明文样本应该按顺序取,数量为一个全排列,而实测攻击应该直接采用大量随机数,两者对明文样本的要求存在较大差别。     

基于混沌和位运算的图像加密算法

为了有效改进图像加密效果及其安全性,在对基于混沌系统及位运算的图像加密算法进行研究的基础上,提出一种改进的数字图像加密算法,该算法首先采用Logistic映射产生混沌序列构造行、列置乱向量进行像素位置的置乱,再利用分段非线性Logistic产生的序列构造灰度置乱放大因子,对图像进行灰度置乱,且对两个过程进行迭代操作。该算法不仅密钥空间增大,灰度直方图更加均匀,而且像素相关性变弱,运算速度较传统算法更快。实验结果表明,改进算法具有良好的加密效果和安全性。     

64位流处理器中运算群的设计与验证

流处理器作为新型高性能处理器,能够高效地处理32位流程序.但是对于64位流处理器的设计,由于VLSI技术的限制,存在着很多挑战.运算群作为流处理器的核心运算部件,在整个流处理器中起着重要作用.运算群部件设计的好坏直接关系到流处理器的性能.本文以典型的流处理器为模型,说明了64位流处理器中运算群的设计技术,并对其功能进行了模拟验证,达到了预期效果.     

面向对象数据库系统O2DB中对象标识的设计与管理

Ｏ２ＤＢ是一个开发出的面向对象数据库系统的核心原型，而对象标识是面向对象方法中的一个重要特征，对于ＯＯＤＢ更为重要。文中着重阐述了面向对象数据库系统（ＯＯＤＢＭＳ）Ｏ２ＤＢ中对象标识的设计与实现方法，详细介绍了对象标识的定义、性质，对于数据共享、数据一致性的作用以及在Ｏ２ＤＢ中的设计与实现方法。     

一种双域Montgomery求逆算法与硬件实现

有限域上的求逆运算是椭圆曲线密码算法的关键运算之一。分别对GF（p）和GF（2ⁿ）域上的Montgomery模逆算法进行分析,并将GF（2ⁿ）域上的Montgomery模逆算法中对变量阶数的比较进行了改进,这样不仅利于GF（p）和GF（2ⁿ）域上的模逆运算在统一的硬件结构上实现,也解决了数据位数较大时进行阶数比较延迟较大的问题,在此基础上提出一种基于GF（p）和GF（2ⁿ）双域上统一的模逆算法,并根据算法,采用双域可伸缩运算单元,实现了一种可扩展的统一Montgomery模逆硬件结构。设计采用Verilog-HDL语言进行硬件描述,并基于0.18 μm工艺标准单元库进行了综合,结果表明该设计与其他设计相比具有灵活性好、性能高的特点。     

The TX1 32-bit microprocessor: performance analysis, and debuggingsupport

The 32-bit TX1 microprocessor, developed to meet the architectural specification of Japan's TRON (The Real-Time-Operating Nucleus) project, has been given a loosely coupled pipeline structure to meet the demands of high-performance systems. The authors discuss the design architecture of the TX1, provide some performance analysis for the design, and describe the debugging feature provided on the processor. Results for several benchmark programs show that the average performance of the TX1 is over 5 MIPS (million instructions per second)     

基于比特置换与核酸序列库的混沌图像加密算法

提出了一种基于比特置换与DNA序列运算的混沌图像加密的算法。该算法首先利用Chen系统产生混沌映射索引对图像进行像素位置置乱,结合蝶形网络对比特位置乱,以实现位级别置乱。再对图像进行DNA编码,并与核酸序列进行代数运算,实现像素的替代,进一步提高了加密的安全性。最后通过密文反馈来进一步增强算法的混淆和扩散特性。实验和安全性分析结果表明,该算法不仅密钥空间大、对密钥的敏感性强,而且能有效抵御统计性分析和穷举分析等攻击操作。     

基于FPGA的32位并行乘法器的设计与实现

首先分析比较了几种典型的乘法器实现结构，然后采用树型组合方式，对其结构进行了优化，最后在FPGA上设计并实现了一个高性能的32位并行乘法器。     

The Impact of 16-bit and 32-bit ASNs Coexistence on the Accuracy of Internet AS Graph

Modeling Internet structure as an autonomous system (AS) graph has attracted researchers over years. AS graph model demonstrates the power-law distribution of the Internet. It also demonstrates the relationship between the cluster coefficient and the small-world structure of the Internet. To obtain an accurate AS graph model, the data used to generate the graph should be massive and correct. In this work, we studied the correctness of the data that is utilized to generate Internet AS graph. We conducted an experiment to measure the popularity of 32-bit AS numbers (ASNs) in the Internet. We examined the impact of the special purpose 16-bit reserved ASN AS23456 on the accuracy of the AS graph. To this end, we proposed a cleaning algorithm to correct the conflict that AS23456 produces. Our results show that the current existing method of mapping 16-bit and 32-bit ASNs reduces the fidelity of the constructed AS graph to various graph parameters.     

Side-channel countermeasures utilizing dynamic logic reconfiguration: Protecting AES/Rijndael and Serpent encryption in hardware

Dynamic logic reconfiguration is a concept that allows for efficient on-the-fly modifications of combinational circuit behavior in both ASIC and FPGA devices. The reconfiguration of Boolean functions is achieved by modification of their generators (e.g., shift register-based look-up tables) and it can be controlled from within the chip, without the necessity of any external intervention. This hardware polymorphism can be utilized for the implementation of side-channel attack countermeasures, as demonstrated by Sasdrich et al. for the lightweight cipher PRESENT.In this work, we adapt these countermeasures to two of the AES finalists, namely Rijndael and Serpent. Just like PRESENT, both Rijndael and Serpent are block ciphers based on a substitution–permutation network. We describe the countermeasures and adjustments necessary to protect these ciphers using the resources available in modern Xilinx FPGAs. We describe our implementations and evaluate the side-channel leakage and effectiveness of different countermeasures combinations using a methodology based on Welch’s t-test. Furthermore, we attempt to break the protected AES/Rijndael implementation using second-order DPA/CPA attacks.We did not detect any significant first-order leakage from the fully protected versions of our implementations. Using one million power traces, we detect second-order leakage from Serpent encryption, while AES encryption second-order leakage is barely detectable. We show that the countermeasures proposed by Sasdrich et al.are, with some modifications, successfully applicable to AES and Serpent.     

Chen氏系统的标度化设计及其硬件实现

为了使混沌系统得到有效的利用,提出了一种基于Chen氏系统的标度化设计方法。对Chen氏系统进行比例变换和微分〖CD*2〗积分变换,并详细分析了标度化Chen氏系统的特性;以标度化系统为模型用普通电路模块搭建标度化Chen氏混沌电路;对标度化系统采用单向单变量耦合替换法,实现驱动系统和响应系统的同步。理论分析与电路实验结果表明该方法可以直接应用于工业生产。