What factors contribute to the acceptance of artificial intelligence? A systematic review

Artificial Intelligence (AI) agents are predicted to infiltrate most industries within the next decade, creating a personal, industrial, and social shift towards the new technology. As a result, there has been a surge of interest and research towards user acceptance of AI technology in recent years. However, the existing research appears dispersed and lacks systematic synthesis, limiting our understanding of user acceptance of AI technologies. To address this gap in the literature, we conducted a systematic review following the Preferred Reporting Items for Systematic Reviews and meta-Analysis guidelines using five databases: EBSCO host, Embase, Inspec (Engineering Village host), Scopus, and Web of Science. Papers were required to focus on both user acceptance and AI technology. Acceptance was defined as the behavioural intention or willingness to use, buy, or try a good or service. A total of 7912 articles were identified in the database search. Sixty articles were included in the review. Most studies (n = 31) did not define AI in their papers, and 38 studies did not define AI for their participants. The extended Technology Acceptance Model (TAM) was the most frequently used theory to assess user acceptance of AI technologies. Perceived usefulness, performance expectancy, attitudes, trust, and effort expectancy significantly and positively predicted behavioural intention, willingness, and use behaviour of AI across multiple industries. However, in some cultural scenarios, it appears that the need for human contact cannot be replicated or replaced by AI, no matter the perceived usefulness or perceived ease of use. Given that most of the methodological approaches present in the literature have relied on self-reported data, further research using naturalistic methods is needed to validate the theoretical model/s that best predict the adoption of AI technologies.     

Layered moving-object segmentation for stereoscopic video using motion and depth information

A novel layered stereoscopic moving-object segmentation method is proposed in this paper by exploiting both motion information and depth information to extract moving objects for each depth layer with high accuracy on their shape boundary. By taking a higher-order statistics on two frame-difference fields across three adjacent frames, the computed motion information are used to conduct change detection and generate one motion mask that consists of all the moving objects from all the depth layers involved at each view. It would be highly desirable, and challenging, to further differentiate them according to their residing depth layer to achieve layered segmentation. For that, multiple depth-layer masks are generated using our proposed disparity estimation method, one for each depth layer. By intersecting the motion mask and one depth-layer mask at any given layer-of-interest, the moving objects associated with the corresponding layer are then extracted. All the above-mentioned processes are repeatedly performed along the video sequence with a sliding window of three frames at a time. For demonstration, only the foreground and the background layers are considered in this paper, while the proposed method is generic and can be straightforwardly extended to more layers, once the corresponding depth-layer masks are made available. Experimental results have shown that the proposed layered moving-object segmentation method is able to segment the foreground and background moving objects separately, with high accuracy on their shape boundary. In addition, the required computational load is considered fairly inexpensive, since our design methodology is to generate masks and perform intersections for extracting the moving objects for each depth layer.     

K Band SiGe HBT single ended active inductors

The study of monolithic integration of active inductors (AI) on a 0.25 μm SiGe BiCMOS technology with 4 metal layers and HBTs with f_T=120 GHz is presented. Two topologies are presented and their performance discussed. Q values higher than 30 were obtained on a 3.4 GHz bandwidth at 28 GHz and maximum values as high as 100. Active inductors can be biased with low power, such as 2 V with a nominal DC current of 0.6 mA. The inductance value is controlled by external bias voltages and adjustments up to 40% were measured. Simple gyrators topologies with only 2 transistors are used for low power consumption and good performance at K Band is proved. The internal parameters of small signal model of HBT were studied and the crucial parameter to enhance the negative resistance and so the Q of the AI was identified.     

Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer

This paper presents a new design of a grounded active inductor (AI) with an improved topology based on Manetakis regulated cascode active inductor comprising of three control voltages for tunability. An additional pMOST was introduced in the design as a drain load at the output of nMOST source follower. The aim of this work is to design a CMOS AI at Ku band using AIDA-C, a state-of-the-art multi-objective multi-constraint circuit-level optimization tool. Firstly, a reasonable AI operating at Ku band was manually designed using a 130 nm technology. This circuit and its design variables were fed to AIDA-C as an element of the initial population. Then the sizing of the proposed AI MOSTs was optimized. AIDA-C circuit sizing tool is able to achieve not only one but a set of solutions for the AI exhibiting high quality factor at a predefined Ku band operating frequency. This set of alternative Pareto optimal solutions enables the designer to choose the most suitable circuit sizing for a given application. AI’s main performance parameters in terms of s parameters (s₁₁), quality factor (Q), inductance value (L), linearity, noise figure, power consumption and tunability based on control and biasing voltages are presented. Layout of the optimized AI is also presented. This AI was used to design active filters. Their selectivity, insertion losses and noise analysis is presented and discussed.     

Designing leakage tolerant, low power wide-OR dominos for sub-130 nm CMOS technologies

In this paper, we discuss the design of leakage tolerant wide-OR domino gates for deep submicron (DSM), bulk CMOS technologies. Technology scaling is resulting in a 3×-5× increase in transistor I_OFF/μm per generation causing 15-30% degradation in the noise margin of high performance domino gates. We investigate several techniques that can improve the noise margin of domino logic gates and thereby ensure their reliable operation for sub-130 nm technologies. Our results indicate that, selective usage of dual V_TH transistors shows acceptable energy-delay tradeoffs for the 90 nm technology. However, techniques like supply voltage (V_cc) reduction or using non-minimum L_e transistors are required in order to ensure robust and low power operation of wide-OR domino designs for the 70 nm generation.     

Enhancing the robustness of object detection via 6G vehicular edge computing

Academic and industrial communities have been paying significant attention to the 6th Generation (6G) wireless communication systems after the commercial deployment of 5G cellular communications. Among the emerging technologies, Vehicular Edge Computing (VEC) can provide essential assurance for the robustness of Artificial Intelligence (AI) algorithms to be used in the 6G systems. Therefore, in this paper, a strategy for enhancing the robustness of AI model deployment using 6G-VEC is proposed, taking the object detection task as an example. This strategy includes two stages: model stabilization and model adaptation. In the former, the state-of-the-art methods are appended to the model to improve its robustness. In the latter, two targeted compression methods are implemented, namely model parameter pruning and knowledge distillation, which result in a trade-off between model performance and runtime resources. Numerical results indicate that the proposed strategy can be smoothly deployed in the onboard edge terminals, where the introduced trade-off outperforms the other strategies available.     

AI语音关键技术与业务实践研究

研究了AI语音技术在业务领域的实践应用,梳理归纳了AI语音三大关键技术:语音识别、语音合成、自然语言处理的技术原理与技术演进路线;描述了构建在三大技术之上的AI语音产品的架构、功能特色和应用场景;详细说明了AI坐席产品、AI质检产品与云呼叫中心对接方案,并通过对比的方法给出各方案的优势劣势;最后对AI语音技术与产品进行...     

Self-determination and attitudes toward artificial intelligence: Cross-national and longitudinal perspectives

Artificial intelligence (AI) is becoming increasingly important in all domains of life. Therefore, it is crucial to understand individuals’ attitudes towards AI. This article investigated attitudes toward AI through two studies that are based on the self-determination theory and basic psychological needs (autonomy, competence, and relatedness). Study 1 used cross-sectional samples of adult populations aged 18–75 from Finland (N = 1,541), France (N = 1,561), Germany (N = 1,529), Ireland (N = 1,112), Italy (N = 1,530), and Poland (N = 1,533). Study 2 was based on a longitudinal two-wave sample of adults aged 18–80 from Finland (N = 828). Based on the robust regression analyses, Study 1 found that fulfillment of basic psychological needs was associated with higher AI positivity and lower AI negativity across Europe. According to the Study 2 results, based on hybrid multilevel regression models, autonomy and relatedness increased AI positivity and decreased AI negativity over time. The results provide robust evidence on the role of self-determination in attitudes towards AI. Self-determination is an important factor in AI acceptance and is becoming increasingly important considering the rapid development and adoption of AI solutions.     

2020年“战略自主”框架下的 欧洲数字主权建设全面提速

2020年,欧洲在“战略自主”框架下全面提速数字主权建设:通过大力发展数字技术和数字基础设施,构建服务全球的欧洲供应链;积极争夺技术主权,在AI、量子、6G等领先技术领域寻求突破;全面提升网络安全,建立弹性、技术主权和领导力,建设预防、威慑和应对的业务能力;同时,欧盟加大网络空间治理力度,不仅继续推动在网络空间国际法领域的领导力,还全方位加大了对数字服务平台的监管。     

On the scaling issues and high-κ replacement of ultrathin gate dielectrics for nanoscale MOS transistors

According to the recent prediction made by the Semiconductor Industry Association (SIA) in International Technology Roadmap for Semiconductors (ITRS), the silicon technology will continue its historical rate of advancement with the Moore’s law for at least a couple of decades. With this trend, the silicon gate oxide will be scaled down to its physical limit in order to maintain proper control of the nanosize MOS transistors. This work reviews several critical issues of MOS gate dielectrics in the nanometer range.Although it was suggested that the conventional oxide can be scaled down, in principle, to two atomic layers of about 7 Å, this is not practically feasible because of the non-scalabilities of interface, trap capture cross-section, leakage current, and the statistical parameters of fabrication processes. Introducing a high-κ material can help solving most of the problems by using physically thicker high-κ gate dielectric films but several other reliability problems of the MOS devices rises. Being used in the extreme fine structure, the requirements for the material properties of the new high-κ are very stringent. Unfortunately, most of the high-κ materials are ionic metal oxides. This fundamental physics results in several undesirable instability issues when interfacing with silicon and with the CMOS processes. Bulk type thin oxynitride/high-κ stack could be a good solution for the coming technology nodes.     

Surface and interface depletion corrections to free carrier-density determinations by hall measurements

Errors in the determination of (N_D-N_A) for semiconductor epitaxial layers by the Hall method can result if corrections for carrier depletion are omitted in the calculations. Simple practical procedures are discussed to correct for carrier depletion that occurs in epitaxial layers at their free surfaces, and their interfaces with semi-insulating substrates. Theoretical estimates of carrier depletion in GaAs indicate that depletion regions can extend several microns into high purity epitaxial layers, and can cause (N_D-N_A) to be considerably underestimated. Experimental evidence is presented in support of the theory.     

Handling mobility in future publish-subscribe information-centric networks

Future information-oriented Internet architectures are expected to effectively support mobility. PSIRP, an EU FP7 research project, designed, prototyped, and investigated a clean-slate architecture for the future Internet based on the publish-subscribe paradigm. PURSUIT, another EU FP7 research project, is further developing this architecture, which we refer to as Ψ, the Publish Subscribe Internet (PSI) architecture, extending it in various directions, including a deeper investigation of higher (transport and application) and lower layers (e.g., various link technologies, such as wireless and optical). In this paper we present the basics of the Ψ architecture, including the built-in multicast and caching mechanisms, with particular focus on mobility support. We discuss how the native, clean-slate, Ψ instantiation of the information-centric model can support mobility and also present an overlay variant of Ψ we have developed in order to provide an evolutionary path to adoption. Based on analysis and simulation we demonstrate the advantages of the proposed architecture compared to well established solutions such as Mobile IPv6.     

人工智能(AI)在电力系统中的应用

简要地介绍了人工智能技术的基本概念,并指出其在电力系统中的应用范围。对专家系统、人工神经网络、模糊理论、遗传算法等人工智能技术的基本概念进行了简单的介绍,并从实用化的观点对他们在电力系统故障诊断中的应用特点、存在问题进行分析,最后指出综合运用多种人工智能技术是电力系统中的人工智能技术应用的最新发展动向,并提出了有针对性的建议。     

Methods increasing inherent resistance of ECC designs against horizontal attacks

Due to the nature of applications such as critical infrastructure and the Internet of Things etc. side channel analysis attacks are becoming a serious threat. Side channel analysis attacks take advantage from the fact that the behaviour of crypto implementations can be observed and provides hints that simplify revealing keys. A new type of SCA is the so called horizontal differential SCA. In this paper we investigate two different approaches to increase the inherent resistance of our hardware accelerator for the kP operation. The first approach aims at reducing the impact of the addressing in our design by realizing a regular schedule of the addressing. In the second approach, we investigated how the formula used to implement the multiplication of GF(2ⁿ)-elements influences the results of horizontal DPA attacks against a Montgomery kP-implementation. We implemented 5 designs with different partial multipliers, i.e. based on different multiplication formulae. We used two different technologies, i.e. a 130 and a 250 nm technology, to simulate power traces for our analysis. We show that the implemented multiplication formula influences the success of horizontal attacks significantly. The combination of these two approaches leads to the most resistant design. For the 250 nm technology only 2 key candidates could be revealed with a correctness of about 70% which is a huge improvement given the fact that for the original design 7 key candidates achieved a correctness of more than 90%. For our 130 nm technology no key candidate was revealed with a correctness of more than 60%.     

Effects of temperature in deep-submicron global interconnect optimization in future technology nodes

The resistance of on-chip interconnects and the current drive of transistors are strongly temperature-dependent. As a result, the interconnect performance in Deep-Submicron technologies is affected by temperature in a substantial proportion. In this paper we evaluate thermal effects in global RLC interconnects and quantify their impact in a standard optimization procedure based on repeaters insertion. By evaluating the difference between a simple RC and an accurate RLC model, we show how the temperature induced increase of resistance may reduce the impact of inductance. We also project the evolution of such effects in future CMOS technologies, according to the semiconductor roadmap.     

Anodes for Li-ion batteries based on <Emphasis Type="Italic">p</Emphasis>-Si with self-organized macropores

The practical application of microstructured anodes produced by the electrochemical etching of single-crystal silicon is limited by their cost. The proposed approach will make it possible to reduce the cost for several reasons: less stringent requirements to the quality of the initial material due to the replacement of n-Si with p-Si, the exclusion of operations that are aimed at the formation of nucleation centers, and the repeated use of a silicon substrate. The formation of random macropores in 10–20 Ω cm p-Si (100) in a 4% solution of hydrofluoric acid in dimethylformamide is studied and the role of chemical etching is revealed. The dependences on the current density are obtained for the etching rate, morphology of the porous layers, effective valence, pore density, and average pore diameter. The part played by chemical dissolution in the electrolyte is determined. A technology is developed for the deposition of 50-μ-thick porous layers. This technology combines successive detachments of several membranes from the same substrate and provides enhanced porosity (~70%). The electrochemical characteristics of anodes formed from these membranes are examined, and 120+ test cycles are performed in the mode with the charge capacity limited to 1000 mA h/g at a current of 0.2 A/g.     

A new dielectric isolation method using porous silicon

A new dielectric isolation technology is proposed. In the new structure, single crystalline Si islands are separated from the silicon substrate by oxidized porous silicon. It is based on the following characteristics of the porous silicon oxide formation: (1) p-type Si is more easily changed to porous silicon than n-type Si; (2) porous silicon is formed along the anodic reaction current flow line; (3) the change in volume of porous silicon after oxidation is relatively small; (4) thick porous silicon films (10 μm) can be obtained easily. In this method, a p-type isolated layer is obtained by proton implantation used for an n-type layer formation. Lateral p-n junctions fabricated in such isolated silicon layers show lower leakage current than those reported in SOS technology.     

HgCdTe molecular beam epitaxy technology: A focus on material properties

HgCdTe MBE technology is becoming a mature growth technology for flexible manufacturing of short-wave, medium-wave, long-wave, and very long-wave infrared focal plane arrays. The main reason that this technology is getting more mature for device applications is the progress made in controlling the dopants (both n-type and p-type in-situ) and the success in lowering the defect density to less than 2 x 10⁵/cm² in the base layer. In this paper, we will discuss the unique approach that we have developed for growing As-doped HgCdTe alloys with cadmium arsenide compound. Material properties including composition, crystallinity, dopant activation, minority carrier lifetime, and morphology are also discussed. In addition, we have fabricated several infrared focal plane arrays using device quality double layers and the device results are approaching that of the state-of-the-art liquid phase epitaxy technology.     

Impact of technology scaling on thermal behavior of leakage current in sub-quarter micron MOSFETs: perspective of low temperature current testing

The increase in the off-state current for sub-quarter micron CMOS technologies is making conventional I_DDQ testing ineffective. Since natural process variation together with low-V_TH devices can significantly increase the absolute leakage value and the variation, choosing a single threshold for I_DDQ testing is impractical. One of the potential solutions is the cooling of the chip during current testing. In this paper we analyze the impact of CMOS technology scaling on the thermal behavior of different leakage current mechanisms in n-MOSFETs and estimate the effectiveness of low temperature I_DDQ testing. We found that the conventional single threshold low temperature I_DDQ testing is not effective for sub-quarter micron CMOS technologies and propose the low temperature ΔI_DDQ test method. The difference between pass and fail current limits was estimated more than 200× for 0.13-μm CMOS technology.