针对片上网络组播通信模型的设计与仿真

文章提出了一种针对片上网络的组播通信模型,能够为片上网络提供无死锁的通信.该模型能显著减少总通信量,增加通道利用率;在测试模式下,能有效节省测试时间.将该模型仿真应用到二维带环网格拓扑结构的片上网络中,试验结果表明,该模型较单播通信具有更小的平均传输延迟和更高的吞吐量.     

基于通讯的NoC设计

近年来，一种全新的集成电路体系结构——Network on Chip（NoC）已经成为徽电子学科研究的热点佃题之一，其核心思想是将计算机网络技术移植到芯片设计中来，从体系结构上彻底解决片上通讯的瓶颈问题。文章提出了一种基于通讯的NoC设计方法，通过监控和协调NoC的网络通讯来获得更好的性能．并总结了实现该设计方法所必须研究的关键技术。     

High-level customization framework for application-specific NoC architectures

Network-on-Chip (NoC) has been recognized as the new paradigm to interconnect and organize a high number of cores. NoCs address global communication issues in System-on-Chips (SoC) involving communication-centric design and implementation of scalable communication structures evolving application-specific NoC design as a key challenge to modern SoC design. In this paper we present a SystemC customization framework and methodology for automatic design and evaluation of regular and irregular NoC architectures. The presented framework also supports application-specific optimization techniques such as priority assignment, node clustering and buffer sizing. Experimental results show that generated regular NoC architectures achieve an average of 5.5 % lower communication-cost compared to other regular NoC designs while irregular NoCs proved to achieve on average 4.5×higher throughput and 40 % network delay reduction compared to regular mesh topologies. In addition, employing a buffer sizing algorithm we achieve a reduction in network’s power consumption by an average of 45 % for both regular and irregular NoC design flow.     

Custom Networks-on-Chip Architectures With Multicast Routing

In this paper, we consider the problem of synthesizing custom networks-on-chip (NoC) architectures that are optimized for a given application. We consider both unicast and multicast traffic flows in the input specification. Multicast traffic flows are used in a variety of applications, and their direct support with only replication of packets at optimal bifurcation points rather than full end-to-end replication can significantly reduce network contention and resource requirements. Our problem formulation is based on the decomposition of the problem into the inter-related steps of finding good flow partitions, deriving a good physical network topology for each group in the partition, and providing an optimized network implementation for the derived topologies. Our solutions may be comprised of multiple custom networks, each interconnecting a subset of communicating modules. We propose several algorithms that can systematically examine different flow partitions, and we propose Rectilinear–Steiner-Tree (RST)-based algorithms for generating efficient network topologies. Our design flow integrates floorplanning, and our solutions consider deadlock-free routing. Experimental results on a variety of NoC benchmarks showed that our synthesis results can on average achieve a 4.82 times reduction in power consumption over different mesh implementations on unicast benchmarks and a 1.92 times reduction in power consumption on multicast benchmarks. Significant improvements in performance were also achieved, with an average of 2.92 times reduction in hop count on unicast benchmarks and 1.82 times reduction in hop count on multicast benchmarks. To further gauge the effectiveness of our heuristic algorithms, we also implemented an exact algorithm that enumerates all distinct set partitions. For the benchmarks where exact results could be obtained, our algorithms on average can achieve results within 3% of exact results, but with much shorter execution times.      

A multi-objective adaptive immune algorithm for multi-application NoC mapping

Current SoC design trends are characterized by the integration of larger amount of IPs targeting a wide range of application fields. Such multi-application systems are constrained by a set of requirements. In such scenario network-on-chips (NoC) are becoming more important as the on-chip communication structure. Designing an optimal NoC for satisfying the requirements of each individual application requires the specification of a large set of configuration parameters leading to a wide solution space. It has been shown that IP mapping is one of the most critical parameters in NoC design, strongly influencing the SoC performance. IP mapping has been solved for single application systems using single and multi-objective optimization algorithms. In this paper we propose the use of a multi-objective adaptive immune algorithm (M²AIA), an evolutionary approach to solve the multi-application NoC mapping problem. Latency and power consumption were adopted as the target multi-objective functions. To compare the efficiency of our approach, our results are compared with those of the genetic and branch and bound multi-objective mapping algorithms. We tested 11 well-known benchmarks, including random and real applications, and combines up to 8 applications at the same SoC. The experimental results showed that the M²AIA decreases in average the power consumption and the latency 27.3 and 42.1 % compared to the branch and bound approach and 29.3 and 36.1 % over the genetic approach.     

Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks

Technology trends are driving parallel on-chip architectures in the form of multiprocessor systems-on-a-chip (MPSoCs) and chip multiprocessors (CMPs). In these systems, the increasing on-chip communication demand among the computation elements necessitates the use of scalable, high-bandwidth network-on-chip (NoC) fabrics instead of dedicated interconnects and shared buses. As transistor feature sizes are further miniaturized, more complicated NoC architectures become feasible that can support more demanding applications. Given the myriad emerging software-hardware combinations, for cost-effectiveness, a system designer critically needs to prune this widening NoC design-space to predict the interconnect fabric(s) that best balance(s) cost/performance, before the actual design process begins. This prompted us to develop Polaris, a system-level roadmapping toolchain for on-chip interconnection networks that helps designers predict the most suitable interconnection network design(s) tailored to their performance needs and power/silicon area constraints with respect to a range of applications that the system will run. Polaris explores the plethora of NoC designs based on projections of network traffic, architectures, and process characteristics. While Polaris's toolchain is extensible so new traffic, network designs, and technology processes can be added, the current version already incorporates 7872 NoC design points. Polaris is rapid, efficiently iterating over thousands of NoC design points, while maintaining high relative and absolute accuracies when validated against detailed NoC synthesis results.     

Solve the Tree Setup Problem and Minimize Control Overhead for High-Density Members in Delay-Bounded Distributed Multicast Networks

The multicast routing is one of the important techniques for achieving multicast applications in wireless networks, e.g., real-time video multicasting in Vehicular Ad-hoc NETwork (VANET). The main objective of a delay-bounded multicast algorithm is to determine the least-cost multicast tree while satisfying the delay-bounded requirement for multicasting voice/video transmission. Several multicast algorithms have been proposed, some disadvantages have not yet solved, including: (1) yielding a large numbers of control messages, (2) yielding dangling nodes, (3) exhibiting the cycle-free problem, (4) increasing the tree setup time, (5) suffering from the tree setup-break problem, etc. Thus, this paper proposes an adaptive distributed multicast routing (ADMR) algorithm to guarantee cycle-free, to overcome the tree setup-break and the dangling nodes problems while achieving the least-cost delay-bounded multicast tree for high density member multicast networks. Numerical results demonstrate that ADMR significantly outperforms the compared algorithms in the number of control messages and the setup convergence time. Finally, the worst case time complexity and the number of messages of ADMR are analyzed, which requires O(n · (m?+?c)) time and O(2m?+?2c) messages, respectively. The analyzed results of ADMR are lower than that of the compared algorithms.     

On the design of multi-wavelength copy interconnects with reduced complexity

A multi-wavelength copy interconnect is a switching network capable of replicating a signal arriving at the input on a specific wavelength to one or more outputs possibly on different wavelengths. Such an interconnect can be useful in building optical multicast switches for wavelength division multiplexing (WDM) networks. In this article, we investigate, for the first time, the problem of designing copy networks that can simultaneously multicast input signals to a set of outputs while changing the wavelength of the replica according to the required routing pattern. We propose a novel multi-wavelength crossbar (MWX) switch that can switch an input signal on a specific wavelength to two different output wavelengths. The proposed MWX is used as a building block to construct two classes of multi-log_2N copy networks, namely, baseline and Bene? interconnects. The design space of the proposed interconnect classes is characterized and their hardware complexity is analyzed. We show that the proposed interconnects are transparent to existing multicast routing algorithms, and present simple routing algorithms for routing of multicast requests over the proposed designs. Comparisons with existing designs confirm that the proposed interconnects require a smaller number of space switches and wavelength conversion processes as compared to most conventional copy networks. In particular, for a large number of wavelengths and for any number of fibers the proposed design requires 50% less switching elements as compared to best available designs.     

k冗余多播网络中网络编码算法设计与分析

k冗余多播网络采用网络编码可实现最大多播速率k的信息传输。该文利用最大距离可分码已有成果,给出k冗余多播网络在不同发送速率下所需的最小有限域,构造最大距离可分码[n, k]生成矩阵,将其列向量作为信源输出链路的全局编码向量,设计网络码字,实现网络编码。应用实例表明该网络编码方法相对现有的通用网络编码算法而言,具有更低的计算复杂度。     

SRNoC: A novel high performance Shared-Resource routing scheme for Network-on-Chip

This paper proposes a novel Shared-Resource routing scheme, SRNoC, that not only enhances network transmission performance, but also provides a high efficient load-balance solution for NoC design. The proposed SRNoC scheme expands the NoC design space and provides a novel effective NoC framework. SRNoC scheme mainly consists of the topology and routing algorithm. The proposed topology of SRNoC is based on the Shared-Resource mechanism, in which the routers are divided into groups and each group of routers share a set of specified link resource. Because of the usage of Shared Resource mechanism, SRNoC could effectively distribute the workload uniformly onto the network so as to improve the utilization of the resource and alleviate the network congestion. The proposed routing algorithm is a minimal oblivious routing algorithm. It could improve average latency and saturation load owing to its flexibility and high efficiency. In order to evaluate the load-balance property of the network, we proposed a method to calculate the Φ which represents the characteristic value of load-balance. The smaller the Φ, the better the performance in load-balance. Simulation results show that the average latency and saturation load are dramatically improved by SRNoC both in synthetic traffic patterns and real application traffic trace with negligible hardware overhead. Under the same simulation condition, SRNoC could cut down the total network workload to 48.67% at least. Moreover, SRNoC reduces the value of Φ 45% at least compared with other routing algorithms, which means it achieves better load-balance feature.     

Mapping and Scheduling for Circuit‐Switched Network‐on‐Chip Architecture

Network‐on‐chip (NoC) architecture provides a high‐performance communication infrastructure for system‐on‐chip designs. Circuit‐switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real‐time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in 6×6, 8×8, and 10×10 mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit‐switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.     

A multiobjective scatter search algorithm for fault-tolerant NoC mapping optimisation

Mapping IP cores to an on-chip network is an important step in Network-on-Chip (NoC) design and affects the performance of NoC systems. A mapping optimisation algorithm and a fault-tolerant mechanism are proposed in this article. The fault-tolerant mechanism and the corresponding routing algorithm can recover NoC communication from switch failures, while preserving high performance. The mapping optimisation algorithm is based on scatter search (SS), which is an intelligent algorithm with a powerful combinatorial search ability. To meet the requests of the NoC mapping application, the standard SS is improved for multiple objective optimisation. This method helps to obtain high-performance mapping layouts. The proposed algorithm was implemented on the Embedded Systems Synthesis Benchmarks Suite (E3S). Experimental results show that this optimisation algorithm achieves low-power consumption, little communication time, balanced link load and high reliability, compared to particle swarm optimisation and genetic algorithm.     

Application-aware virtual paths insertion for NOCs

Network-on-chip (NoC) has rapidly become a promising alternative for complex system-on-chip architectures including recent multicore architectures. Additionally, optimizing NoC architectures with respect to different design objectives that are suitable for a particular application domain is crucial for achieving high-performance and energy-efficient customized solutions. Despite the fact that many researches have provided various solutions for different aspects of NoCs design, a comprehensive NoCs system solution has not emerged yet. This paper presents a novel methodology to provide a solution for complex on-chip communication problems to reduce power, latency and area overhead. Our proposed NoC communication architecture is based on setting up virtual source–destination paths between selected pairs of NoCs cores so that the packets belonging to distance nodes in the network can bypass intermediate routers while traveling through these virtual paths. In this scheme, the paths are constructed for an application based on its task-graph at the design time. After that, the run time scheduling mechanism is applied to improve the buffer management, virtual channel and switch allocation schemes and hence, the constructed paths are optimized dynamically. Moreover, in our design the router complexity and its overheads are reduced. Additionally, the suggested router has been implemented on Xilinx Virtex-5 FPGA family. The evaluation results captured by SPLASH-2 benchmark suite reveal that in comparison with the conventional NoC router, the proposed router takes 25% and 53% reduction in latency and energy, respectively besides 3.5% area overhead. Indeed, our experimental results demonstrate a significant reduction in the average packet latency and total power consumption with negligible area overhead.     

BiLink: A high performance NoC router architecture using bi-directional link with double data rate

This paper presents a novel high performance Network-on-Chip (NoC) router architecture design using a bi-directional link with double data rate (BiLink). Ideally, it can provide as high as 2 times speed-up compared with the conventional NoC router. BiLink utilizes an extra link stage between routers and transmits two flits in one link per cycle using phase pipelining if both routers require to use the current link. To further increase the effective bandwidth, the direction of each link can be configured in every clock cycle to cater for different traffic loads from each side. Therefore, the data rate can be as high as 4 times compared with conventional NoC routers under uneven traffic. Centralized mode control scheme is implemented using a finite state machine (FSM) approach. Cycle-accurate simulations are carried out on both synthetic traffic patterns as well as real application benchmarks. Simulation results show that BiLink can provide as high as 90% and 250% speedup compared with conventional NoC routers for even and uneven traffic, respectively. 2X and 3X gains in throughput are obtained under even and uneven traffic, respectively, when compared with the conventional NoC router for the virtual channel flow control. The BiLink router architecture is synthesized using TSMC 65 nm process technology and it is shown that an area overhead of 28% over state-of-the-art bi-directional NoC is introduced while the critical path is about 9% higher than that of the conventional routers. Despite the overhead in critical path and power consumption, a 47.45% improvement of Energy-Delay-Product (EDP) is achieved by BiLink under high injection rate traffic.     

Low-cost and low-power unidirectional torus network-on-chip with corner buffer power-gating

Network-on-chip (NoC) is one of critical communication architectures for the scaling of future many-core processors. The challenge for on-chip network is reducing design complexity to save both area and power while providing high performance such as low latency and high throughput. Especially, with increase of network size, both design complexity and power consumption have become the bottlenecks preventing proper network scaling. Moreover, as technology continuously scales down, leakage power takes up a larger fraction of total NoC power. It is increasingly important for a power-efficient NoC design to reduce the increasing leakage power. Power-gating, as a representative low-power technique, can be applied to an on-chip network for mitigating leakage power. In this paper, we propose a low-cost and low-power router architecture for the unidirectional torus network, and adopt an improved corner buffer structure for the inoffensive power-gating, which has minimal impact on network performance. Besides, an explicit starvation avoidance mechanism is introduced to guarantee injection fairness while decreasing its negative impact on network throughput. Simulation results with synthetic traffic show that our design can improve network throughput by 11.3% on average and achieve significant power-saving in low- and medium-load regions. In the SPLASH-2 workload simulation, our design can save on average 27.2% of total power compared to the baseline, and decrease 42.8% average latency compared to the baseline with power-gating.     

Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding

Network on Chip (NoC) is an enabling methodology of integrating a very high number of intellectual property (IP) blocks in a single System on Chip (SoC). A major challenge that NoC design is expected to face is the intrinsic unreliability of the interconnect infrastructure under technology limitations. Research must address the combination of new device-level defects or error-prone technologies within systems that must deliver high levels of reliability and dependability while satisfying other hard constraints such as low energy consumption. By incorporating novel error correcting codes it is possible to protect the NoC communication fabric against transient errors and at the same time lower the energy dissipation. We propose a novel, simple coding scheme called Crosstalk Avoiding Double Error Correction Code (CADEC). Detailed analysis followed by simulations with three commonly used NoC architectures show that CADEC provides significant energy savings compared to previously proposed crosstalk avoiding single error correcting codes and error-detection/retransmission schemes.     

乘积码在片上网络中的应用研究

研究了一种适用于片上网络(NoC)的能够纠3个错码的乘积码,该码的行编码采用扩展汉明码,列编码采用奇偶交验码实现.给出了乘积码的编解码方法,在此基础上对乘积码功耗和复杂度进行了仿真并与现有的码进行了分析比较.最后,给出了乘积码功能验证结果,结果表明所设计的乘积码功能正确,适合在NoC中应用.     

A system-level bandwidth design method for wormhole network-on-chip

To improve the Network-on-Chip (NoC) performance, we propose a system-level bandwidth design method customising the bandwidths of the NoC links. In details, we first built a mathematical model to catch the relationship between the NoC commutation latency and the NoC link bandwidth, and then develop a bandwidth allocation algorithm to automatically optimise the bandwidth for each NoC link. The experimental results show that our bandwidth-customising method improves the NoC performance compared to the traditional uniform bandwidth allocation method. Besides, it can also make our NoC to achieve the same communication performance level as the uniform bandwidth NoC but using fewer bandwidth resources, which is beneficial to save the NoC area and power.     

Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors

Today, chip multiprocessors (CMPs) that accommodate multiple processor cores on the same chip have become a reality. As the communication complexity of such multicore systems is rapidly increasing, designing an interconnect architecture with predictable behavior is essential for proper system operation. In CMPs, general-purpose processor cores are used to run software tasks of different applications and the communication between the cores cannot be precharacterized. Designing an efficient network-on-chip (NoC)-based interconnect with predictable performance is thus a challenging task. In this paper, we address the important design issue of synthesizing the most power efficient NoC interconnect for CMPs, providing guaranteed optimum throughput and predictable performance for any application to be executed on the CMP. In our synthesis approach, we use accurate delay and power models for the network components (switches and links) that are obtained from layouts of the components using industry standard tools. The synthesis approach utilizes the floorplan knowledge of the NoC to detect timing violations on the NoC links early in the design cycle. This leads to a faster design cycle and quicker design convergence across the high-level synthesis approach and the physical implementation of the design. We validate the design flow predictability of our proposed approach by performing a layout of the NoC synthesized for a 25-core CMP. Our approach maintains the regular and predictable structure of the NoC and is applicable in practice to existing NoC architectures.