Analytical drain thermal noise current model valid for deep submicron MOSFETs

In this paper, a physics-based MOSFET drain thermal noise current model valid for deep submicron channel lengths was derived and verified with experiments. It is found that the well-known /spl mu/Q/sub inv//L/sup 2/ formula, previously derived for long channels, remains valid for short channels. Carrier heating in the gradual channel region was taken into account implicitly with the form of diffusion noise source and then impedance field method taking velocity saturation effect was used to calculate the external drain thermal noise current. The derived model was verified by experimental noise for devices with channel lengths down to 0.18 /spl mu/m. Excellent agreement between measured and modeled drain thermal noise was obtained for the entire V/sub GS/ and V/sub DS/ bias regions.     

Modeling of drain current overshoot and recombination lifetimeextraction in floating-body submicron SOI MOSFETs

This work reports on a new general modeling of recombination-based mechanisms related to electrically floating-body partially-depleted (PD) SOI MOSFETs. The model describes drain current overshoots induced when turning on the transistor gate and suggests a novel extraction method for the recombination lifetime in the silicon film. We show that the recombination process associated with drain current overshoots in PD silicon-on-insulator (SOI) MOSFETs takes place mainly in the depletion region and not in the neutral region as in case of pulsed MOS capacitors. Associated with existing techniques for generation lifetime extraction, our model offers, for the first time, the possibility of complete and rapid characterization for both generation and recombination lifetime using drain current transients in floating-body SOI MOSFETs. The model is used in order to characterize submicron SOI devices, allowing a thorough investigation of technological parameters impact on floating-body-induced transient mechanisms     

Ga0.47In0.53As depletion mode MISFETs withnegligible drain current drift

Ga_0.47In_0.53As depletion-mode metal insulator semiconductor field-effect transistors with a transconductance in the range 100-140 mS/mm and with no significant current drift (less than 3% in 30 hours) have been fabricated on epitaxial layers grown by MOCVD. This high performance has been achieved using an efficient passivation of the GaInAs surface which associates in situ native oxide removal by a hydrogen multipolar plasma and a Si₃N₄ film deposition     

A new method to characterize border traps in submicron transistors using hysteresis in the drain current

In this paper, a new method for measuring border trap density (n/sub BT/) in submicron transistors using hysteresis in the drain current is proposed. This method is used to measure energy and spatial distribution of border traps in jet vapor deposited (JVD) metal-silicon nitride-semiconductor field effect transistors (MNSFETs). The drain current transient varies linearly with logarithmic time suggesting that tunneling to and from the spatially uniform border traps is the dominant charge exchange mechanism. Using a feedback mechanism gate voltage transients are obtained from which n/sub BT/ is calculated. The prestress energy distribution in JVD MNSFETs is found to be uniform whereas the post-stress energy distribution shows a peak near the midgap.     

Simulation of substrate current characteristics of submicron MOSFETs

A method for economical prediction of substrate currents in submicron-scale MOSFETs is described and validated by comparison of simulation and experimental results. Two-dimensional energy transport simulation is used to obtain average electron energies and temperature, and hole transport is described using the standard drift-diffusion method. Relatively little computation time is required to give a physically correct picture of device operation on a SUN 3/60 or equivalent workstation.<>     

Shallow source/drain extensions for deep submicron MOSFETs using spin-on-dopants

Spin-on-dopants and rapid thermal processing have been used to form ultra-shallow n/sup +/-p junctions with metallurgical junction depths as shallow as 12 nm as determined by secondary ion mass spectroscopy. The electrical junction depth and the total charge concentration have been measured in the vicinity of the junction using electron holography and are shown to be consistent with activation efficiencies of 80%. The ultra-shallow junctions have been used as the source and drain contacts of sub-100-nm gate length MOSFETs. From electrical measurements, the authors extract a lateral diffusion length for the source and drains that is comparable to the vertical extent of the n/sup +/-p junctions.     

Influence of the surface and the episubstrate interface on the drain current drift of GaAs MESFET's

Long-term drift of GaAs MESFET's under gate bias and under substrate bias was extensively investigated to discover whether the dominant cause of the phenomenon is due to the surface or the epi-substrate interface. It was found that the activation energy of the ordinary drain current drift under gate bias scatters greatly from 0.16 eV to 0.8 eV, depending on the amount of the drift, whereas the activation energy of the drift due to substrate bias is always constant at 0.82 eV. Ordinary drift under gate bias and its activation energy are greatly influenced by surface conditions, but drift due to substrate bias is not so influenced. Changes of the high frequency parameters are also different for each case. These results indicate that the drift in GaAs MESFET's performance, which has often been observed in the past, is dominated by surface conditions, probably mobile charges on the surface.     

A new drain current model for short-channel MOSFETs

Reduction of channel length makes the channel current to be less than that of drain current. In this paper, by using multiplication factor model [Proc. IEEE IRPS. (1996) 318, Proc. IEEE IRPS (1999) 167] and a simple approximation of the collector current of PBT the drain current in short-channel MOSFETs is modeled and simulated. This model makes use of four parameters, which by extracting them for each device, it is possible to calculate total drain current. The simulation results from this model are compared with the results obtained from MINIMOS, in which match observed between them.     

Simple model for the saturation voltage and current of submicron MOSFETs

A simple but reasonably accurate model is presented for the saturation voltage and current of submicron MOSFETs in strong inversion. Relevant device physics such as the effects of short channel, narrow channel, and the voltage drop along the channel caused by the drain voltage are accounted for in a first-order manner. The conventional model is also derived from the present model by employing several approximations. It is shown that the present model compares more favourably with PISCES device simulation results and that the conventional model can overestimate the saturation I-V characteristics by about 30% for a typical submicron MOSFET. We further suggest that the error caused by the conventional model is smaller for a MOSFET having a shorter channel, a wider channel, or/and a lower impurity doping concentration.     

On the drain current saturation in short channel MOSFETs

Submicron MOSFETs are the issue for ULSI integrated circuits. However, drastic reduction of device size leads to a complex modeling of the MOSFET drain current, which is affected by the electrical and physical phenomena induced by the low device dimension. Several current models are proposed to explain the drain current behavior in the saturation region of the I_D-V_D characteristic curve. Mainly, we can distinguish two types: long channel and short channel current modeling. In the present work, a survey of current voltage models is presented aiming a contribution to the interpretation of the current behavior in the saturation region of the I-V curves, i.e. non-saturation of the drain current, which are critical in submicronic devices.     

Hot-carrier-stress effects on gate-induced drain leakage current inn-channel MOSFETs

The effects of hot-carrier stress on gate-induced drain leakage (GIDL) current in n-channel MOSFETs with thin gate oxides are studied. It is found that the effects of generated interface traps (ΔD _it) and oxide trapped charge on the GIDL current enhancement are very different. Specifically, it is shown that the oxide trapped charge only shifts the flat-band voltage, unlike ΔD _it. Besides band-to-band (B-B) tunneling, ΔD _it introduces an additional trap-assisted leakage current component. Evidence for this extra component is provided by hole injection. While trapped-charge induced leakage current can be eliminated by a hole injection subsequent to stress, such injection does not suppress interface-trap-induced leakage current     

An analytical drain current model of short-channel MOSFETs including source/drain resistance effect

In this paper, the DC characteristics of MOSFETs are investigated by means of an analytical approach with considerations of the source/drain parasitic resistance (R _S/R _D). Experimental data of MOS devices for DRAM design and results of TCAD simulation are used to verify the accuracy of theoretical calculation. It is found that both the R _S and R _D can induce a large reduction in the drain current in the linear region, but only the source resistance can cause a large reduction in the drain current in the saturation region. Moreover, the drain current deduction due to the R _S/R _D increases with decreasing channel length and oxide thickness.     

Mechanism of drain current droop in GaAs MESFETs

The mechanisms responsible for the drain current droop in GaAs MESFETs are discussed and their relative contributions evaluated. Contrary to a common belief that the cause is mainly self-heating, it is shown on the example of a power MESFET that deep level effects (surface states and bulk traps) have a higher contribution     

Subthreshold surface potential and drain current models for short-channel pocket-implanted MOSFETs

An analytical subthreshold surface potential model for short-channel pocket-implanted (double-halo) MOSFET is presented. The effect of the depletion layers around the source and drain junctions on channel depletion layer depth, which is very important for short-channel devices, is included. Using this surface potential, a drift-diffusion based analytical subthreshold drain current model for short-channel pocket-implanted MOSFETs is also proposed. A physically-based empirical modification of the channel conduction layer thickness that was originally proposed for relatively long-channel conventional device is made for such short-channel double-halo devices. Very good agreement for both the surface potential and drain current is observed between the model calculation and the prediction made by the 2-D numerical device simulation using Dessis.     

Analytical modelling of ultra-thin film depletion-mode SOI MOSFETs

Reliable analytical models for thin and ultra-thin film depletion-mode SOI MOSFETs have been developed. These models are based on the linearly varying potential (LVP) approximation in the Si film. They allow the understanding and optimization of electrical properties of these devices. In particular, the behaviour of the subthreshold swing and the transconductance is discussed and compared successfully with numerical simulation.     

Drain current thermal noise modeling for deep submicron n- and p-channel MOSFETs

The drain current thermal noise has been measured and modeled for the short-channel devices fabricated with a standard 0.18 μm CMOS technology. We have derived a physics-based drain current thermal noise model for short-channel MOSFETs, which takes into account the velocity saturation effect and the carrier heating effect in gradual channel region. As a result, it is found that the well-known Q_inv/L²––formula, previously derived for long-channel, remains valid for even short-channel. The model excellently explained the carefully measured drain thermal noise for the entire V_GS and V_DS bias regions, not only in the n-channel, but also in the p-channel MOSFETs. Large excess noise, which was reported earlier in some other groups, was not observed in both the n-channel and the p-channel devices.     

The effect of the elevated source/drain doping profile onperformance and reliability of deep submicron MOSFETs

Deep submicron NMOSFETs with elevated source/drain (ESD) were fabricated using self-aligned selective epitaxial deposition and engineered ion implanted profiles in the elevated layers, Deeper source/drain (S/D) junctions give rise to improved drive current over shallower profiles when the same spacer thickness and LDD doping level are used, Shallower junctions, especially with the heavily-doped S/D residing in the elevated layer, give better immunity to drain-induced-barrier lowering (DLBL) and bulk punchthrough. Tradeoffs between short-channel behavior and drive current with regard to S/D junction depth and spacer thickness were further studied using process/device simulations to cover a broader range of structure parameters. Despite the existence of epi facets along the sidewall spacers, the elevated S/D could be used as a sacrificial layer for silicidation, without degradation of the low-leakage junctions. The effects of the elevated S/D doping profile on substrate current and hot-electron-induced degradation were measured and analyzed. The simulated results were used, for the first time, to define the range of spacer thickness and LDD doses that are required in order for the lightly-doped region in the elevated S/D to effectively suppress the lateral electric field     

Accurate modeling for drain breakdown current of GaAs MESFET's

Extensive measurements of a drain breakdown current as a function of device bias are reported in this paper. To represent the measured drain breakdown currents accurately, a new modeling function and an equivalent circuit controlled by two voltages are proposed. This model, when integrated into a large-signal analysis program, improves the accuracy of the simulation     

A surface potential based drain current model for asymmetric double gate MOSFETs

In this paper, we present a generic surface potential based current voltage (I-V) model for doped or undoped asymmetric double gate (DG) MOSFET. The model is derived from the 1-D Poisson’s equation with all the charge terms included and the channel potential is solved for the asymmetric operation of DG MOSFET based on the Newton-Raphson iterative method. A noncharge sheet based drain current model based on the Pao-Sah’s double integral method is formulated in terms of front and back gate surface potentials at the source and drain end. The model is able to clearly show the dependence of the front and back surface potential and the drain current on the terminal voltages, gate oxide thicknesses, channel doping concentrations and the Silicon body thickness and a good agreement is observed with the 2-D numerical simulation results.