风云三号卫星微波湿度计数据处理与系统控制的冗余设计方案

微波湿度计是风云三号卫星重要载荷之一,其中数据处理与系统控制单元是控制系统工作状态、数据采集和数据交换的核心部件,该单元的可靠性和安全性对微波湿度计至关重要。结合神舟四号多模态微波遥感器的研制经验,对冗余设计中通用的设计方案进行了分析和比较,详细介绍了风云三号卫星微波湿度计数据处理与系统控制所采用的冗余设计方案的选择依据、基本原理和特点。通过风云三号卫星微波湿度计的实际应用,该方案的可行性与可靠性得到了充分验证。     

基于MAP-CA的视频多点处理系统的研究与实现

文中介绍了一种高性能媒体信号处理器MAP-CA，它具备对视音频信号进行压缩处理的优化结构和多种方便的标准音视频接口。针对视频会议中视频信息的处理需求，以MAP—CA为核心处理器，设计了一个基于PC机的插卡式视频多点处理子系统，可应用于视频会议中多路码流的实时合成和转换，并且不会增加PC机负担。     

Proto-Perf：快速精确的通用处理器原型系统性能评估方法

性能验证及评估是通用处理器设计实现过程中最重要且必须实施的关键步骤之一.高效的通用处理器原型系统性能评估方法不仅可以帮助处理器设计人员在处理器设计阶段尽早地定位性能设计缺陷,而且还可以在设计流片前验证处理器能否达到性能设计预期.然而,对处理器原型系统进行完整的性能测试需要运行较长的时间,这样巨大的时间开销导致设计人员无法及时进行性能设计分析,进而导致处理器原型系统的性能评估成为整个项目的瓶颈.提出了一种快速精确的通用处理器原型系统性能评估方法Proto-Perf.Proto-Perf性能评估方法使用动态程序分析方法和基本块聚合技术抽取测试程序的特征程序片段进行测试,显著地缩短了性能测试时间.实验结果表明,相比于完整运行SPEC CPU2006 REF数据规模测试程序获得的性能数据,使用Proto-Perf测试得到的性能数据的绝对误差平均达到1.53％,其中最高达到7.86％.并且,对于实验中的每个程序,使用Proto-Perf方法进行测试的时间都明显缩短.     

IPSEC模块中输入/输出控制单元FPGA实现

本文提出了一种由FPGA实现IPSec协议数据的输入、输出控制单元的方案。文中介绍了该输入、输出控制单元的总体结构设计,详细阐述了该系统中主要子模块的的实现方法。尤其是对输入、输出控制单元中的关键部分——加密解密模块的实现方案,文中给出了具体设计细节。     

Dual-port RAMs simplify processor communications

Conventional memory blocks have a single address input and a single, usually bidirectional, data output. Dual-port memories have two address inputs and two data ports. These memories have been designed to facilitate the exchange of data between CPUs within a multiprocessor system. Each microprocessor can access the multiport memory and therefore read the data of another processor or leave data for another processor. There are two problems in the design of multiport memory systems. The first, and more trivial, concerns the way in which each processor supplies an address to the memory and how it accesses the memory data bus. This is not a particularly complex problem and the designer biggest worry is how to design the interface with the least number of multiplexers and buffers. Whenever a processor wishes to access the multiport memory, it takes control of the address and data bus and then accesses the memory. A more fundamental design problem is posed when two or more processors try to access the memory nearly simultaneously. Memory contention is solved by the use of an arbitration circuit that arbitrates between the contending processors, grants access to only one processor and forces the others to wait. Fortunately, it is no longer necessary for all designers to construct their own dual-port memories from discrete components, since several manufacturers now put the memory, address and data multiplexers plus arbitration circuits on chip. IDT's application note shows how its dual-port memory operates and how it is used in multiprocessor systems.     

Design of parallel conversion multichannel analog to digital converter for scan time reduction of programmable logic controller using FPGA

The execution speed of a programmable logic controller (PLC) depends upon the number of analog and digital input it scans, complication in ladder diagram and the time to store the ladder diagram outputs in memory. Next to the ladder diagram, scanning of analog signals consume enough time as they have to be converted into digital. The two facts that limit the conversion speed is that the processor used for analog signal scanning can process only one channel at a time and the multichannel analog to digital converter (ADC) has digital output for only one channel. The hardware nature of field programmable gate array (FPGA) allows simultaneous conversion of all the analog signals into digital and storage of digital data in block RAM. The proposed design discusses the design of multichannel ADC using FPGA. The simulation result shows that the conversion time of ‘n’ channel ADC is 13.17 μs. This increases the PLC execution speed.     

基于CORDIC算法的高精度浮点超越函数的FPGA实现

提出了一种新的输入输出浮点处理单元硬件架构,将数据从CORDIC算法内部格式转换为处理器能够支持的IEEE754标准浮点数据格式。输入数据支持2种不同的角度单位浮点数据直接输入,同时,硬件模块还直接支持超过360°的大角度数据输入。在Altera公司NiosⅡ处理器系统中以用户自定义指令的形式实现了该浮点硬件计算模块,并通过C语言程序验证了该模块的正确性。     

Box-Jenkins identification revisited—Part I: Theory

In classical time domain Box-Jenkins identification discrete-time plant and noise models are estimated using sampled input/output signals. The frequency content of the input/output samples covers uniformly the whole unit circle in a natural way, even in case of prefiltering. Recently, the classical time domain Box-Jenkins framework has been extended to frequency domain data captured in open loop. The proposed frequency domain maximum likelihood (ML) solution can handle (i) discrete-time models using data that only covers a part of the unit circle, and (ii) continuous-time models. Part I of this series of two papers (i) generalizes the frequency domain ML solution to the closed loop case, and (ii) proves the properties of the ML estimator under non-standard conditions. Contrary to the classical time domain case it is shown that the controller should be either known or estimated. The proposed ML estimators are applicable to frequency domain data as well as time domain data.     

SADDLE: A computer-aided structural analysis and dynamic design language—part II. database management system

The SADDLE program is a tool for computer-aided optimal design of structural and mechanical systems. The system is divided into four parts; the pre-processor, the “analyzer”, the “synthesizer” and the post-processor. The structural model and the design data are generated by the preprocessor. The analyzer used the finite-element method to compute deflections and stresses in the structure. The synthesizer solves the design problem that is cast into a nonlinear programming format. The post-processor is used to examine the analysis and design results. Different parts of the system interact via a global database. The database management system is presented in detail, in this part of a two part paper. The data manager has three distinct parts: the data model processor, the resource manager and the I/O manager. Both the relational and hierarchical data models are supported. Tuning parameters are provided to enhance computational efficiency on different computers. The emphasis is on friendlier user-system interaction; free-format input, error recoveries, and easy means to create, edit, and update information.     

Design of statistical databases: A methodology for the conceptual step

The aim of the conceptual step in database design is to describe data involving in the application in a formal and abstract way, without any concern to the specific model and language chosen for the implementation. In statistical applications, data are described at different levels of aggregation, from elementary facts of the reality to complex aggregations such as classifications, time series, indexes. The paper describes a methodology for conceptual design of statistical databases that provides the designer suitable strategies for defining such different levels of aggregation starting from user requirements, and checking the completeness, coherence and minimality of the conceptual schema at the different levels. The methodology makes use of two data models for the representation of data: for elementary data the Entity-Relationship model, widely used in database applications, and for summary data a new model is proposed, designed to be an effective trade-off between expressive power and simplicity of use.     

Dynamic routing of data stream tuples among parallel query plan running on multi-core processors

In this paper, a method for fast processing of data stream tuples in parallel execution of continuous queries over a multiprocessing environment is proposed. A copy of the query plan is assigned to each of processing units in the multiprocessing environment. Dynamic and continuous routing of input data stream tuples among the graph constructed by these copies (called the Query Mega Graph) for each input tuple determines that, after getting processed by each processing unit (e.g., processor), to which next processor it should be forwarded. Selection of the proper next processor is performed such that the destination processor imposes the minimum tuple latency to the corresponding tuple, among all of the alternative processors. The tuple latency is derived from processing, buffering and communication time delay which varies in different practical parallel systems.     

具有时变输入输出函数的反馈过程神经网络及应用

针对输入和输出均为时变函数或过程的实际系统建模和仿真问题,提出一种输入和输出均为时变函数的反馈过程神经网络模型,该模型的第1隐层对来自输入层的时变信号进行空间加权聚合和激励运算,并在将其输出传送至第2隐层的同时反馈至输入层;第2隐层完成对其时变输入的空间加权聚合、时间累积聚合和激励运算,并将其输出传送至输出层．给出了相应的学习算法,并以实例验证了该模型及其学习算法的有效性．     

一种数据交换方案的设计与实现

提出了在两个孤立的SQL Server数据库之间的自动数据交换的方案，每个数据库都有输入接口和输出接口，在输出接口中生成操作一个数据库的SQL语句，然后通过自行制订的协议传输到另一个数据库发布SQL语句，对数据库中的输入接口进行同样的SQL操作，从而达到数据交换的目的。方案通过Visual Basic平台和串行接口通信进行了实现，其中包括自行制订的数据抽取模式和简单传输协议。所提的方案在一定程度上对解决“数据孤岛”问题也有所帮助。     

具有以太网接口的变电站监控系统设计

本文介绍了具有工业以太网接口的变电站监控系统的设计与实现。提出了双CPU结构的变电站监控系统,数字信号处理器TMS320VC5402作为主CPU,用于以太网接口的控制管理,以及定时向上位计算机发送数据,同时读取下位数字信号处理器采集的数据。数字信号处理器TMS320LF2407A作为从CPU,用于键盘、显示的控制,开关量、脉冲量、电网频率、模拟量等数据的采集以及模拟量和继电器的输出控制。系统软件支持MAC,TCP/IP等协议规范,从而实现了监控系统的网络化。给出了数字信号处理器TMS320VC5402与以太网控制器RTL8019AS的硬件设计及嵌入式TCP/IP协议的汇编程序设计。     

基于多互联网络的并行信号处理系统

在并行处理系统中,处理节点之间的通信开销是制约处理机性能提高的主要瓶颈。该文提出一种以TMS320C641X数字信号处理器为核心的并行处理系统,设计了PCI总线、串口和包交换网络等多种并行互联网络,使得输入、输出、控制等多种数据流分离,在适合的网络上传输,可以提高传输效率,实现高性能DSP与高性能互联系统的结合。     

应用于OFDM系统中的高速FFT处理器设计

针对无线城域网中工作在2GHz~11GHz频带的IEEE802.16a标准,在实现其OFDM系统时提出一种高速而且经济的FFT处理器设计方案。设计中采用了Radix-4的频率抽取算法和并行的蝶型计算单元结构,而且将旋转因子预先存储在ROM中以提高处理器运行的速度。设计方案采用了单个蝶型运算单元以达到控制FFT处理器规模的目的。数据的输入与输出都共用一个存储器,这进一步节约了硬件资源损耗。     

基于NiosⅡ的视频采集与DVI成像研究及实现

采用FPGA作为视频采集控制和图像处理芯片,配置NiosⅡ软核,在FPGA片内完成图像处理和图像显示控制,简化了硬件电路和软件程序的设计。在FPGA片内编写视频采集时序,并配置NiosⅡ控制软核,模拟视频数据经视频解码芯片输出ITU-RBT.656格式数据送入FPGA,通过时序控制和NiosⅡ软核把视频解码数据依序存储在SSRAM中,并进行裁剪、交织、颜色处理。     

基于双核处理器的机敏结构振动主动控制器设计

针对分布植入式压电机敏结构振动主动控制技术需求,提出一种新型基于嵌入式架构的多通道振动响应控制器;该系统以嵌入式处理器(ARM)和数字信号处理器(DSP)为双处理器核心,ARM处理器上运行实时操作系统μC/OS-II,并提供人机接口单元和通信等功能,DSP处理器主要负责数据采集、算法运算和处理结果输出,整个系统充分结合了ARM处理器强大的中断处理能力和DSP处理器高效快速的数据处理能力;详细阐述系统总体设计思想、系统软硬件设计方案、系统构成与核心部件、功能指标和开发过程,以及实验测试设置与结果验证;设计开发与测试分析表明,该控制器性能良好且功能丰富,能够满足实际研究工作的需要。