Design tradeoffs between surface and buried-channel FET's

A study of the operation of surface- and buried-mode p-channel FET's is conducted. The buried-channel devices are fabricated using n-type polysilicon gates while the surface-channel devices employ p-type polysilicon gates. Using devices with different channel lengths (20 to 0.4 µm), threshold voltage lowering, subthreshold characteristics, transconductance, punchthrough, and body effects are compared over a wide range of background doping concentrations. In the study surface-channel devices were found to be more resistant to short-channel effects than their buried-channel counterparts independent of background doping concentration. Two-dimensional computer simulation revealed that buried-channel devices are more subject to drain-induced barrier lowering and bulk punchthrough. The body effect for the surface-channel device is lower than its counterpart at low background doping concentrations whereas the buried-channel device has a lower body effect at high background doping levels. The effective carrier mobility of buried-channel devices was found greater than that of surface devices. The net difference in the transconductance, however, is offset by the high parasitic diffusion resistance.     

The sensitivity of threshold voltage of ion-implanted MOSFET's to substrate doping and oxide thickness fluctuations

When the gate region of a MOSFET is implanted in order to adjust, the threshold voltage, the sensitivity of the threshold voltage to fluctuations in substrate doping will be affected. It is shown here that when the implanted ion is of the Same impurity type as the substrate, this sensitivity is lower than for a similar, unimplanted structure. However, the converse is found to he true when the implanted ion is of opposite type and the device is operating in a deep-depletion mode. The latter result has obvious importance in view of substrate–doping fluctuations over the surface of a single silicon wafer, and more so between many different wafers. The effect on the threshold voltage of oxide thickness variations is also investigated, and it is found there is a range of implant energy and dose over which the sensitivity can be very small. This is associated, however, with a sharp rise in the sensitivity outside this range.     

Numerical simulation study of current–voltage characteristics of a Schottky diode with inverse doped surface layer

The Poisson’s equation and drift–diffusion equations are used to simulate the current–voltage characteristics of Schottky diode with an inverse doped surface layer. The potential inside the bulk semiconductor near the metal–semiconductor contact is estimated by simultaneously solving these equations, and current as a function of bias through the Schottky diode is calculated for various inverse layer thicknesses and doping concentrations. The Schottky diode parameters are then extracted by fitting of simulated current–voltage data into thermionic emission diffusion equation. The obtained diode parameters are analyzed to study the effect of inverse layer thickness and doping concentration on the Schottky diode parameters and its behavior at low temperatures. It is shown that increase in inverse layer thickness and its doping concentration give rise to Schottky barrier height enhancement and a change in the ideality factor. The temperature dependences of Schottky barrier height and ideality factor are studied. The effect of temperature dependence of carrier mobility on the Schottky diode characteristics is also discussed.     

应变Si1-xGex沟道PMOSFET空穴局域化研究

为充分利用应变 Si Ge材料相对于 Si较高的空穴迁移率 ,研究了 Si/Si Ge/Si PMOSFET中垂直结构和参数同沟道开启及空穴分布之间的依赖关系。在理论分析的基础上 ,以数值模拟为手段 ,研究了栅氧化层厚度、Si帽层厚度、Si Ge层 Ge组分及厚度、缓冲层厚度及衬底掺杂浓度对阈值电压、交越电压和空穴分布的影响与作用 ,特别强调了 δ掺杂的意义。模拟和分析表明 ,栅氧化层厚度、Si帽层厚度、Si Ge层 Ge组分、衬底掺杂浓度及 δ掺杂剂量是决定空穴分布的主要因素 ,而 Si Ge层厚度、缓冲层厚度和隔离层厚度对空穴分布并不敏感。最后总结了沟道反型及空穴分布随垂直结构及参数变化的一般规律 ,为优化器件设计提供了参考。     

GaN基HEMT器件结构设计及其性能仿真北大核心

利用Silvaco TCAD器件模拟软件研究了AlGaN/GaN高电子迁移率晶体管(HEMT)器件势垒层的厚度、沟道宽长比和掺杂浓度对器件的转移特性和跨导曲线的影响。结果表明,器件势垒层厚度的变化可以调节器件的电流开关比和开启电压,实现由耗尽型器件向增强型器件的转变;沟道宽长比的改变可以调节器件的开启电压,并且随着沟道宽长比的增加,栅极电压控制量子阱中二维电子气的能力增强;势垒层适量掺杂提高了输出电流,并且使跨导的峰值增大,但过度掺杂会造成器件不易关断情况出现。     

SiGe沟道pMOSFET阈值电压模型

通过求解泊松方程,综合考虑短沟道效应和漏致势垒降低效应,建立了小尺寸S iG e沟道pM O SFET阈值电压模型,模拟结果和实验数据吻合良好。模拟分析表明,当S iG e沟道长度小于200 nm时,阈值电压受沟道长度、G e组份、衬底掺杂浓度、盖帽层厚度、栅氧化层厚度的影响较大。而对于500 nm以上的沟道长度,可忽略短沟道效应和漏致势垒降低效应对阈值电压的影响。     

Model Development for Analyzing 2DEG Sheet Charge Density and Threshold Voltage considering Interface DOS for AlInN/GaN MOSHEMT

A model predicting the behavior of various parameters, such as 2DEG sheet charge density and threshold voltage, with the variation of barrier thickness and oxide thickness considering interface density of states is presented. The mathematical dependence of these parameters is derived in conjunction with the interface density of states. The dependence of sheet charge density with the barrier thickness and with the oxide thickness is plotted and an insight into the barrier scaling properties of AlInN based MOSHEMTs is presented. The threshold voltage is also plotted with respect to barrier thickness and oxide thickness, which reveals the possibility of the enhancement mode operation of the device at low values of the interface DOS. The results are in good agreement with the fabricated device available in the literature.     

Two-carrier conduction in MOS tunnel—Oxides II—Theory

Analytic expressions describing electron and hole current flow in the metal/tunnel—oxide/n-silicon structure are derived. In the particular approach that is taken, the tunneling barrier presented by the SiO₂ layer is treated using a “thick-oxide” MOS model; i.e. a trapezoidal tunneling barrier is used. Rather than assume a constant tunneling probability, the dependence of the tunneling barrier on applied bias and on the minority carrier density at the semiconductor surface is also included. Calculations based on the resultant equations are found to be in good agreement with experimental observations, and to correctly predict the “current-multiplication” effect that occurs under conditions of minority carrier injection to the Si---SiO₂ interface [1].

The derived equations are used to simulate device behaviour under various experimental conditions, including the effects of minority carrier injection, non-zero flatband voltage, and changes in substrate doping concentration and temperature. In addition, device parameters such as barrier height and carrier effective mass are also investigated with regard to their effect on the resultant electron and hole tunneling currents.     

Temperature effects on trigate SOI MOSFETs

Trigate silicon-on-insulator (SOI) MOSFETs have been measured in the 5-400 K temperature range. The device fin width and height is 45 and 82 nm, respectively, and the p-type doping concentration in the channel is 6/spl times/10/sup 17/ cm/sup -3/. The subthreshold slope varies linearly with temperature as predicted by fully depleted SOI MOS theory. The mobility is phonon limited for temperatures larger than 100 K, while it is limited by surface roughness below that temperature. The corner effect, in which the device corners have a lower threshold voltage than the top and sidewall Si/SiO/sub 2/ interfaces, shows up at temperatures lower than 150 K.     

Design of enhanced Schottky-barrier AlGaAs/GaAs MODFET's using highly doped p+surface layers

The design and performance of enhanced Schottky-barrier height modulation-doped AlGaAs/GaAs field-effect transistors (ESMODFET's) is discussed. Results are presented showing that the addition of a thin highly doped p⁺layer under the gate can increase the forward biased gate turn-on voltage from 0.8 V (conventional MODFET) to as high as 1.6 V. A mathematical model is presented that predicts the thickness and doping of the heterostructure layers required to obtain a given threshold voltage and effective Schottky-barrier height. It is predicted that this enhanced Schottky barrier will allow increased gate-voltage swings and thus significantly improve the noise margin of enhancement-mode MODFET circuits.     

Reduction of threshold voltage sensitivity in SOI MOSFET's

The threshold voltage sensitivity, of fully depleted SOI MOSFET's to variations in SOI silicon film thickness was examined through both simulation and device experiments. The concept of designing the channel V_th implant to achieve a constant dose within the film, rather than a constant doping concentration, was studied for a given range of film thicknesses. Minimizing the variation in retained dose reduced the threshold voltage sensitivity to film thickness for the range of t_si examined. One-dimensional process simulations were performed to determine the optimal channel implant condition that would reduce the variation in retained dose using realistic process parameters for both NMOS and PMOS device processes. SOI NMOS transistors were fabricated. The experimental results confirmed the simulation findings and achieved a reduced threshold voltage sensitivity     

The p-n heterojunction quantum well APD: A new high-gain low-noise high speed photodetector suitable for lightwave communications and digital applications

A new Ga0.47In0.53As/Al0.48In0.52As multiquantum well avalanche photodiode, the APD, is presented that provides comparable signal-to-noise performance compared to either the doped quantum well APD or the p-n junction quantum well APD, but without carrier trapping effects even at very low overall applied electric fields. The device is made of repeated unit cells consisting of a p-n junction formed between two dissimilar materials followed by a nearly intrinsic wide-bandgap layer. As in the doped quantum well device, the asymmetric unit cell selectively heats the electron distribution much more than the hole distribution within the narrow-gap Ga0.47In0.53As layer leading to a greatly enhanced electron-to-hole ionization rates ratio. The most significant improvement over the doped and p-n junction quantum well devices is the lack of carrier trapping at the heterojunction without further engineering of the interface (compositional grading). Carrier trapping is avoided, thereby providing very high-speed performance even for low-voltage devices, by doping the narrow-gap layer. The resulting built-in field within the GaInAs layer is sufficiently large of itself that both electrons and holes are heated to energies large enough to overcome the potential barrier at the end of the quantum well. In this way, devices operating at 5 V bias can be built that will provide a gain of about 4 at large bandwidths, ~18 GHz.     

Analyses of LED nonlinear distortions

This paper treats LED nonlinear distortions of differential gain (DG) and differential phase (DP) theoretically. Possible origins and numerical analyses are presented for AlxGa1-xAs LED's, considering various junction structures; double-heterostructure, single-heterostructure, and homostructure. It is shown that homostructure is superior to the others in linearity. The double-heterostructure is superior in optical power generation and in high-speed modulation, if the same structure parameters are adopted. The effects on linearity of doping concentrations, thermal resistance, and carrier confinement breakdown due to insufficient heterointerface barrier height are analyzed. An experimental result is shown to confirm the analyses. The results obtained will contribute to linear LED design.     

Comparative analysis of hot electron injection and induced devicedegradation in scaled 0.1 μm SOI n-MOSFETs using Monte Carlosimulation

A self-consistent Monte Carlo (MC) simulator is employed to investigate and compare hot electron phenomena in three competing design strategies for 0.1 μm SOI n-MOSFETs operating under low voltage conditions, i.e., V_d considerably less than the Si-SiO₂ injection barrier height φ_b. Simulations of these designs reveal that non-local carrier transport effects and two-dimensional current how play a significant role in determining the relative rate and location of hot electron injection into both the front and back oxides. Specifically, simulations indicate that electron-electron interactions near the drain edge are a main source of electron energies exceeding φ_b. The hot electron injection distributions are then coupled with an empirical model to generate interface state distributions at both the front and back oxide interfaces. These interface states are incorporated into a drift-diffusion simulator to examine relative hot-electron-induced device degradation for the three 0.1 μm SOI designs. Simulations suggest that both the Si layer thickness and doping distribution affect device sensitivity to hot-electron-induced interface states. In particular, the simulations show that a decrease in the channel doping results in increased sensitivity to back oxide charge. In the comparison of the heavily-doped designs, the design with a thinner T_Si experiences significantly more hot-electron-induced oxide damage in the back oxide and more degradation from the charged states at the back interface     

Threshold voltage reduction model for buried channel PMOSFETs using quasi-2-D Poisson equation

A quasi-two-dimensional (2-D) threshold voltage reduction model for buried channel pMOSFETs is derived. In order to account for the coexistence of isoand anisotype junctions in a buried channel structure, we have incorporated charge sharing effect in the quasi-2-D Poisson model. The proposed model correctly predicts the effects of drain bias (V/sub DS/), counter doping layer thickness (x/sub CD/), counter doping concentration (N/sub CD/), substrate doping concentration (N/sub sub/) and source/drain junction depth (x/sub j/), and the new model performs satisfactorily in the sub-0.1 /spl mu/m regime. By using the proposed model on the threshold voltage reduction and subthreshold swing, we have obtained the process windows of the counter doping thickness and the substrate concentration. These process windows are very useful for predicting the scaling limit of the buried channel pMOSFET with known process conditions or systematic design of the buried channel pMOSFET.     

IGFET circuit performance-n-channel versus p-channel

The n-channel insulated-gate field-effect transistor offers a factor of 2 to 3.4 mobility advantage (depending on crystal orientation and substrate doping level) over p-channel devices. In addition, several advantages result from the fact that the work function difference between an aluminum gate and the silicon substrate is about -0.8 volt for a p substrate compared with about zero for an n substrate. In particular, this results in a low threshold voltage that allows the use of a substrate bias to adjust the threshold voltage over a useful design range resulting in an added flexibility in choice of thresholds and substrate doping, a reduction in the effect of source-substrate bias on device threshold, decreased junction capacitance, and larger parasitic thick-oxide thresholds for a given insulator thickness. The speed, power, and density advantages of the n-channel device are illustrated for logic and memory circuits using representative n- and p-channel device designs.     

Polysilicon quantization effects on the electrical properties of MOS transistors

The quantum-mechanical behavior of charge carriers at the polysilicon/oxide interface is investigated. It is shown that a dark space depleted of free carriers is created at the interface as a consequence of the abrupt potential energy barrier, which dominates the polysilicon capacitance and voltage drop in all regions of operation of modern MOS devices. Quantum-mechanical effects in polysilicon lead to a reduction in the gate capacitance in the same way as substrate quantization, and to a negative voltage shift, which is opposed to the positive shift caused by carrier quantization in the channel. Effects on the extraction of device physical parameters such as oxide thickness and polysilicon doping are also addressed.     

Theory of the GaInAs/AlInAs-doped quantum well APD: A new low-noise solid-state photodetector for lightwave communication systems

We present calculations of the electron and hole ionization coefficients, the excess noise factor, and gain for a doped quantum well APD made from the Al0.48In0.52As/Ga0.47In0.53As material systems. The ionization rates are calculated based on an ensemble Monte Carlo method. The effect of all of the device parameters, i.e., doping concentrations, layer widths, and the overall dc bias field, on the carrier ionization coefficients and the deterministic ionization probabilities,PandQ, is determined. These results in conjunction with recent noise theory results are utilized to determine an optimal device design that provides high gain at very low noise. A complete design including number of stages and individual stage design is presented for the lowest noise, highest gain device realizable in this system. It is anticipated that this device can be used as a new ultralow-noise high-gain receiver in lightwave communications systems.     

Submicrometer-channel CMOS for low-temperature operation

A 0.5-µm-channel CMOS design optimized for liquid-nitrogen temperature operation is described. Thin gate oxide (12.5 nm) and dual polysilicon work functions (n⁺-poly gate for n-channel and p⁺-poly for p-channel transistors) are used. The power supply voltage is chosen to be 2.5 V based on performance, hot-carrier effects, and power dissipation considerations. The doping profiles of the channel and the background (substrate or well) are chosen to optimize the mobility, substrate sensitivity, and junction capacitance with minimum process complexity. The reduced supply voltage enables the use of silicided shallow arsenic and boron junctions, without any intentional junction grading, to control short-channel effects and to reduce the parasitic series resistance at 77 K. The same self-aligned silicide over the polysilicon gate electrode reduces the sheet resistance (as low as 1 Ω/sq at 77 K) and provides the strapping between the gates of the complementary transistors. The design has been demonstrated by a simple n-well/p-substrate CMOS process with very good device characteristics and ring-oscillator performance at 77 K.     

A physically based analytical model for the threshold voltage of strained-Si n-MOSFETs

A physically based analytic model for the threshold voltage V/sub t/ of long-channel strained-Si--Si/sub 1-x/Ge/sub x/ n-MOSFETs is presented and confirmed using numerical simulations for a wide range of channel doping concentration, gate-oxide thicknesses, and strained-Si layer thicknesses. The threshold voltage is sensitive to both the electron affinity and bandgap of the strained-Si cap material and the relaxed-Si/sub 1-x/Ge/sub x/ substrate. It is shown that the threshold voltage difference between strained- and unstrained-Si devices increases with channel doping, but that the increase is mitigated by gate oxide thickness reduction. Strained Si devices with constant, high channel doping have a threshold voltage difference that is sensitive to Si cap thickness, for thicknesses below the equilibrium critical thickness for strain relaxation.